1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
7 * mpc8536ds board configuration file
13 #include "../board/freescale/common/ics307_clk.h"
16 #define CONFIG_RAMBOOT_SDCARD 1
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
20 #ifdef CONFIG_SPIFLASH
21 #define CONFIG_RAMBOOT_SPIFLASH 1
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
25 #ifndef CONFIG_RESET_VECTOR_ADDRESS
26 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
29 #ifndef CONFIG_SYS_MONITOR_BASE
30 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
33 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
34 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
35 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
39 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
43 #define CONFIG_ENV_OVERWRITE
45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
47 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
50 * These can be toggled for performance analysis, otherwise use default.
52 #define CONFIG_L2_CACHE /* toggle L2 cache */
53 #define CONFIG_BTB /* toggle branch predition */
55 #define CONFIG_ENABLE_36BIT_PHYS 1
57 #ifdef CONFIG_PHYS_64BIT
58 #define CONFIG_ADDR_MAP 1
59 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
62 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
66 * Config the L2 Cache as L2 SRAM
68 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
69 #ifdef CONFIG_PHYS_64BIT
70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
74 #define CONFIG_SYS_L2_SIZE (512 << 10)
75 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
77 #define CONFIG_SYS_CCSRBAR 0xffe00000
78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
80 #if defined(CONFIG_NAND_SPL)
81 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
85 #define CONFIG_VERY_BIG_RAM
86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
87 #define CONFIG_DDR_SPD
89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
96 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
98 /* I2C addresses of SPD EEPROMs */
99 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
100 #define CONFIG_SYS_SPD_BUS_NUM 1
102 /* These are used when DDR doesn't use SPD. */
103 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
104 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
105 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
106 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
107 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
108 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
109 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
110 #define CONFIG_SYS_DDR_MODE_1 0x00480432
111 #define CONFIG_SYS_DDR_MODE_2 0x00000000
112 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
113 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
114 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
115 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
116 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
117 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
118 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
120 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
121 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
122 #define CONFIG_SYS_DDR_SBE 0x00010000
124 /* Make sure required options are set */
125 #ifndef CONFIG_SPD_EEPROM
126 #error ("CONFIG_SPD_EEPROM is required")
129 #undef CONFIG_CLOCKS_IN_MHZ
132 * Memory map -- xxx -this is wrong, needs updating
134 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
135 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
136 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
137 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
139 * Localbus cacheable (TBD)
140 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
142 * Localbus non-cacheable
143 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
144 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
145 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
146 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
147 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
148 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
152 * Local Bus Definitions
154 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
155 #ifdef CONFIG_PHYS_64BIT
156 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
158 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
161 #define CONFIG_FLASH_BR_PRELIM \
162 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
163 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
165 #define CONFIG_SYS_BR1_PRELIM \
166 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
168 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
170 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
171 CONFIG_SYS_FLASH_BASE_PHYS }
172 #define CONFIG_SYS_FLASH_QUIET_TEST
173 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
175 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
176 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
177 #undef CONFIG_SYS_FLASH_CHECKSUM
178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
181 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
182 #define CONFIG_SYS_RAMBOOT
184 #undef CONFIG_SYS_RAMBOOT
187 #define CONFIG_SYS_FLASH_EMPTY_INFO
188 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
190 #define CONFIG_HWCONFIG /* enable hwconfig */
191 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
192 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
193 #ifdef CONFIG_PHYS_64BIT
194 #define PIXIS_BASE_PHYS 0xfffdf0000ull
196 #define PIXIS_BASE_PHYS PIXIS_BASE
199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
200 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
202 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
203 #define PIXIS_VER 0x1 /* Board version at offset 1 */
204 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
205 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
206 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
207 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
208 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
209 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
210 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
211 #define PIXIS_VCTL 0x10 /* VELA Control Register */
212 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
213 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
214 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
215 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
216 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
217 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
218 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
219 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
220 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
221 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
222 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
223 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
224 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
225 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
226 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
227 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
228 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
229 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
230 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
231 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
232 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
233 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
234 #define PIXIS_LED 0x25 /* LED Register */
236 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
238 /* old pixis referenced names */
239 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
240 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
241 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
243 #define CONFIG_SYS_INIT_RAM_LOCK 1
244 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
245 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
247 #define CONFIG_SYS_GBL_DATA_OFFSET \
248 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
249 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
251 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
252 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
254 #ifndef CONFIG_NAND_SPL
255 #define CONFIG_SYS_NAND_BASE 0xffa00000
256 #ifdef CONFIG_PHYS_64BIT
257 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
259 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
262 #define CONFIG_SYS_NAND_BASE 0xfff00000
263 #ifdef CONFIG_PHYS_64BIT
264 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
266 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
269 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
270 CONFIG_SYS_NAND_BASE + 0x40000, \
271 CONFIG_SYS_NAND_BASE + 0x80000, \
272 CONFIG_SYS_NAND_BASE + 0xC0000}
273 #define CONFIG_SYS_MAX_NAND_DEVICE 4
274 #define CONFIG_NAND_FSL_ELBC 1
275 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
277 /* NAND boot: 4K NAND loader config */
278 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
279 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
280 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
281 #define CONFIG_SYS_NAND_U_BOOT_START \
282 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
283 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
284 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
285 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
287 /* NAND flash config */
288 #define CONFIG_SYS_NAND_BR_PRELIM \
289 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
290 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
291 | BR_PS_8 /* Port Size = 8 bit */ \
292 | BR_MS_FCM /* MSEL = FCM */ \
294 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
295 | OR_FCM_PGS /* Large Page*/ \
303 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
304 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
305 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
306 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
308 #define CONFIG_SYS_BR4_PRELIM \
309 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
310 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
311 | BR_PS_8 /* Port Size = 8 bit */ \
312 | BR_MS_FCM /* MSEL = FCM */ \
314 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
315 #define CONFIG_SYS_BR5_PRELIM \
316 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
317 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
318 | BR_PS_8 /* Port Size = 8 bit */ \
319 | BR_MS_FCM /* MSEL = FCM */ \
321 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
323 #define CONFIG_SYS_BR6_PRELIM \
324 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
325 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
326 | BR_PS_8 /* Port Size = 8 bit */ \
327 | BR_MS_FCM /* MSEL = FCM */ \
329 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
331 /* Serial Port - controlled on board with jumper J8
335 #define CONFIG_SYS_NS16550_SERIAL
336 #define CONFIG_SYS_NS16550_REG_SIZE 1
337 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
338 #ifdef CONFIG_NAND_SPL
339 #define CONFIG_NS16550_MIN_FUNCTIONS
342 #define CONFIG_SYS_BAUDRATE_TABLE \
343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
351 #define CONFIG_SYS_I2C
352 #define CONFIG_SYS_I2C_FSL
353 #define CONFIG_SYS_FSL_I2C_SPEED 400000
354 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
355 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
356 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
357 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
358 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
359 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
364 #define CONFIG_ID_EEPROM
365 #ifdef CONFIG_ID_EEPROM
366 #define CONFIG_SYS_I2C_EEPROM_NXID
368 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
369 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
370 #define CONFIG_SYS_EEPROM_BUS_NUM 1
374 * Memory space is mapped 1-1, but I/O space must start from 0.
377 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
378 #ifdef CONFIG_PHYS_64BIT
379 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
380 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
382 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
383 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
385 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
386 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
387 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
388 #ifdef CONFIG_PHYS_64BIT
389 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
391 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
393 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
395 /* controller 1, Slot 1, tgtid 1, Base address a000 */
396 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
397 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
402 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
405 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
406 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
407 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
411 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
413 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
415 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
416 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
417 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
418 #ifdef CONFIG_PHYS_64BIT
419 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
420 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
422 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
423 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
425 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
426 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
427 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
428 #ifdef CONFIG_PHYS_64BIT
429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
431 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
433 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
435 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
436 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
437 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
438 #ifdef CONFIG_PHYS_64BIT
439 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
440 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
442 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
443 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
445 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
446 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
447 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
448 #ifdef CONFIG_PHYS_64BIT
449 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
451 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
453 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
455 #if defined(CONFIG_PCI)
456 /*PCIE video card used*/
457 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
459 /*PCI video card used*/
460 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
464 #if defined(CONFIG_VIDEO)
465 #define CONFIG_BIOSEMU
466 #define CONFIG_ATI_RADEON_FB
467 #define CONFIG_VIDEO_LOGO
468 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
471 #undef CONFIG_EEPRO100
474 #ifndef CONFIG_PCI_PNP
475 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
476 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
477 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
480 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
482 #endif /* CONFIG_PCI */
485 #define CONFIG_SYS_SATA_MAX_DEVICE 2
487 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
488 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
490 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
491 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
493 #ifdef CONFIG_FSL_SATA
497 #if defined(CONFIG_TSEC_ENET)
499 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
500 #define CONFIG_TSEC1 1
501 #define CONFIG_TSEC1_NAME "eTSEC1"
502 #define CONFIG_TSEC3 1
503 #define CONFIG_TSEC3_NAME "eTSEC3"
505 #define CONFIG_FSL_SGMII_RISER 1
506 #define SGMII_RISER_PHY_OFFSET 0x1c
508 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
509 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
511 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
512 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
514 #define TSEC1_PHYIDX 0
515 #define TSEC3_PHYIDX 0
517 #define CONFIG_ETHPRIME "eTSEC1"
519 #endif /* CONFIG_TSEC_ENET */
525 #if defined(CONFIG_SYS_RAMBOOT)
526 #if defined(CONFIG_RAMBOOT_SPIFLASH)
527 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
528 #define CONFIG_ENV_OFFSET 0xF0000
529 #define CONFIG_ENV_SECT_SIZE 0x10000
530 #elif defined(CONFIG_RAMBOOT_SDCARD)
531 #define CONFIG_FSL_FIXED_MMC_LOCATION
532 #define CONFIG_ENV_SIZE 0x2000
533 #define CONFIG_SYS_MMC_ENV_DEV 0
535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
536 #define CONFIG_ENV_SIZE 0x2000
539 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
540 #define CONFIG_ENV_SIZE 0x2000
541 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
544 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
545 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
547 #undef CONFIG_WATCHDOG /* watchdog disabled */
550 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
556 #define CONFIG_HAS_FSL_MPH_USB
557 #ifdef CONFIG_HAS_FSL_MPH_USB
558 #ifdef CONFIG_USB_EHCI_HCD
559 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
560 #define CONFIG_USB_EHCI_FSL
565 * Miscellaneous configurable options
567 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
570 * For booting Linux, the board info and command line data
571 * have to be in the first 64 MB of memory, since this is
572 * the maximum mapped by the Linux kernel during initialization.
574 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
575 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
577 #if defined(CONFIG_CMD_KGDB)
578 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
582 * Environment Configuration
585 /* The mac addresses for all ethernet interface */
586 #if defined(CONFIG_TSEC_ENET)
587 #define CONFIG_HAS_ETH0
588 #define CONFIG_HAS_ETH1
589 #define CONFIG_HAS_ETH2
590 #define CONFIG_HAS_ETH3
593 #define CONFIG_IPADDR 192.168.1.254
595 #define CONFIG_HOSTNAME "unknown"
596 #define CONFIG_ROOTPATH "/opt/nfsroot"
597 #define CONFIG_BOOTFILE "uImage"
598 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
600 #define CONFIG_SERVERIP 192.168.1.1
601 #define CONFIG_GATEWAYIP 192.168.1.1
602 #define CONFIG_NETMASK 255.255.255.0
604 /* default location for tftp and bootm */
605 #define CONFIG_LOADADDR 1000000
607 #define CONFIG_EXTRA_ENV_SETTINGS \
609 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
610 "tftpflash=tftpboot $loadaddr $uboot; " \
611 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
613 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
615 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
617 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
619 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
621 "consoledev=ttyS0\0" \
622 "ramdiskaddr=2000000\0" \
623 "ramdiskfile=8536ds/ramdisk.uboot\0" \
624 "fdtaddr=1e00000\0" \
625 "fdtfile=8536ds/mpc8536ds.dtb\0" \
627 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
629 #define CONFIG_HDBOOT \
630 "setenv bootargs root=/dev/$bdev rw " \
631 "console=$consoledev,$baudrate $othbootargs;" \
632 "tftp $loadaddr $bootfile;" \
633 "tftp $fdtaddr $fdtfile;" \
634 "bootm $loadaddr - $fdtaddr"
636 #define CONFIG_NFSBOOTCOMMAND \
637 "setenv bootargs root=/dev/nfs rw " \
638 "nfsroot=$serverip:$rootpath " \
639 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "tftp $loadaddr $bootfile;" \
642 "tftp $fdtaddr $fdtfile;" \
643 "bootm $loadaddr - $fdtaddr"
645 #define CONFIG_RAMBOOTCOMMAND \
646 "setenv bootargs root=/dev/ram rw " \
647 "console=$consoledev,$baudrate $othbootargs;" \
648 "tftp $ramdiskaddr $ramdiskfile;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr $ramdiskaddr $fdtaddr"
653 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
655 #endif /* __CONFIG_H */