2 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * mpc8536ds board configuration file
14 #include "../board/freescale/common/ics307_clk.h"
17 #define CONFIG_RAMBOOT_SDCARD 1
18 #define CONFIG_SYS_TEXT_BASE 0xf8f40000
19 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
22 #ifdef CONFIG_SPIFLASH
23 #define CONFIG_RAMBOOT_SPIFLASH 1
24 #define CONFIG_SYS_TEXT_BASE 0xf8f40000
25 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
28 #ifndef CONFIG_SYS_TEXT_BASE
29 #define CONFIG_SYS_TEXT_BASE 0xeff40000
32 #ifndef CONFIG_RESET_VECTOR_ADDRESS
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
36 #ifndef CONFIG_SYS_MONITOR_BASE
37 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
40 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
41 #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
42 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
43 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
44 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
45 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
46 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
47 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
48 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
51 #define CONFIG_TSEC_ENET /* tsec ethernet support */
52 #define CONFIG_ENV_OVERWRITE
54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
56 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
59 * These can be toggled for performance analysis, otherwise use default.
61 #define CONFIG_L2_CACHE /* toggle L2 cache */
62 #define CONFIG_BTB /* toggle branch predition */
64 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
66 #define CONFIG_ENABLE_36BIT_PHYS 1
68 #ifdef CONFIG_PHYS_64BIT
69 #define CONFIG_ADDR_MAP 1
70 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
73 #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
74 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
75 #define CONFIG_PANIC_HANG /* do not reset board on panic */
78 * Config the L2 Cache as L2 SRAM
80 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
81 #ifdef CONFIG_PHYS_64BIT
82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
84 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
86 #define CONFIG_SYS_L2_SIZE (512 << 10)
87 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
89 #define CONFIG_SYS_CCSRBAR 0xffe00000
90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
92 #if defined(CONFIG_NAND_SPL)
93 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
97 #define CONFIG_VERY_BIG_RAM
98 #undef CONFIG_FSL_DDR_INTERACTIVE
99 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
100 #define CONFIG_DDR_SPD
102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
108 #define CONFIG_NUM_DDR_CONTROLLERS 1
109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
110 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
112 /* I2C addresses of SPD EEPROMs */
113 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
114 #define CONFIG_SYS_SPD_BUS_NUM 1
116 /* These are used when DDR doesn't use SPD. */
117 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
118 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
119 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
121 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
122 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
123 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
124 #define CONFIG_SYS_DDR_MODE_1 0x00480432
125 #define CONFIG_SYS_DDR_MODE_2 0x00000000
126 #define CONFIG_SYS_DDR_INTERVAL 0x06180100
127 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
128 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
129 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
130 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
131 #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
132 #define CONFIG_SYS_DDR_CONTROL2 0x04400010
134 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
135 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
136 #define CONFIG_SYS_DDR_SBE 0x00010000
138 /* Make sure required options are set */
139 #ifndef CONFIG_SPD_EEPROM
140 #error ("CONFIG_SPD_EEPROM is required")
143 #undef CONFIG_CLOCKS_IN_MHZ
146 * Memory map -- xxx -this is wrong, needs updating
148 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
149 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
150 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
151 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
153 * Localbus cacheable (TBD)
154 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
156 * Localbus non-cacheable
157 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
158 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
159 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
160 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
161 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
162 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
166 * Local Bus Definitions
168 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
172 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
175 #define CONFIG_FLASH_BR_PRELIM \
176 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
177 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
179 #define CONFIG_SYS_BR1_PRELIM \
180 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
182 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
184 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
185 CONFIG_SYS_FLASH_BASE_PHYS }
186 #define CONFIG_SYS_FLASH_QUIET_TEST
187 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
190 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
191 #undef CONFIG_SYS_FLASH_CHECKSUM
192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
195 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
196 #define CONFIG_SYS_RAMBOOT
197 #define CONFIG_SYS_EXTRA_ENV_RELOC
199 #undef CONFIG_SYS_RAMBOOT
202 #define CONFIG_FLASH_CFI_DRIVER
203 #define CONFIG_SYS_FLASH_CFI
204 #define CONFIG_SYS_FLASH_EMPTY_INFO
205 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
207 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
209 #define CONFIG_HWCONFIG /* enable hwconfig */
210 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
211 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
212 #ifdef CONFIG_PHYS_64BIT
213 #define PIXIS_BASE_PHYS 0xfffdf0000ull
215 #define PIXIS_BASE_PHYS PIXIS_BASE
218 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
219 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
221 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
222 #define PIXIS_VER 0x1 /* Board version at offset 1 */
223 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
224 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
225 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
226 #define PIXIS_PWR 0x5 /* PIXIS Power status register */
227 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
228 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
229 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
230 #define PIXIS_VCTL 0x10 /* VELA Control Register */
231 #define PIXIS_VSTAT 0x11 /* VELA Status Register */
232 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
233 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
234 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
235 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
236 #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
237 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
238 #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
239 #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
240 #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
241 #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
242 #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
243 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
244 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
245 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
246 #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
247 #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
248 #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
249 #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
250 #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
251 #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
252 #define PIXIS_VWATCH 0x24 /* Watchdog Register */
253 #define PIXIS_LED 0x25 /* LED Register */
255 #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
257 /* old pixis referenced names */
258 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
259 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
260 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
262 #define CONFIG_SYS_INIT_RAM_LOCK 1
263 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
264 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
266 #define CONFIG_SYS_GBL_DATA_OFFSET \
267 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
268 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
270 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
271 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
273 #ifndef CONFIG_NAND_SPL
274 #define CONFIG_SYS_NAND_BASE 0xffa00000
275 #ifdef CONFIG_PHYS_64BIT
276 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
278 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
281 #define CONFIG_SYS_NAND_BASE 0xfff00000
282 #ifdef CONFIG_PHYS_64BIT
283 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
285 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
288 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
289 CONFIG_SYS_NAND_BASE + 0x40000, \
290 CONFIG_SYS_NAND_BASE + 0x80000, \
291 CONFIG_SYS_NAND_BASE + 0xC0000}
292 #define CONFIG_SYS_MAX_NAND_DEVICE 4
293 #define CONFIG_CMD_NAND 1
294 #define CONFIG_NAND_FSL_ELBC 1
295 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
297 /* NAND boot: 4K NAND loader config */
298 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
299 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
300 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
301 #define CONFIG_SYS_NAND_U_BOOT_START \
302 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
303 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
304 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
305 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
307 /* NAND flash config */
308 #define CONFIG_SYS_NAND_BR_PRELIM \
309 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
310 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
311 | BR_PS_8 /* Port Size = 8 bit */ \
312 | BR_MS_FCM /* MSEL = FCM */ \
314 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
315 | OR_FCM_PGS /* Large Page*/ \
323 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
324 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
325 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
326 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
328 #define CONFIG_SYS_BR4_PRELIM \
329 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
330 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
331 | BR_PS_8 /* Port Size = 8 bit */ \
332 | BR_MS_FCM /* MSEL = FCM */ \
334 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
335 #define CONFIG_SYS_BR5_PRELIM \
336 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
338 | BR_PS_8 /* Port Size = 8 bit */ \
339 | BR_MS_FCM /* MSEL = FCM */ \
341 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
343 #define CONFIG_SYS_BR6_PRELIM \
344 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
345 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
346 | BR_PS_8 /* Port Size = 8 bit */ \
347 | BR_MS_FCM /* MSEL = FCM */ \
349 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
351 /* Serial Port - controlled on board with jumper J8
355 #define CONFIG_CONS_INDEX 1
356 #define CONFIG_SYS_NS16550_SERIAL
357 #define CONFIG_SYS_NS16550_REG_SIZE 1
358 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
359 #ifdef CONFIG_NAND_SPL
360 #define CONFIG_NS16550_MIN_FUNCTIONS
363 #define CONFIG_SYS_BAUDRATE_TABLE \
364 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
366 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
367 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
372 #define CONFIG_SYS_I2C
373 #define CONFIG_SYS_I2C_FSL
374 #define CONFIG_SYS_FSL_I2C_SPEED 400000
375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
376 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
377 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
378 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
379 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
380 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
385 #define CONFIG_ID_EEPROM
386 #ifdef CONFIG_ID_EEPROM
387 #define CONFIG_SYS_I2C_EEPROM_NXID
389 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
390 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
391 #define CONFIG_SYS_EEPROM_BUS_NUM 1
394 * eSPI - Enhanced SPI
396 #define CONFIG_HARD_SPI
398 #if defined(CONFIG_SPI_FLASH)
399 #define CONFIG_SF_DEFAULT_SPEED 10000000
400 #define CONFIG_SF_DEFAULT_MODE 0
405 * Memory space is mapped 1-1, but I/O space must start from 0.
408 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
409 #ifdef CONFIG_PHYS_64BIT
410 #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
411 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
413 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
414 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
416 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
417 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
418 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
419 #ifdef CONFIG_PHYS_64BIT
420 #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
422 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
424 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
426 /* controller 1, Slot 1, tgtid 1, Base address a000 */
427 #define CONFIG_SYS_PCIE1_NAME "Slot 1"
428 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
429 #ifdef CONFIG_PHYS_64BIT
430 #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
433 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
434 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
436 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
437 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
438 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
439 #ifdef CONFIG_PHYS_64BIT
440 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
442 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
444 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
446 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
447 #define CONFIG_SYS_PCIE2_NAME "Slot 2"
448 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
449 #ifdef CONFIG_PHYS_64BIT
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
453 #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
454 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
456 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
457 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
458 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
459 #ifdef CONFIG_PHYS_64BIT
460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
464 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
466 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
467 #define CONFIG_SYS_PCIE3_NAME "Slot 3"
468 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
473 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
474 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
476 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
477 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
478 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
479 #ifdef CONFIG_PHYS_64BIT
480 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
482 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
484 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
486 #if defined(CONFIG_PCI)
487 /*PCIE video card used*/
488 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
490 /*PCI video card used*/
491 /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
495 #if defined(CONFIG_VIDEO)
496 #define CONFIG_BIOSEMU
497 #define CONFIG_ATI_RADEON_FB
498 #define CONFIG_VIDEO_LOGO
499 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
502 #undef CONFIG_EEPRO100
505 #ifndef CONFIG_PCI_PNP
506 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
507 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
508 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
511 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
513 #endif /* CONFIG_PCI */
516 #define CONFIG_LIBATA
517 #define CONFIG_FSL_SATA
519 #define CONFIG_SYS_SATA_MAX_DEVICE 2
521 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
522 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
524 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
525 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
527 #ifdef CONFIG_FSL_SATA
529 #define CONFIG_CMD_SATA
530 #define CONFIG_DOS_PARTITION
533 #if defined(CONFIG_TSEC_ENET)
535 #define CONFIG_MII 1 /* MII PHY management */
536 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
537 #define CONFIG_TSEC1 1
538 #define CONFIG_TSEC1_NAME "eTSEC1"
539 #define CONFIG_TSEC3 1
540 #define CONFIG_TSEC3_NAME "eTSEC3"
542 #define CONFIG_FSL_SGMII_RISER 1
543 #define SGMII_RISER_PHY_OFFSET 0x1c
545 #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
546 #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
548 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
549 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
551 #define TSEC1_PHYIDX 0
552 #define TSEC3_PHYIDX 0
554 #define CONFIG_ETHPRIME "eTSEC1"
556 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
558 #endif /* CONFIG_TSEC_ENET */
564 #if defined(CONFIG_SYS_RAMBOOT)
565 #if defined(CONFIG_RAMBOOT_SPIFLASH)
566 #define CONFIG_ENV_IS_IN_SPI_FLASH
567 #define CONFIG_ENV_SPI_BUS 0
568 #define CONFIG_ENV_SPI_CS 0
569 #define CONFIG_ENV_SPI_MAX_HZ 10000000
570 #define CONFIG_ENV_SPI_MODE 0
571 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
572 #define CONFIG_ENV_OFFSET 0xF0000
573 #define CONFIG_ENV_SECT_SIZE 0x10000
574 #elif defined(CONFIG_RAMBOOT_SDCARD)
575 #define CONFIG_ENV_IS_IN_MMC
576 #define CONFIG_FSL_FIXED_MMC_LOCATION
577 #define CONFIG_ENV_SIZE 0x2000
578 #define CONFIG_SYS_MMC_ENV_DEV 0
580 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
582 #define CONFIG_ENV_SIZE 0x2000
585 #define CONFIG_ENV_IS_IN_FLASH 1
586 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
587 #define CONFIG_ENV_SIZE 0x2000
588 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
591 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
592 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
595 * Command line configuration.
597 #define CONFIG_CMD_IRQ
598 #define CONFIG_CMD_IRQ
599 #define CONFIG_CMD_REGINFO
601 #if defined(CONFIG_PCI)
602 #define CONFIG_CMD_PCI
605 #undef CONFIG_WATCHDOG /* watchdog disabled */
608 #define CONFIG_FSL_ESDHC
609 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
610 #define CONFIG_GENERIC_MMC
616 #define CONFIG_HAS_FSL_MPH_USB
617 #ifdef CONFIG_HAS_FSL_MPH_USB
618 #define CONFIG_USB_EHCI
620 #ifdef CONFIG_USB_EHCI
621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
622 #define CONFIG_USB_EHCI_FSL
626 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
627 #define CONFIG_DOS_PARTITION
631 * Miscellaneous configurable options
633 #define CONFIG_SYS_LONGHELP /* undef to save memory */
634 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
635 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
636 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
637 #if defined(CONFIG_CMD_KGDB)
638 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
640 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
642 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
643 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
644 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
645 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
648 * For booting Linux, the board info and command line data
649 * have to be in the first 64 MB of memory, since this is
650 * the maximum mapped by the Linux kernel during initialization.
652 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
653 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
655 #if defined(CONFIG_CMD_KGDB)
656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
660 * Environment Configuration
663 /* The mac addresses for all ethernet interface */
664 #if defined(CONFIG_TSEC_ENET)
665 #define CONFIG_HAS_ETH0
666 #define CONFIG_HAS_ETH1
667 #define CONFIG_HAS_ETH2
668 #define CONFIG_HAS_ETH3
671 #define CONFIG_IPADDR 192.168.1.254
673 #define CONFIG_HOSTNAME unknown
674 #define CONFIG_ROOTPATH "/opt/nfsroot"
675 #define CONFIG_BOOTFILE "uImage"
676 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
678 #define CONFIG_SERVERIP 192.168.1.1
679 #define CONFIG_GATEWAYIP 192.168.1.1
680 #define CONFIG_NETMASK 255.255.255.0
682 /* default location for tftp and bootm */
683 #define CONFIG_LOADADDR 1000000
685 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
687 #define CONFIG_BAUDRATE 115200
689 #define CONFIG_EXTRA_ENV_SETTINGS \
691 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
692 "tftpflash=tftpboot $loadaddr $uboot; " \
693 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
695 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
697 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
699 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
701 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
703 "consoledev=ttyS0\0" \
704 "ramdiskaddr=2000000\0" \
705 "ramdiskfile=8536ds/ramdisk.uboot\0" \
706 "fdtaddr=1e00000\0" \
707 "fdtfile=8536ds/mpc8536ds.dtb\0" \
709 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
711 #define CONFIG_HDBOOT \
712 "setenv bootargs root=/dev/$bdev rw " \
713 "console=$consoledev,$baudrate $othbootargs;" \
714 "tftp $loadaddr $bootfile;" \
715 "tftp $fdtaddr $fdtfile;" \
716 "bootm $loadaddr - $fdtaddr"
718 #define CONFIG_NFSBOOTCOMMAND \
719 "setenv bootargs root=/dev/nfs rw " \
720 "nfsroot=$serverip:$rootpath " \
721 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
722 "console=$consoledev,$baudrate $othbootargs;" \
723 "tftp $loadaddr $bootfile;" \
724 "tftp $fdtaddr $fdtfile;" \
725 "bootm $loadaddr - $fdtaddr"
727 #define CONFIG_RAMBOOTCOMMAND \
728 "setenv bootargs root=/dev/ram rw " \
729 "console=$consoledev,$baudrate $othbootargs;" \
730 "tftp $ramdiskaddr $ramdiskfile;" \
731 "tftp $loadaddr $bootfile;" \
732 "tftp $fdtaddr $fdtfile;" \
733 "bootm $loadaddr $ramdiskaddr $fdtaddr"
735 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
737 #endif /* __CONFIG_H */