include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_HWCONFIG
  17
  18 /*
  19  * On-board devices
  20  */
  21 #define CONFIG_VSC7385_ENET
  22
  23 /*
  24  * Hardware Reset Configuration Word
  25  */
  26 #define CONFIG_SYS_HRCW_LOW (\
  27         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  28         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  29         HRCWL_SVCOD_DIV_2 |\
  30         HRCWL_CSB_TO_CLKIN_5X1 |\
  31         HRCWL_CORE_TO_CSB_2X1)
  32
  33 #ifdef CONFIG_PCISLAVE
  34 #define CONFIG_SYS_HRCW_HIGH (\
  35         HRCWH_PCI_AGENT |\
  36         HRCWH_PCI1_ARBITER_DISABLE |\
  37         HRCWH_CORE_ENABLE |\
  38         HRCWH_FROM_0XFFF00100 |\
  39         HRCWH_BOOTSEQ_DISABLE |\
  40         HRCWH_SW_WATCHDOG_DISABLE |\
  41         HRCWH_ROM_LOC_LOCAL_16BIT |\
  42         HRCWH_RL_EXT_LEGACY |\
  43         HRCWH_TSEC1M_IN_RGMII |\
  44         HRCWH_TSEC2M_IN_RGMII |\
  45         HRCWH_BIG_ENDIAN |\
  46         HRCWH_LDP_CLEAR)
  47 #else
  48 #define CONFIG_SYS_HRCW_HIGH (\
  49         HRCWH_PCI_HOST |\
  50         HRCWH_PCI1_ARBITER_ENABLE |\
  51         HRCWH_CORE_ENABLE |\
  52         HRCWH_FROM_0X00000100 |\
  53         HRCWH_BOOTSEQ_DISABLE |\
  54         HRCWH_SW_WATCHDOG_DISABLE |\
  55         HRCWH_ROM_LOC_LOCAL_16BIT |\
  56         HRCWH_RL_EXT_LEGACY |\
  57         HRCWH_TSEC1M_IN_RGMII |\
  58         HRCWH_TSEC2M_IN_RGMII |\
  59         HRCWH_BIG_ENDIAN |\
  60         HRCWH_LDP_CLEAR)
  61 #endif
  62
  63 /* System performance - define the value i.e. CONFIG_SYS_XXX
  64 */
  65
  66 /* Arbiter Configuration Register */
  67 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  68 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  69
  70 /* System Priority Control Regsiter */
  71 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  72
  73 /* System Clock Configuration Register */
  74 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  75 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  76 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  77
  78 /*
  79  * System IO Config
  80  */
  81 #define CONFIG_SYS_SICRH                0x08200000
  82 #define CONFIG_SYS_SICRL                0x00000000
  83
  84 /*
  85  * Output Buffer Impedance
  86  */
  87 #define CONFIG_SYS_OBIR         0x30100000
  88
  89 /*
  90  * IMMR new address
  91  */
  92 #define CONFIG_SYS_IMMR         0xE0000000
  93
  94 /*
  95  * Device configurations
  96  */
  97
  98 /* Vitesse 7385 */
  99
 100 #ifdef CONFIG_VSC7385_ENET
 101
 102 #define CONFIG_TSEC2
 103
 104 /* The flash address and size of the VSC7385 firmware image */
 105 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 106 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 107
 108 #endif
 109
 110 /*
 111  * DDR Setup
 112  */
 113 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 114 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 115 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 116 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 117 #define CONFIG_SYS_83XX_DDR_USES_CS0
 118
 119 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 120
 121 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 122 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 123
 124 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 125
 126 /*
 127  * Manually set up DDR parameters
 128  */
 129 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 130 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 131 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 132                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 133                                         | CSCONFIG_ROW_BIT_13 \
 134                                         | CSCONFIG_COL_BIT_10)
 135
 136 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 137 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 138                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 140                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 141                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 142                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 143                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 144                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 145                                 /* 0x00260802 */ /* DDR400 */
 146 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 147                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 148                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 149                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 150                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 151                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 152                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 153                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 154                                 /* 0x3937d322 */
 155 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 156                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 157                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 158                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 159                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 160                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 161                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 162                                 /* 0x02984cc8 */
 163
 164 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 165                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 166                                 /* 0x06090100 */
 167
 168 #if defined(CONFIG_DDR_2T_TIMING)
 169 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 170                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 171                                         | SDRAM_CFG_32_BE \
 172                                         | SDRAM_CFG_2T_EN)
 173                                         /* 0x43088000 */
 174 #else
 175 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 176                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 177                                         /* 0x43000000 */
 178 #endif
 179 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 180 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 181                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 182                                         /* 0x04400442 */ /* DDR400 */
 183 #define CONFIG_SYS_DDR_MODE2            0x00000000
 184
 185 /*
 186  * Memory test
 187  */
 188 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 189 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 190 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 191
 192 /*
 193  * The reserved memory
 194  */
 195 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 196
 197 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 198 #define CONFIG_SYS_RAMBOOT
 199 #else
 200 #undef  CONFIG_SYS_RAMBOOT
 201 #endif
 202
 203 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 204 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 205
 206 /*
 207  * Initial RAM Base Address Setup
 208  */
 209 #define CONFIG_SYS_INIT_RAM_LOCK        1
 210 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 211 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 212 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 213                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 214
 215 /*
 216  * Local Bus Configuration & Clock Setup
 217  */
 218 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 219 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 220 #define CONFIG_SYS_LBC_LBCR             0x00000000
 221 #define CONFIG_FSL_ELBC         1
 222
 223 /*
 224  * FLASH on the Local Bus
 225  */
 226 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 227 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 228
 229 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 230
 231                                         /* Window base at flash base */
 232 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 233 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 234
 235 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 236                                 | BR_PS_16      /* 16 bit port */ \
 237                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 238                                 | BR_V)         /* valid */
 239 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 240                                 | OR_GPCM_XACS \
 241                                 | OR_GPCM_SCY_9 \
 242                                 | OR_GPCM_EHTR_SET \
 243                                 | OR_GPCM_EAD)
 244                                 /* 0xFF800191 */
 245
 246 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 247 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 248
 249 #undef  CONFIG_SYS_FLASH_CHECKSUM
 250 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 251 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 252
 253 /*
 254  * NAND Flash on the Local Bus
 255  */
 256 #define CONFIG_SYS_NAND_BASE    0xE0600000
 257 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 258                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 259                                 | BR_PS_8               /* 8 bit port */ \
 260                                 | BR_MS_FCM             /* MSEL = FCM */ \
 261                                 | BR_V)                 /* valid */
 262 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 263                                 | OR_FCM_CSCT \
 264                                 | OR_FCM_CST \
 265                                 | OR_FCM_CHT \
 266                                 | OR_FCM_SCY_1 \
 267                                 | OR_FCM_TRLX \
 268                                 | OR_FCM_EHTR)
 269 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 270 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 271
 272 /* Vitesse 7385 */
 273
 274 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 275
 276 #ifdef CONFIG_VSC7385_ENET
 277
 278 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 279                                         | BR_PS_8 \
 280                                         | BR_MS_GPCM \
 281                                         | BR_V)
 282                                         /* 0xF0000801 */
 283 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 284                                         | OR_GPCM_CSNT \
 285                                         | OR_GPCM_XACS \
 286                                         | OR_GPCM_SCY_15 \
 287                                         | OR_GPCM_SETA \
 288                                         | OR_GPCM_TRLX_SET \
 289                                         | OR_GPCM_EHTR_SET \
 290                                         | OR_GPCM_EAD)
 291                                         /* 0xfffe09ff */
 292
 293                                         /* Access Base */
 294 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 295 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 296
 297 #endif
 298
 299 /*
 300  * Serial Port
 301  */
 302 #define CONFIG_SYS_NS16550_SERIAL
 303 #define CONFIG_SYS_NS16550_REG_SIZE     1
 304 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 305
 306 #define CONFIG_SYS_BAUDRATE_TABLE \
 307                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 308
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 311
 312 /* SERDES */
 313 #define CONFIG_FSL_SERDES
 314 #define CONFIG_FSL_SERDES1      0xe3000
 315 #define CONFIG_FSL_SERDES2      0xe3100
 316
 317 /* I2C */
 318 #define CONFIG_SYS_I2C
 319 #define CONFIG_SYS_I2C_FSL
 320 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 321 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 322 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 323 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 324
 325 /*
 326  * Config on-board RTC
 327  */
 328 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 329 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 330
 331 /*
 332  * General PCI
 333  * Addresses are mapped 1-1.
 334  */
 335 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 336 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 337 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 338 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 339 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 340 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 341 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 342 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 343 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 344
 345 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 346 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 347 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 348
 349 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 350 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 351 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 352 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 353 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 354 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 355 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 356 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 357 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 358
 359 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 360 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 361 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 362 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 363 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 364 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 365 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 366 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 367 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 368
 369 #ifdef CONFIG_PCI
 370 #define CONFIG_PCI_INDIRECT_BRIDGE
 371
 372 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 373 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 374 #endif  /* CONFIG_PCI */
 375
 376 /*
 377  * TSEC
 378  */
 379 #ifdef CONFIG_TSEC_ENET
 380
 381 #define CONFIG_GMII                     /* MII PHY management */
 382
 383 #define CONFIG_TSEC1
 384
 385 #ifdef CONFIG_TSEC1
 386 #define CONFIG_HAS_ETH0
 387 #define CONFIG_TSEC1_NAME               "TSEC0"
 388 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 389 #define TSEC1_PHY_ADDR                  2
 390 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 391 #define TSEC1_PHYIDX                    0
 392 #endif
 393
 394 #ifdef CONFIG_TSEC2
 395 #define CONFIG_HAS_ETH1
 396 #define CONFIG_TSEC2_NAME               "TSEC1"
 397 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 398 #define TSEC2_PHY_ADDR                  0x1c
 399 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 400 #define TSEC2_PHYIDX                    0
 401 #endif
 402
 403 /* Options are: TSEC[0-1] */
 404 #define CONFIG_ETHPRIME                 "TSEC0"
 405
 406 #endif
 407
 408 /*
 409  * SATA
 410  */
 411 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 412 #define CONFIG_SATA1
 413 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 414 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 415 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 416 #define CONFIG_SATA2
 417 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 418 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 419 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 420
 421 #ifdef CONFIG_FSL_SATA
 422 #define CONFIG_LBA48
 423 #endif
 424
 425 /*
 426  * Environment
 427  */
 428 #ifndef CONFIG_SYS_RAMBOOT
 429         #define CONFIG_ENV_ADDR         \
 430                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 431         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 432         #define CONFIG_ENV_SIZE         0x4000
 433 #else
 434         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 435         #define CONFIG_ENV_SIZE         0x2000
 436 #endif
 437
 438 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 439 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 440
 441 /*
 442  * BOOTP options
 443  */
 444 #define CONFIG_BOOTP_BOOTFILESIZE
 445
 446 /*
 447  * Command line configuration.
 448  */
 449
 450 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 451
 452 #ifdef CONFIG_MMC
 453 #define CONFIG_FSL_ESDHC_PIN_MUX
 454 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 455 #endif
 456
 457 /*
 458  * Miscellaneous configurable options
 459  */
 460 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 461
 462 /*
 463  * For booting Linux, the board info and command line data
 464  * have to be in the first 256 MB of memory, since this is
 465  * the maximum mapped by the Linux kernel during initialization.
 466  */
 467 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 468 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 469
 470 /*
 471  * Core HID Setup
 472  */
 473 #define CONFIG_SYS_HID0_INIT    0x000000000
 474 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 475                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 476 #define CONFIG_SYS_HID2         HID2_HBE
 477
 478 /*
 479  * MMU Setup
 480  */
 481
 482 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 483
 484 /* DDR: cache cacheable */
 485 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 486 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 487
 488 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 489                                 | BATL_PP_RW \
 490                                 | BATL_MEMCOHERENCE)
 491 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 492                                 | BATU_BL_256M \
 493                                 | BATU_VS \
 494                                 | BATU_VP)
 495 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 496 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 497
 498 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 499                                 | BATL_PP_RW \
 500                                 | BATL_MEMCOHERENCE)
 501 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 502                                 | BATU_BL_256M \
 503                                 | BATU_VS \
 504                                 | BATU_VP)
 505 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 506 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 507
 508 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 509 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 510                                 | BATL_PP_RW \
 511                                 | BATL_CACHEINHIBIT \
 512                                 | BATL_GUARDEDSTORAGE)
 513 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 514                                 | BATU_BL_8M \
 515                                 | BATU_VS \
 516                                 | BATU_VP)
 517 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 518 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 519
 520 /* L2 Switch: cache-inhibit and guarded */
 521 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 522                                 | BATL_PP_RW \
 523                                 | BATL_CACHEINHIBIT \
 524                                 | BATL_GUARDEDSTORAGE)
 525 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 526                                 | BATU_BL_128K \
 527                                 | BATU_VS \
 528                                 | BATU_VP)
 529 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 530 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 531
 532 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 533 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 534                                 | BATL_PP_RW \
 535                                 | BATL_MEMCOHERENCE)
 536 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 537                                 | BATU_BL_32M \
 538                                 | BATU_VS \
 539                                 | BATU_VP)
 540 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 541                                 | BATL_PP_RW \
 542                                 | BATL_CACHEINHIBIT \
 543                                 | BATL_GUARDEDSTORAGE)
 544 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 545
 546 /* Stack in dcache: cacheable, no memory coherence */
 547 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 548 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 549                                 | BATU_BL_128K \
 550                                 | BATU_VS \
 551                                 | BATU_VP)
 552 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 553 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 554
 555 #ifdef CONFIG_PCI
 556 /* PCI MEM space: cacheable */
 557 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 558                                 | BATL_PP_RW \
 559                                 | BATL_MEMCOHERENCE)
 560 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 561                                 | BATU_BL_256M \
 562                                 | BATU_VS \
 563                                 | BATU_VP)
 564 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 565 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 566 /* PCI MMIO space: cache-inhibit and guarded */
 567 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 568                                 | BATL_PP_RW \
 569                                 | BATL_CACHEINHIBIT \
 570                                 | BATL_GUARDEDSTORAGE)
 571 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 572                                 | BATU_BL_256M \
 573                                 | BATU_VS \
 574                                 | BATU_VP)
 575 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 576 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 577 #else
 578 #define CONFIG_SYS_IBAT6L       (0)
 579 #define CONFIG_SYS_IBAT6U       (0)
 580 #define CONFIG_SYS_IBAT7L       (0)
 581 #define CONFIG_SYS_IBAT7U       (0)
 582 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 583 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 584 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 585 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 586 #endif
 587
 588 #if defined(CONFIG_CMD_KGDB)
 589 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 590 #endif
 591
 592 /*
 593  * Environment Configuration
 594  */
 595 #define CONFIG_ENV_OVERWRITE
 596
 597 #define CONFIG_HAS_FSL_DR_USB
 598 #define CONFIG_USB_EHCI_FSL
 599 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 600
 601 #define CONFIG_NETDEV           "eth1"
 602
 603 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 604 #define CONFIG_ROOTPATH         "/nfsroot"
 605 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 606 #define CONFIG_BOOTFILE         "uImage"
 607                                 /* U-Boot image on TFTP server */
 608 #define CONFIG_UBOOTPATH        "u-boot.bin"
 609 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 610
 611                                 /* default location for tftp and bootm */
 612 #define CONFIG_LOADADDR         800000
 613
 614 #define CONFIG_EXTRA_ENV_SETTINGS \
 615         "netdev=" CONFIG_NETDEV "\0"                            \
 616         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 617         "tftpflash=tftp $loadaddr $uboot;"                              \
 618                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 619                         " +$filesize; " \
 620                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 621                         " +$filesize; " \
 622                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 623                         " $filesize; "  \
 624                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 625                         " +$filesize; " \
 626                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 627                         " $filesize\0"  \
 628         "fdtaddr=780000\0"                                              \
 629         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 630         "ramdiskaddr=1000000\0"                                         \
 631         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 632         "console=ttyS0\0"                                               \
 633         "setbootargs=setenv bootargs "                                  \
 634                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 635         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 636                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 637                                                         "$netdev:off "  \
 638                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 639
 640 #define CONFIG_NFSBOOTCOMMAND                                           \
 641         "setenv rootdev /dev/nfs;"                                      \
 642         "run setbootargs;"                                              \
 643         "run setipargs;"                                                \
 644         "tftp $loadaddr $bootfile;"                                     \
 645         "tftp $fdtaddr $fdtfile;"                                       \
 646         "bootm $loadaddr - $fdtaddr"
 647
 648 #define CONFIG_RAMBOOTCOMMAND                                           \
 649         "setenv rootdev /dev/ram;"                                      \
 650         "run setbootargs;"                                              \
 651         "tftp $ramdiskaddr $ramdiskfile;"                               \
 652         "tftp $loadaddr $bootfile;"                                     \
 653         "tftp $fdtaddr $fdtfile;"                                       \
 654         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 655
 656 #endif  /* __CONFIG_H */