Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / MPC837XERDB.h
1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1 /* E300 family */
16 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
17 #define CONFIG_MPC837XERDB      1
18 #define CONFIG_DISPLAY_BOARDINFO
19 #define CONFIG_SYS_GENERIC_BOARD
20
21 #define CONFIG_SYS_TEXT_BASE    0xFE000000
22
23 #define CONFIG_PCI      1
24
25 #define CONFIG_BOARD_EARLY_INIT_F
26 #define CONFIG_MISC_INIT_R
27 #define CONFIG_HWCONFIG
28
29 /*
30  * On-board devices
31  */
32 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
33 #define CONFIG_VSC7385_ENET
34
35 /*
36  * System Clock Setup
37  */
38 #ifdef CONFIG_PCISLAVE
39 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
40 #else
41 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
42 #define CONFIG_PCIE
43 #endif
44
45 #ifndef CONFIG_SYS_CLK_FREQ
46 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
47 #endif
48
49 /*
50  * Hardware Reset Configuration Word
51  */
52 #define CONFIG_SYS_HRCW_LOW (\
53         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54         HRCWL_DDR_TO_SCB_CLK_1X1 |\
55         HRCWL_SVCOD_DIV_2 |\
56         HRCWL_CSB_TO_CLKIN_5X1 |\
57         HRCWL_CORE_TO_CSB_2X1)
58
59 #ifdef CONFIG_PCISLAVE
60 #define CONFIG_SYS_HRCW_HIGH (\
61         HRCWH_PCI_AGENT |\
62         HRCWH_PCI1_ARBITER_DISABLE |\
63         HRCWH_CORE_ENABLE |\
64         HRCWH_FROM_0XFFF00100 |\
65         HRCWH_BOOTSEQ_DISABLE |\
66         HRCWH_SW_WATCHDOG_DISABLE |\
67         HRCWH_ROM_LOC_LOCAL_16BIT |\
68         HRCWH_RL_EXT_LEGACY |\
69         HRCWH_TSEC1M_IN_RGMII |\
70         HRCWH_TSEC2M_IN_RGMII |\
71         HRCWH_BIG_ENDIAN |\
72         HRCWH_LDP_CLEAR)
73 #else
74 #define CONFIG_SYS_HRCW_HIGH (\
75         HRCWH_PCI_HOST |\
76         HRCWH_PCI1_ARBITER_ENABLE |\
77         HRCWH_CORE_ENABLE |\
78         HRCWH_FROM_0X00000100 |\
79         HRCWH_BOOTSEQ_DISABLE |\
80         HRCWH_SW_WATCHDOG_DISABLE |\
81         HRCWH_ROM_LOC_LOCAL_16BIT |\
82         HRCWH_RL_EXT_LEGACY |\
83         HRCWH_TSEC1M_IN_RGMII |\
84         HRCWH_TSEC2M_IN_RGMII |\
85         HRCWH_BIG_ENDIAN |\
86         HRCWH_LDP_CLEAR)
87 #endif
88
89 /* System performance - define the value i.e. CONFIG_SYS_XXX
90 */
91
92 /* Arbiter Configuration Register */
93 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
94 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
95
96 /* System Priority Control Regsiter */
97 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
98
99 /* System Clock Configuration Register */
100 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
101 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
102 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
103
104 /*
105  * System IO Config
106  */
107 #define CONFIG_SYS_SICRH                0x08200000
108 #define CONFIG_SYS_SICRL                0x00000000
109
110 /*
111  * Output Buffer Impedance
112  */
113 #define CONFIG_SYS_OBIR         0x30100000
114
115 /*
116  * IMMR new address
117  */
118 #define CONFIG_SYS_IMMR         0xE0000000
119
120 /*
121  * Device configurations
122  */
123
124 /* Vitesse 7385 */
125
126 #ifdef CONFIG_VSC7385_ENET
127
128 #define CONFIG_TSEC2
129
130 /* The flash address and size of the VSC7385 firmware image */
131 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
132 #define CONFIG_VSC7385_IMAGE_SIZE       8192
133
134 #endif
135
136 /*
137  * DDR Setup
138  */
139 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
140 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
141 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
142 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
143 #define CONFIG_SYS_83XX_DDR_USES_CS0
144
145 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
146
147 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
148 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
149
150 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
151
152 /*
153  * Manually set up DDR parameters
154  */
155 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
156 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
157 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
158                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
159                                         | CSCONFIG_ROW_BIT_13 \
160                                         | CSCONFIG_COL_BIT_10)
161
162 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
163 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
164                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
165                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
166                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
167                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
168                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
169                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
170                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
171                                 /* 0x00260802 */ /* DDR400 */
172 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
173                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
174                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
175                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
176                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
177                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
178                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
179                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
180                                 /* 0x3937d322 */
181 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
182                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
183                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
184                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
185                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
186                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
187                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
188                                 /* 0x02984cc8 */
189
190 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
191                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
192                                 /* 0x06090100 */
193
194 #if defined(CONFIG_DDR_2T_TIMING)
195 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
196                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
197                                         | SDRAM_CFG_32_BE \
198                                         | SDRAM_CFG_2T_EN)
199                                         /* 0x43088000 */
200 #else
201 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
202                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
203                                         /* 0x43000000 */
204 #endif
205 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
206 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
207                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
208                                         /* 0x04400442 */ /* DDR400 */
209 #define CONFIG_SYS_DDR_MODE2            0x00000000
210
211 /*
212  * Memory test
213  */
214 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
215 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
216 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
217
218 /*
219  * The reserved memory
220  */
221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
222
223 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224 #define CONFIG_SYS_RAMBOOT
225 #else
226 #undef  CONFIG_SYS_RAMBOOT
227 #endif
228
229 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
230 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
231
232 /*
233  * Initial RAM Base Address Setup
234  */
235 #define CONFIG_SYS_INIT_RAM_LOCK        1
236 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
237 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
238 #define CONFIG_SYS_GBL_DATA_OFFSET      \
239                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
240
241 /*
242  * Local Bus Configuration & Clock Setup
243  */
244 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
245 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
246 #define CONFIG_SYS_LBC_LBCR             0x00000000
247 #define CONFIG_FSL_ELBC         1
248
249 /*
250  * FLASH on the Local Bus
251  */
252 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
253 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
254 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
255 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
256
257 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
258 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
259 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
260
261                                         /* Window base at flash base */
262 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
263 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
264
265 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
266                                 | BR_PS_16      /* 16 bit port */ \
267                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
268                                 | BR_V)         /* valid */
269 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
270                                 | OR_GPCM_XACS \
271                                 | OR_GPCM_SCY_9 \
272                                 | OR_GPCM_EHTR_SET \
273                                 | OR_GPCM_EAD)
274                                 /* 0xFF800191 */
275
276 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
277 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
278
279 #undef  CONFIG_SYS_FLASH_CHECKSUM
280 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
281 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
282
283 /*
284  * NAND Flash on the Local Bus
285  */
286 #define CONFIG_SYS_NAND_BASE    0xE0600000
287 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
288                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
289                                 | BR_PS_8               /* 8 bit port */ \
290                                 | BR_MS_FCM             /* MSEL = FCM */ \
291                                 | BR_V)                 /* valid */
292 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
293                                 | OR_FCM_CSCT \
294                                 | OR_FCM_CST \
295                                 | OR_FCM_CHT \
296                                 | OR_FCM_SCY_1 \
297                                 | OR_FCM_TRLX \
298                                 | OR_FCM_EHTR)
299 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
300 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
301
302 /* Vitesse 7385 */
303
304 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
305
306 #ifdef CONFIG_VSC7385_ENET
307
308 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
309                                         | BR_PS_8 \
310                                         | BR_MS_GPCM \
311                                         | BR_V)
312                                         /* 0xF0000801 */
313 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
314                                         | OR_GPCM_CSNT \
315                                         | OR_GPCM_XACS \
316                                         | OR_GPCM_SCY_15 \
317                                         | OR_GPCM_SETA \
318                                         | OR_GPCM_TRLX_SET \
319                                         | OR_GPCM_EHTR_SET \
320                                         | OR_GPCM_EAD)
321                                         /* 0xfffe09ff */
322
323                                         /* Access Base */
324 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
325 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
326
327 #endif
328
329 /*
330  * Serial Port
331  */
332 #define CONFIG_CONS_INDEX       1
333 #define CONFIG_SYS_NS16550
334 #define CONFIG_SYS_NS16550_SERIAL
335 #define CONFIG_SYS_NS16550_REG_SIZE     1
336 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
337
338 #define CONFIG_SYS_BAUDRATE_TABLE \
339                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
340
341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
343
344 /* SERDES */
345 #define CONFIG_FSL_SERDES
346 #define CONFIG_FSL_SERDES1      0xe3000
347 #define CONFIG_FSL_SERDES2      0xe3100
348
349 /* Use the HUSH parser */
350 #define CONFIG_SYS_HUSH_PARSER
351
352 /* Pass open firmware flat tree */
353 #define CONFIG_OF_LIBFDT        1
354 #define CONFIG_OF_BOARD_SETUP   1
355 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
356
357 /* I2C */
358 #define CONFIG_SYS_I2C
359 #define CONFIG_SYS_I2C_FSL
360 #define CONFIG_SYS_FSL_I2C_SPEED        400000
361 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
362 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
363 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
364
365 /*
366  * Config on-board RTC
367  */
368 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
369 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
370
371 /*
372  * General PCI
373  * Addresses are mapped 1-1.
374  */
375 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
376 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
377 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
378 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
379 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
380 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
381 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
382 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
383 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
384
385 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
386 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
387 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
388
389 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
390 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
391 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
392 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
393 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
394 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
395 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
396 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
397 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
398
399 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
400 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
401 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
402 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
403 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
404 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
405 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
406 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
407 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
408
409 #ifdef CONFIG_PCI
410 #define CONFIG_PCI_INDIRECT_BRIDGE
411 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
412
413 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
414 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
415 #endif  /* CONFIG_PCI */
416
417 /*
418  * TSEC
419  */
420 #ifdef CONFIG_TSEC_ENET
421
422 #define CONFIG_GMII                     /* MII PHY management */
423
424 #define CONFIG_TSEC1
425
426 #ifdef CONFIG_TSEC1
427 #define CONFIG_HAS_ETH0
428 #define CONFIG_TSEC1_NAME               "TSEC0"
429 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
430 #define TSEC1_PHY_ADDR                  2
431 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
432 #define TSEC1_PHYIDX                    0
433 #endif
434
435 #ifdef CONFIG_TSEC2
436 #define CONFIG_HAS_ETH1
437 #define CONFIG_TSEC2_NAME               "TSEC1"
438 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
439 #define TSEC2_PHY_ADDR                  0x1c
440 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
441 #define TSEC2_PHYIDX                    0
442 #endif
443
444 /* Options are: TSEC[0-1] */
445 #define CONFIG_ETHPRIME                 "TSEC0"
446
447 #endif
448
449 /*
450  * SATA
451  */
452 #define CONFIG_LIBATA
453 #define CONFIG_FSL_SATA
454
455 #define CONFIG_SYS_SATA_MAX_DEVICE      2
456 #define CONFIG_SATA1
457 #define CONFIG_SYS_SATA1_OFFSET 0x18000
458 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
459 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
460 #define CONFIG_SATA2
461 #define CONFIG_SYS_SATA2_OFFSET 0x19000
462 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
463 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
464
465 #ifdef CONFIG_FSL_SATA
466 #define CONFIG_LBA48
467 #define CONFIG_CMD_SATA
468 #define CONFIG_DOS_PARTITION
469 #define CONFIG_CMD_EXT2
470 #endif
471
472 /*
473  * Environment
474  */
475 #ifndef CONFIG_SYS_RAMBOOT
476         #define CONFIG_ENV_IS_IN_FLASH  1
477         #define CONFIG_ENV_ADDR         \
478                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
479         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
480         #define CONFIG_ENV_SIZE         0x4000
481 #else
482         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
483         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
484         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
485         #define CONFIG_ENV_SIZE         0x2000
486 #endif
487
488 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
489 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
490
491 /*
492  * BOOTP options
493  */
494 #define CONFIG_BOOTP_BOOTFILESIZE
495 #define CONFIG_BOOTP_BOOTPATH
496 #define CONFIG_BOOTP_GATEWAY
497 #define CONFIG_BOOTP_HOSTNAME
498
499
500 /*
501  * Command line configuration.
502  */
503 #include <config_cmd_default.h>
504
505 #define CONFIG_CMD_PING
506 #define CONFIG_CMD_I2C
507 #define CONFIG_CMD_MII
508 #define CONFIG_CMD_DATE
509
510 #if defined(CONFIG_PCI)
511 #define CONFIG_CMD_PCI
512 #endif
513
514 #if defined(CONFIG_SYS_RAMBOOT)
515 #undef CONFIG_CMD_SAVEENV
516 #undef CONFIG_CMD_LOADS
517 #endif
518
519 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
520 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
521
522 #undef CONFIG_WATCHDOG          /* watchdog disabled */
523
524 #define CONFIG_MMC     1
525
526 #ifdef CONFIG_MMC
527 #define CONFIG_FSL_ESDHC
528 #define CONFIG_FSL_ESDHC_PIN_MUX
529 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
530 #define CONFIG_CMD_MMC
531 #define CONFIG_GENERIC_MMC
532 #define CONFIG_CMD_EXT2
533 #define CONFIG_CMD_FAT
534 #define CONFIG_DOS_PARTITION
535 #endif
536
537 /*
538  * Miscellaneous configurable options
539  */
540 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
541 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
542
543 #if defined(CONFIG_CMD_KGDB)
544         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
545 #else
546         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
547 #endif
548
549                                 /* Print Buffer Size */
550 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
551 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
552                                 /* Boot Argument Buffer Size */
553 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
554
555 /*
556  * For booting Linux, the board info and command line data
557  * have to be in the first 256 MB of memory, since this is
558  * the maximum mapped by the Linux kernel during initialization.
559  */
560 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
561
562 /*
563  * Core HID Setup
564  */
565 #define CONFIG_SYS_HID0_INIT    0x000000000
566 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
567                                 | HID0_ENABLE_INSTRUCTION_CACHE)
568 #define CONFIG_SYS_HID2         HID2_HBE
569
570 /*
571  * MMU Setup
572  */
573
574 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
575
576 /* DDR: cache cacheable */
577 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
578 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
579
580 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
581                                 | BATL_PP_RW \
582                                 | BATL_MEMCOHERENCE)
583 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
584                                 | BATU_BL_256M \
585                                 | BATU_VS \
586                                 | BATU_VP)
587 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
588 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
589
590 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
591                                 | BATL_PP_RW \
592                                 | BATL_MEMCOHERENCE)
593 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
594                                 | BATU_BL_256M \
595                                 | BATU_VS \
596                                 | BATU_VP)
597 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
598 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
599
600 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
601 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
602                                 | BATL_PP_RW \
603                                 | BATL_CACHEINHIBIT \
604                                 | BATL_GUARDEDSTORAGE)
605 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
606                                 | BATU_BL_8M \
607                                 | BATU_VS \
608                                 | BATU_VP)
609 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
610 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
611
612 /* L2 Switch: cache-inhibit and guarded */
613 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
614                                 | BATL_PP_RW \
615                                 | BATL_CACHEINHIBIT \
616                                 | BATL_GUARDEDSTORAGE)
617 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
618                                 | BATU_BL_128K \
619                                 | BATU_VS \
620                                 | BATU_VP)
621 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
622 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
623
624 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
625 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
626                                 | BATL_PP_RW \
627                                 | BATL_MEMCOHERENCE)
628 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
629                                 | BATU_BL_32M \
630                                 | BATU_VS \
631                                 | BATU_VP)
632 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
633                                 | BATL_PP_RW \
634                                 | BATL_CACHEINHIBIT \
635                                 | BATL_GUARDEDSTORAGE)
636 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
637
638 /* Stack in dcache: cacheable, no memory coherence */
639 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
640 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
641                                 | BATU_BL_128K \
642                                 | BATU_VS \
643                                 | BATU_VP)
644 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
645 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
646
647 #ifdef CONFIG_PCI
648 /* PCI MEM space: cacheable */
649 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
650                                 | BATL_PP_RW \
651                                 | BATL_MEMCOHERENCE)
652 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
653                                 | BATU_BL_256M \
654                                 | BATU_VS \
655                                 | BATU_VP)
656 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
657 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
658 /* PCI MMIO space: cache-inhibit and guarded */
659 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
660                                 | BATL_PP_RW \
661                                 | BATL_CACHEINHIBIT \
662                                 | BATL_GUARDEDSTORAGE)
663 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
664                                 | BATU_BL_256M \
665                                 | BATU_VS \
666                                 | BATU_VP)
667 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
668 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
669 #else
670 #define CONFIG_SYS_IBAT6L       (0)
671 #define CONFIG_SYS_IBAT6U       (0)
672 #define CONFIG_SYS_IBAT7L       (0)
673 #define CONFIG_SYS_IBAT7U       (0)
674 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
675 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
676 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
677 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
678 #endif
679
680 #if defined(CONFIG_CMD_KGDB)
681 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
682 #endif
683
684 /*
685  * Environment Configuration
686  */
687 #define CONFIG_ENV_OVERWRITE
688
689 #define CONFIG_HAS_FSL_DR_USB
690 #define CONFIG_CMD_USB
691 #define CONFIG_USB_STORAGE
692 #define CONFIG_USB_EHCI
693 #define CONFIG_USB_EHCI_FSL
694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
695
696 #define CONFIG_NETDEV           "eth1"
697
698 #define CONFIG_HOSTNAME         mpc837x_rdb
699 #define CONFIG_ROOTPATH         "/nfsroot"
700 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
701 #define CONFIG_BOOTFILE         "uImage"
702                                 /* U-Boot image on TFTP server */
703 #define CONFIG_UBOOTPATH        "u-boot.bin"
704 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
705
706                                 /* default location for tftp and bootm */
707 #define CONFIG_LOADADDR         800000
708 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
709 #define CONFIG_BAUDRATE         115200
710
711 #define CONFIG_EXTRA_ENV_SETTINGS \
712         "netdev=" CONFIG_NETDEV "\0"                            \
713         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
714         "tftpflash=tftp $loadaddr $uboot;"                              \
715                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
716                         " +$filesize; " \
717                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
718                         " +$filesize; " \
719                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
720                         " $filesize; "  \
721                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
722                         " +$filesize; " \
723                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
724                         " $filesize\0"  \
725         "fdtaddr=780000\0"                                              \
726         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
727         "ramdiskaddr=1000000\0"                                         \
728         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
729         "console=ttyS0\0"                                               \
730         "setbootargs=setenv bootargs "                                  \
731                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
732         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
733                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
734                                                         "$netdev:off "  \
735                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
736
737 #define CONFIG_NFSBOOTCOMMAND                                           \
738         "setenv rootdev /dev/nfs;"                                      \
739         "run setbootargs;"                                              \
740         "run setipargs;"                                                \
741         "tftp $loadaddr $bootfile;"                                     \
742         "tftp $fdtaddr $fdtfile;"                                       \
743         "bootm $loadaddr - $fdtaddr"
744
745 #define CONFIG_RAMBOOTCOMMAND                                           \
746         "setenv rootdev /dev/ram;"                                      \
747         "run setbootargs;"                                              \
748         "tftp $ramdiskaddr $ramdiskfile;"                               \
749         "tftp $loadaddr $bootfile;"                                     \
750         "tftp $fdtaddr $fdtfile;"                                       \
751         "bootm $loadaddr $ramdiskaddr $fdtaddr"
752
753 #endif  /* __CONFIG_H */