1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_HWCONFIG
21 #define CONFIG_VSC7385_ENET
23 /* System performance - define the value i.e. CONFIG_SYS_XXX
26 /* System Clock Configuration Register */
27 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
28 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
29 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
34 #define CONFIG_SYS_SICRH 0x08200000
35 #define CONFIG_SYS_SICRL 0x00000000
38 * Output Buffer Impedance
40 #define CONFIG_SYS_OBIR 0x30100000
43 * Device configurations
48 #ifdef CONFIG_VSC7385_ENET
52 /* The flash address and size of the VSC7385 firmware image */
53 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
54 #define CONFIG_VSC7385_IMAGE_SIZE 8192
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
62 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
63 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
64 #define CONFIG_SYS_83XX_DDR_USES_CS0
66 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
68 #undef CONFIG_DDR_ECC /* support DDR ECC function */
69 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
71 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
74 * Manually set up DDR parameters
76 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
77 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
78 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
79 | CSCONFIG_ODT_WR_ONLY_CURRENT \
80 | CSCONFIG_ROW_BIT_13 \
81 | CSCONFIG_COL_BIT_10)
83 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
84 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
85 | (0 << TIMING_CFG0_WRT_SHIFT) \
86 | (0 << TIMING_CFG0_RRT_SHIFT) \
87 | (0 << TIMING_CFG0_WWT_SHIFT) \
88 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
89 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
90 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
91 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
92 /* 0x00260802 */ /* DDR400 */
93 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
94 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
95 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
96 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
97 | (13 << TIMING_CFG1_REFREC_SHIFT) \
98 | (3 << TIMING_CFG1_WRREC_SHIFT) \
99 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
100 | (2 << TIMING_CFG1_WRTORD_SHIFT))
102 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
103 | (5 << TIMING_CFG2_CPO_SHIFT) \
104 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
105 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
106 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
107 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
108 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
111 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
112 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
115 #if defined(CONFIG_DDR_2T_TIMING)
116 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
117 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
122 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
123 | SDRAM_CFG_SDRAM_TYPE_DDR2)
126 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
127 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
128 | (0x0442 << SDRAM_MODE_SD_SHIFT))
129 /* 0x04400442 */ /* DDR400 */
130 #define CONFIG_SYS_DDR_MODE2 0x00000000
135 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
136 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
137 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
140 * The reserved memory
142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
144 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
145 #define CONFIG_SYS_RAMBOOT
147 #undef CONFIG_SYS_RAMBOOT
150 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
151 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
154 * Initial RAM Base Address Setup
156 #define CONFIG_SYS_INIT_RAM_LOCK 1
157 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
158 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
159 #define CONFIG_SYS_GBL_DATA_OFFSET \
160 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
163 * Local Bus Configuration & Clock Setup
165 #define CONFIG_SYS_LBC_LBCR 0x00000000
166 #define CONFIG_FSL_ELBC 1
169 * FLASH on the Local Bus
171 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
172 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
174 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
178 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
180 #undef CONFIG_SYS_FLASH_CHECKSUM
181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
185 * NAND Flash on the Local Bus
187 #define CONFIG_SYS_NAND_BASE 0xE0600000
192 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
194 #ifdef CONFIG_VSC7385_ENET
202 #define CONFIG_SYS_NS16550_SERIAL
203 #define CONFIG_SYS_NS16550_REG_SIZE 1
204 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
206 #define CONFIG_SYS_BAUDRATE_TABLE \
207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
213 #define CONFIG_FSL_SERDES
214 #define CONFIG_FSL_SERDES1 0xe3000
215 #define CONFIG_FSL_SERDES2 0xe3100
218 #define CONFIG_SYS_I2C
219 #define CONFIG_SYS_I2C_FSL
220 #define CONFIG_SYS_FSL_I2C_SPEED 400000
221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
223 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
226 * Config on-board RTC
228 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
229 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
233 * Addresses are mapped 1-1.
235 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
236 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
237 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
238 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
239 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
240 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
241 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
242 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
243 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
245 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
246 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
247 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
249 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
250 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
251 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
252 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
253 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
254 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
255 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
256 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
257 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
259 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
260 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
261 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
262 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
263 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
264 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
265 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
266 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
267 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
270 #define CONFIG_PCI_INDIRECT_BRIDGE
272 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
273 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
274 #endif /* CONFIG_PCI */
279 #ifdef CONFIG_TSEC_ENET
281 #define CONFIG_GMII /* MII PHY management */
286 #define CONFIG_HAS_ETH0
287 #define CONFIG_TSEC1_NAME "TSEC0"
288 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
289 #define TSEC1_PHY_ADDR 2
290 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
291 #define TSEC1_PHYIDX 0
295 #define CONFIG_HAS_ETH1
296 #define CONFIG_TSEC2_NAME "TSEC1"
297 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
298 #define TSEC2_PHY_ADDR 0x1c
299 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
300 #define TSEC2_PHYIDX 0
303 /* Options are: TSEC[0-1] */
304 #define CONFIG_ETHPRIME "TSEC0"
311 #define CONFIG_SYS_SATA_MAX_DEVICE 2
313 #define CONFIG_SYS_SATA1_OFFSET 0x18000
314 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
315 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
317 #define CONFIG_SYS_SATA2_OFFSET 0x19000
318 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
319 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
321 #ifdef CONFIG_FSL_SATA
328 #ifndef CONFIG_SYS_RAMBOOT
329 #define CONFIG_ENV_ADDR \
330 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
331 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
332 #define CONFIG_ENV_SIZE 0x4000
334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
335 #define CONFIG_ENV_SIZE 0x2000
338 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
339 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
344 #define CONFIG_BOOTP_BOOTFILESIZE
347 * Command line configuration.
350 #undef CONFIG_WATCHDOG /* watchdog disabled */
353 #define CONFIG_FSL_ESDHC_PIN_MUX
354 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
358 * Miscellaneous configurable options
360 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
363 * For booting Linux, the board info and command line data
364 * have to be in the first 256 MB of memory, since this is
365 * the maximum mapped by the Linux kernel during initialization.
367 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
368 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
370 #if defined(CONFIG_CMD_KGDB)
371 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
375 * Environment Configuration
377 #define CONFIG_ENV_OVERWRITE
379 #define CONFIG_HAS_FSL_DR_USB
380 #define CONFIG_USB_EHCI_FSL
381 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
383 #define CONFIG_NETDEV "eth1"
385 #define CONFIG_HOSTNAME "mpc837x_rdb"
386 #define CONFIG_ROOTPATH "/nfsroot"
387 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
388 #define CONFIG_BOOTFILE "uImage"
389 /* U-Boot image on TFTP server */
390 #define CONFIG_UBOOTPATH "u-boot.bin"
391 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
393 /* default location for tftp and bootm */
394 #define CONFIG_LOADADDR 800000
396 #define CONFIG_EXTRA_ENV_SETTINGS \
397 "netdev=" CONFIG_NETDEV "\0" \
398 "uboot=" CONFIG_UBOOTPATH "\0" \
399 "tftpflash=tftp $loadaddr $uboot;" \
400 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
402 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
404 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
406 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
408 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
411 "fdtfile=" CONFIG_FDTFILE "\0" \
412 "ramdiskaddr=1000000\0" \
413 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
415 "setbootargs=setenv bootargs " \
416 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
417 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
418 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
420 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
422 #define CONFIG_NFSBOOTCOMMAND \
423 "setenv rootdev /dev/nfs;" \
426 "tftp $loadaddr $bootfile;" \
427 "tftp $fdtaddr $fdtfile;" \
428 "bootm $loadaddr - $fdtaddr"
430 #define CONFIG_RAMBOOTCOMMAND \
431 "setenv rootdev /dev/ram;" \
433 "tftp $ramdiskaddr $ramdiskfile;" \
434 "tftp $loadaddr $bootfile;" \
435 "tftp $fdtaddr $fdtfile;" \
436 "bootm $loadaddr $ramdiskaddr $fdtaddr"
438 #endif /* __CONFIG_H */