1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
11 #include <linux/stringify.h>
14 * High Level Configuration Options
16 #define CONFIG_E300 1 /* E300 family */
18 #define CONFIG_HWCONFIG
23 #define CONFIG_VSC7385_ENET
25 /* System performance - define the value i.e. CONFIG_SYS_XXX
28 /* System Clock Configuration Register */
29 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
30 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
31 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
36 #define CONFIG_SYS_SICRH 0x08200000
37 #define CONFIG_SYS_SICRL 0x00000000
40 * Output Buffer Impedance
42 #define CONFIG_SYS_OBIR 0x30100000
45 * Device configurations
50 #ifdef CONFIG_VSC7385_ENET
54 /* The flash address and size of the VSC7385 firmware image */
55 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
56 #define CONFIG_VSC7385_IMAGE_SIZE 8192
63 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
65 #define CONFIG_SYS_83XX_DDR_USES_CS0
67 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
69 #undef CONFIG_DDR_ECC /* support DDR ECC function */
70 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
72 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
75 * Manually set up DDR parameters
77 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
78 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
79 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
80 | CSCONFIG_ODT_WR_ONLY_CURRENT \
81 | CSCONFIG_ROW_BIT_13 \
82 | CSCONFIG_COL_BIT_10)
84 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
85 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
86 | (0 << TIMING_CFG0_WRT_SHIFT) \
87 | (0 << TIMING_CFG0_RRT_SHIFT) \
88 | (0 << TIMING_CFG0_WWT_SHIFT) \
89 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
90 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
91 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
92 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
93 /* 0x00260802 */ /* DDR400 */
94 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
95 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
96 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
97 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
98 | (13 << TIMING_CFG1_REFREC_SHIFT) \
99 | (3 << TIMING_CFG1_WRREC_SHIFT) \
100 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
101 | (2 << TIMING_CFG1_WRTORD_SHIFT))
103 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
104 | (5 << TIMING_CFG2_CPO_SHIFT) \
105 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
106 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
107 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
108 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
109 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
112 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
113 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
116 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
117 | SDRAM_CFG_SDRAM_TYPE_DDR2)
119 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
120 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
121 | (0x0442 << SDRAM_MODE_SD_SHIFT))
122 /* 0x04400442 */ /* DDR400 */
123 #define CONFIG_SYS_DDR_MODE2 0x00000000
128 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
131 * The reserved memory
133 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
135 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
136 #define CONFIG_SYS_RAMBOOT
138 #undef CONFIG_SYS_RAMBOOT
141 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
142 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
145 * Initial RAM Base Address Setup
147 #define CONFIG_SYS_INIT_RAM_LOCK 1
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
150 #define CONFIG_SYS_GBL_DATA_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 * FLASH on the Local Bus
156 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
157 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
159 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
163 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
165 #undef CONFIG_SYS_FLASH_CHECKSUM
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
170 * NAND Flash on the Local Bus
172 #define CONFIG_SYS_NAND_BASE 0xE0600000
177 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
182 #define CONFIG_SYS_NS16550_SERIAL
183 #define CONFIG_SYS_NS16550_REG_SIZE 1
184 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
186 #define CONFIG_SYS_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
193 #define CONFIG_FSL_SERDES
194 #define CONFIG_FSL_SERDES1 0xe3000
195 #define CONFIG_FSL_SERDES2 0xe3100
198 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
201 * Config on-board RTC
203 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
204 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
208 * Addresses are mapped 1-1.
210 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
211 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
212 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
213 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
214 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
215 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
216 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
217 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
218 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
220 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
221 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
222 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
224 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
225 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
226 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
227 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
228 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
229 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
230 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
231 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
232 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
234 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
235 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
236 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
237 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
238 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
239 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
240 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
241 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
242 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
245 #define CONFIG_PCI_INDIRECT_BRIDGE
247 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
248 #endif /* CONFIG_PCI */
253 #ifdef CONFIG_TSEC_ENET
255 #define CONFIG_GMII /* MII PHY management */
260 #define CONFIG_HAS_ETH0
261 #define CONFIG_TSEC1_NAME "TSEC0"
262 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
263 #define TSEC1_PHY_ADDR 2
264 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
265 #define TSEC1_PHYIDX 0
269 #define CONFIG_HAS_ETH1
270 #define CONFIG_TSEC2_NAME "TSEC1"
271 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
272 #define TSEC2_PHY_ADDR 0x1c
273 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
274 #define TSEC2_PHYIDX 0
277 /* Options are: TSEC[0-1] */
278 #define CONFIG_ETHPRIME "TSEC0"
285 #define CONFIG_SYS_SATA_MAX_DEVICE 2
287 #define CONFIG_SYS_SATA1_OFFSET 0x18000
288 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
289 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
291 #define CONFIG_SYS_SATA2_OFFSET 0x19000
292 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
293 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
295 #ifdef CONFIG_FSL_SATA
303 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
304 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
309 #define CONFIG_BOOTP_BOOTFILESIZE
311 #undef CONFIG_WATCHDOG /* watchdog disabled */
314 #define CONFIG_FSL_ESDHC_PIN_MUX
315 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
319 * Miscellaneous configurable options
321 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
324 * For booting Linux, the board info and command line data
325 * have to be in the first 256 MB of memory, since this is
326 * the maximum mapped by the Linux kernel during initialization.
328 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
329 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
331 #if defined(CONFIG_CMD_KGDB)
332 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
336 * Environment Configuration
339 #define CONFIG_HAS_FSL_DR_USB
340 #define CONFIG_USB_EHCI_FSL
341 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
343 #define CONFIG_NETDEV "eth1"
345 #define CONFIG_HOSTNAME "mpc837x_rdb"
346 #define CONFIG_ROOTPATH "/nfsroot"
347 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
348 #define CONFIG_BOOTFILE "uImage"
349 /* U-Boot image on TFTP server */
350 #define CONFIG_UBOOTPATH "u-boot.bin"
351 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
353 /* default location for tftp and bootm */
354 #define CONFIG_LOADADDR 800000
356 #define CONFIG_EXTRA_ENV_SETTINGS \
357 "netdev=" CONFIG_NETDEV "\0" \
358 "uboot=" CONFIG_UBOOTPATH "\0" \
359 "tftpflash=tftp $loadaddr $uboot;" \
360 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
362 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
364 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
366 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
368 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
371 "fdtfile=" CONFIG_FDTFILE "\0" \
372 "ramdiskaddr=1000000\0" \
373 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
375 "setbootargs=setenv bootargs " \
376 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
377 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
378 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
380 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
382 #define NFSBOOTCOMMAND \
383 "setenv rootdev /dev/nfs;" \
386 "tftp $loadaddr $bootfile;" \
387 "tftp $fdtaddr $fdtfile;" \
388 "bootm $loadaddr - $fdtaddr"
390 #define RAMBOOTCOMMAND \
391 "setenv rootdev /dev/ram;" \
393 "tftp $ramdiskaddr $ramdiskfile;" \
394 "tftp $loadaddr $bootfile;" \
395 "tftp $fdtaddr $fdtfile;" \
396 "bootm $loadaddr $ramdiskaddr $fdtaddr"
398 #endif /* __CONFIG_H */