include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_HWCONFIG
  17
  18 /*
  19  * On-board devices
  20  */
  21 #define CONFIG_VSC7385_ENET
  22
  23 /* System performance - define the value i.e. CONFIG_SYS_XXX
  24 */
  25
  26 /* Arbiter Configuration Register */
  27 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  28 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  29
  30 /* System Priority Control Regsiter */
  31 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  32
  33 /* System Clock Configuration Register */
  34 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  35 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  36 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  37
  38 /*
  39  * System IO Config
  40  */
  41 #define CONFIG_SYS_SICRH                0x08200000
  42 #define CONFIG_SYS_SICRL                0x00000000
  43
  44 /*
  45  * Output Buffer Impedance
  46  */
  47 #define CONFIG_SYS_OBIR         0x30100000
  48
  49 /*
  50  * Device configurations
  51  */
  52
  53 /* Vitesse 7385 */
  54
  55 #ifdef CONFIG_VSC7385_ENET
  56
  57 #define CONFIG_TSEC2
  58
  59 /* The flash address and size of the VSC7385 firmware image */
  60 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  61 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  62
  63 #endif
  64
  65 /*
  66  * DDR Setup
  67  */
  68 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  69 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  70 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  71 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
  72 #define CONFIG_SYS_83XX_DDR_USES_CS0
  73
  74 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  75
  76 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
  77 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
  78
  79 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
  80
  81 /*
  82  * Manually set up DDR parameters
  83  */
  84 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  85 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  86 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  87                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  88                                         | CSCONFIG_ROW_BIT_13 \
  89                                         | CSCONFIG_COL_BIT_10)
  90
  91 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  92 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  93                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  94                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  95                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  96                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  97                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  98                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  99                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 100                                 /* 0x00260802 */ /* DDR400 */
 101 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 102                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 103                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 104                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 105                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 106                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 107                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 108                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 109                                 /* 0x3937d322 */
 110 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 111                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 112                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 113                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 114                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 115                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 116                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 117                                 /* 0x02984cc8 */
 118
 119 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 120                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 121                                 /* 0x06090100 */
 122
 123 #if defined(CONFIG_DDR_2T_TIMING)
 124 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 125                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 126                                         | SDRAM_CFG_32_BE \
 127                                         | SDRAM_CFG_2T_EN)
 128                                         /* 0x43088000 */
 129 #else
 130 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 131                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 132                                         /* 0x43000000 */
 133 #endif
 134 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 135 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 136                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 137                                         /* 0x04400442 */ /* DDR400 */
 138 #define CONFIG_SYS_DDR_MODE2            0x00000000
 139
 140 /*
 141  * Memory test
 142  */
 143 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 144 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 145 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 146
 147 /*
 148  * The reserved memory
 149  */
 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 151
 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 153 #define CONFIG_SYS_RAMBOOT
 154 #else
 155 #undef  CONFIG_SYS_RAMBOOT
 156 #endif
 157
 158 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 159 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 160
 161 /*
 162  * Initial RAM Base Address Setup
 163  */
 164 #define CONFIG_SYS_INIT_RAM_LOCK        1
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 166 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 167 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 168                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 169
 170 /*
 171  * Local Bus Configuration & Clock Setup
 172  */
 173 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 174 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 175 #define CONFIG_SYS_LBC_LBCR             0x00000000
 176 #define CONFIG_FSL_ELBC         1
 177
 178 /*
 179  * FLASH on the Local Bus
 180  */
 181 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 182 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 183
 184 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 185
 186
 187 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 188 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 189
 190 #undef  CONFIG_SYS_FLASH_CHECKSUM
 191 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 192 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 193
 194 /*
 195  * NAND Flash on the Local Bus
 196  */
 197 #define CONFIG_SYS_NAND_BASE    0xE0600000
 198
 199
 200 /* Vitesse 7385 */
 201
 202 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 203
 204 #ifdef CONFIG_VSC7385_ENET
 205
 206
 207 #endif
 208
 209 /*
 210  * Serial Port
 211  */
 212 #define CONFIG_SYS_NS16550_SERIAL
 213 #define CONFIG_SYS_NS16550_REG_SIZE     1
 214 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 215
 216 #define CONFIG_SYS_BAUDRATE_TABLE \
 217                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 218
 219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 221
 222 /* SERDES */
 223 #define CONFIG_FSL_SERDES
 224 #define CONFIG_FSL_SERDES1      0xe3000
 225 #define CONFIG_FSL_SERDES2      0xe3100
 226
 227 /* I2C */
 228 #define CONFIG_SYS_I2C
 229 #define CONFIG_SYS_I2C_FSL
 230 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 231 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 232 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 233 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 234
 235 /*
 236  * Config on-board RTC
 237  */
 238 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 239 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 240
 241 /*
 242  * General PCI
 243  * Addresses are mapped 1-1.
 244  */
 245 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 246 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 247 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 248 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 249 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 250 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 251 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 252 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 253 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 254
 255 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 256 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 257 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 258
 259 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 260 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 261 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 262 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 263 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 264 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 265 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 266 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 267 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 268
 269 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 270 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 271 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 272 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 273 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 274 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 275 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 276 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 277 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 278
 279 #ifdef CONFIG_PCI
 280 #define CONFIG_PCI_INDIRECT_BRIDGE
 281
 282 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 283 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 284 #endif  /* CONFIG_PCI */
 285
 286 /*
 287  * TSEC
 288  */
 289 #ifdef CONFIG_TSEC_ENET
 290
 291 #define CONFIG_GMII                     /* MII PHY management */
 292
 293 #define CONFIG_TSEC1
 294
 295 #ifdef CONFIG_TSEC1
 296 #define CONFIG_HAS_ETH0
 297 #define CONFIG_TSEC1_NAME               "TSEC0"
 298 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 299 #define TSEC1_PHY_ADDR                  2
 300 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 301 #define TSEC1_PHYIDX                    0
 302 #endif
 303
 304 #ifdef CONFIG_TSEC2
 305 #define CONFIG_HAS_ETH1
 306 #define CONFIG_TSEC2_NAME               "TSEC1"
 307 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 308 #define TSEC2_PHY_ADDR                  0x1c
 309 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 310 #define TSEC2_PHYIDX                    0
 311 #endif
 312
 313 /* Options are: TSEC[0-1] */
 314 #define CONFIG_ETHPRIME                 "TSEC0"
 315
 316 #endif
 317
 318 /*
 319  * SATA
 320  */
 321 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 322 #define CONFIG_SATA1
 323 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 324 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 325 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 326 #define CONFIG_SATA2
 327 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 328 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 329 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 330
 331 #ifdef CONFIG_FSL_SATA
 332 #define CONFIG_LBA48
 333 #endif
 334
 335 /*
 336  * Environment
 337  */
 338 #ifndef CONFIG_SYS_RAMBOOT
 339         #define CONFIG_ENV_ADDR         \
 340                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 341         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 342         #define CONFIG_ENV_SIZE         0x4000
 343 #else
 344         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 345         #define CONFIG_ENV_SIZE         0x2000
 346 #endif
 347
 348 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 349 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 350
 351 /*
 352  * BOOTP options
 353  */
 354 #define CONFIG_BOOTP_BOOTFILESIZE
 355
 356 /*
 357  * Command line configuration.
 358  */
 359
 360 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 361
 362 #ifdef CONFIG_MMC
 363 #define CONFIG_FSL_ESDHC_PIN_MUX
 364 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 365 #endif
 366
 367 /*
 368  * Miscellaneous configurable options
 369  */
 370 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 371
 372 /*
 373  * For booting Linux, the board info and command line data
 374  * have to be in the first 256 MB of memory, since this is
 375  * the maximum mapped by the Linux kernel during initialization.
 376  */
 377 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 378 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 379
 380 #if defined(CONFIG_CMD_KGDB)
 381 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 382 #endif
 383
 384 /*
 385  * Environment Configuration
 386  */
 387 #define CONFIG_ENV_OVERWRITE
 388
 389 #define CONFIG_HAS_FSL_DR_USB
 390 #define CONFIG_USB_EHCI_FSL
 391 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 392
 393 #define CONFIG_NETDEV           "eth1"
 394
 395 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 396 #define CONFIG_ROOTPATH         "/nfsroot"
 397 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 398 #define CONFIG_BOOTFILE         "uImage"
 399                                 /* U-Boot image on TFTP server */
 400 #define CONFIG_UBOOTPATH        "u-boot.bin"
 401 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 402
 403                                 /* default location for tftp and bootm */
 404 #define CONFIG_LOADADDR         800000
 405
 406 #define CONFIG_EXTRA_ENV_SETTINGS \
 407         "netdev=" CONFIG_NETDEV "\0"                            \
 408         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 409         "tftpflash=tftp $loadaddr $uboot;"                              \
 410                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 411                         " +$filesize; " \
 412                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 413                         " +$filesize; " \
 414                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 415                         " $filesize; "  \
 416                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 417                         " +$filesize; " \
 418                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 419                         " $filesize\0"  \
 420         "fdtaddr=780000\0"                                              \
 421         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 422         "ramdiskaddr=1000000\0"                                         \
 423         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 424         "console=ttyS0\0"                                               \
 425         "setbootargs=setenv bootargs "                                  \
 426                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 427         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 428                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 429                                                         "$netdev:off "  \
 430                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 431
 432 #define CONFIG_NFSBOOTCOMMAND                                           \
 433         "setenv rootdev /dev/nfs;"                                      \
 434         "run setbootargs;"                                              \
 435         "run setipargs;"                                                \
 436         "tftp $loadaddr $bootfile;"                                     \
 437         "tftp $fdtaddr $fdtfile;"                                       \
 438         "bootm $loadaddr - $fdtaddr"
 439
 440 #define CONFIG_RAMBOOTCOMMAND                                           \
 441         "setenv rootdev /dev/ram;"                                      \
 442         "run setbootargs;"                                              \
 443         "tftp $ramdiskaddr $ramdiskfile;"                               \
 444         "tftp $loadaddr $bootfile;"                                     \
 445         "tftp $fdtaddr $fdtfile;"                                       \
 446         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 447
 448 #endif  /* __CONFIG_H */