Merge branch 'master' of git://git.denx.de/u-boot-usb
[platform/kernel/u-boot.git] / include / configs / MPC837XERDB.h
1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  * Kevin Lam <kevin.lam@freescale.com>
4  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5  *
6  * SPDX-License-Identifier:     GPL-2.0+
7  */
8
9 #ifndef __CONFIG_H
10 #define __CONFIG_H
11
12 /*
13  * High Level Configuration Options
14  */
15 #define CONFIG_E300             1 /* E300 family */
16 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
17 #define CONFIG_MPC837XERDB      1
18
19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
20
21 #define CONFIG_MISC_INIT_R
22 #define CONFIG_HWCONFIG
23
24 /*
25  * On-board devices
26  */
27 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
28 #define CONFIG_VSC7385_ENET
29
30 /*
31  * System Clock Setup
32  */
33 #ifdef CONFIG_PCISLAVE
34 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
35 #else
36 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
37 #define CONFIG_PCIE
38 #endif
39
40 #ifndef CONFIG_SYS_CLK_FREQ
41 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
42 #endif
43
44 /*
45  * Hardware Reset Configuration Word
46  */
47 #define CONFIG_SYS_HRCW_LOW (\
48         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
49         HRCWL_DDR_TO_SCB_CLK_1X1 |\
50         HRCWL_SVCOD_DIV_2 |\
51         HRCWL_CSB_TO_CLKIN_5X1 |\
52         HRCWL_CORE_TO_CSB_2X1)
53
54 #ifdef CONFIG_PCISLAVE
55 #define CONFIG_SYS_HRCW_HIGH (\
56         HRCWH_PCI_AGENT |\
57         HRCWH_PCI1_ARBITER_DISABLE |\
58         HRCWH_CORE_ENABLE |\
59         HRCWH_FROM_0XFFF00100 |\
60         HRCWH_BOOTSEQ_DISABLE |\
61         HRCWH_SW_WATCHDOG_DISABLE |\
62         HRCWH_ROM_LOC_LOCAL_16BIT |\
63         HRCWH_RL_EXT_LEGACY |\
64         HRCWH_TSEC1M_IN_RGMII |\
65         HRCWH_TSEC2M_IN_RGMII |\
66         HRCWH_BIG_ENDIAN |\
67         HRCWH_LDP_CLEAR)
68 #else
69 #define CONFIG_SYS_HRCW_HIGH (\
70         HRCWH_PCI_HOST |\
71         HRCWH_PCI1_ARBITER_ENABLE |\
72         HRCWH_CORE_ENABLE |\
73         HRCWH_FROM_0X00000100 |\
74         HRCWH_BOOTSEQ_DISABLE |\
75         HRCWH_SW_WATCHDOG_DISABLE |\
76         HRCWH_ROM_LOC_LOCAL_16BIT |\
77         HRCWH_RL_EXT_LEGACY |\
78         HRCWH_TSEC1M_IN_RGMII |\
79         HRCWH_TSEC2M_IN_RGMII |\
80         HRCWH_BIG_ENDIAN |\
81         HRCWH_LDP_CLEAR)
82 #endif
83
84 /* System performance - define the value i.e. CONFIG_SYS_XXX
85 */
86
87 /* Arbiter Configuration Register */
88 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
89 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
90
91 /* System Priority Control Regsiter */
92 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
93
94 /* System Clock Configuration Register */
95 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
96 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
97 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
98
99 /*
100  * System IO Config
101  */
102 #define CONFIG_SYS_SICRH                0x08200000
103 #define CONFIG_SYS_SICRL                0x00000000
104
105 /*
106  * Output Buffer Impedance
107  */
108 #define CONFIG_SYS_OBIR         0x30100000
109
110 /*
111  * IMMR new address
112  */
113 #define CONFIG_SYS_IMMR         0xE0000000
114
115 /*
116  * Device configurations
117  */
118
119 /* Vitesse 7385 */
120
121 #ifdef CONFIG_VSC7385_ENET
122
123 #define CONFIG_TSEC2
124
125 /* The flash address and size of the VSC7385 firmware image */
126 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
127 #define CONFIG_VSC7385_IMAGE_SIZE       8192
128
129 #endif
130
131 /*
132  * DDR Setup
133  */
134 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
135 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
136 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
137 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
138 #define CONFIG_SYS_83XX_DDR_USES_CS0
139
140 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
141
142 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
143 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
144
145 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
146
147 /*
148  * Manually set up DDR parameters
149  */
150 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
151 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
152 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
153                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
154                                         | CSCONFIG_ROW_BIT_13 \
155                                         | CSCONFIG_COL_BIT_10)
156
157 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
158 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
159                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
160                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
161                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
162                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
163                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
164                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
165                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
166                                 /* 0x00260802 */ /* DDR400 */
167 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
168                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
169                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
170                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
171                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
172                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
173                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
174                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
175                                 /* 0x3937d322 */
176 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
177                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
178                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
179                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
180                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
181                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
182                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
183                                 /* 0x02984cc8 */
184
185 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
186                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
187                                 /* 0x06090100 */
188
189 #if defined(CONFIG_DDR_2T_TIMING)
190 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
191                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
192                                         | SDRAM_CFG_32_BE \
193                                         | SDRAM_CFG_2T_EN)
194                                         /* 0x43088000 */
195 #else
196 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
197                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
198                                         /* 0x43000000 */
199 #endif
200 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
201 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
202                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
203                                         /* 0x04400442 */ /* DDR400 */
204 #define CONFIG_SYS_DDR_MODE2            0x00000000
205
206 /*
207  * Memory test
208  */
209 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
210 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
211 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
212
213 /*
214  * The reserved memory
215  */
216 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
217
218 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
219 #define CONFIG_SYS_RAMBOOT
220 #else
221 #undef  CONFIG_SYS_RAMBOOT
222 #endif
223
224 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
225 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
226
227 /*
228  * Initial RAM Base Address Setup
229  */
230 #define CONFIG_SYS_INIT_RAM_LOCK        1
231 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
233 #define CONFIG_SYS_GBL_DATA_OFFSET      \
234                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
235
236 /*
237  * Local Bus Configuration & Clock Setup
238  */
239 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
240 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
241 #define CONFIG_SYS_LBC_LBCR             0x00000000
242 #define CONFIG_FSL_ELBC         1
243
244 /*
245  * FLASH on the Local Bus
246  */
247 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
248 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
249 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
250 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
251
252 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
253 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
254 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       /* buffer up multiple bytes */
255
256                                         /* Window base at flash base */
257 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
258 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
259
260 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
261                                 | BR_PS_16      /* 16 bit port */ \
262                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
263                                 | BR_V)         /* valid */
264 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
265                                 | OR_GPCM_XACS \
266                                 | OR_GPCM_SCY_9 \
267                                 | OR_GPCM_EHTR_SET \
268                                 | OR_GPCM_EAD)
269                                 /* 0xFF800191 */
270
271 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
272 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
273
274 #undef  CONFIG_SYS_FLASH_CHECKSUM
275 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
276 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
277
278 /*
279  * NAND Flash on the Local Bus
280  */
281 #define CONFIG_SYS_NAND_BASE    0xE0600000
282 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
283                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
284                                 | BR_PS_8               /* 8 bit port */ \
285                                 | BR_MS_FCM             /* MSEL = FCM */ \
286                                 | BR_V)                 /* valid */
287 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
288                                 | OR_FCM_CSCT \
289                                 | OR_FCM_CST \
290                                 | OR_FCM_CHT \
291                                 | OR_FCM_SCY_1 \
292                                 | OR_FCM_TRLX \
293                                 | OR_FCM_EHTR)
294 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
295 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
296
297 /* Vitesse 7385 */
298
299 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
300
301 #ifdef CONFIG_VSC7385_ENET
302
303 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
304                                         | BR_PS_8 \
305                                         | BR_MS_GPCM \
306                                         | BR_V)
307                                         /* 0xF0000801 */
308 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
309                                         | OR_GPCM_CSNT \
310                                         | OR_GPCM_XACS \
311                                         | OR_GPCM_SCY_15 \
312                                         | OR_GPCM_SETA \
313                                         | OR_GPCM_TRLX_SET \
314                                         | OR_GPCM_EHTR_SET \
315                                         | OR_GPCM_EAD)
316                                         /* 0xfffe09ff */
317
318                                         /* Access Base */
319 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
320 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
321
322 #endif
323
324 /*
325  * Serial Port
326  */
327 #define CONFIG_CONS_INDEX       1
328 #define CONFIG_SYS_NS16550_SERIAL
329 #define CONFIG_SYS_NS16550_REG_SIZE     1
330 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
331
332 #define CONFIG_SYS_BAUDRATE_TABLE \
333                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
334
335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
337
338 /* SERDES */
339 #define CONFIG_FSL_SERDES
340 #define CONFIG_FSL_SERDES1      0xe3000
341 #define CONFIG_FSL_SERDES2      0xe3100
342
343 /* I2C */
344 #define CONFIG_SYS_I2C
345 #define CONFIG_SYS_I2C_FSL
346 #define CONFIG_SYS_FSL_I2C_SPEED        400000
347 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
348 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
349 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
350
351 /*
352  * Config on-board RTC
353  */
354 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
355 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
356
357 /*
358  * General PCI
359  * Addresses are mapped 1-1.
360  */
361 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
362 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
363 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
364 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
365 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
366 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
367 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
368 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
369 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
370
371 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
372 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
373 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
374
375 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
376 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
377 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
378 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
379 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
380 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
381 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
382 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
383 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
384
385 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
386 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
387 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
388 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
389 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
390 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
391 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
392 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
393 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
394
395 #ifdef CONFIG_PCI
396 #define CONFIG_PCI_INDIRECT_BRIDGE
397
398 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
399 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
400 #endif  /* CONFIG_PCI */
401
402 /*
403  * TSEC
404  */
405 #ifdef CONFIG_TSEC_ENET
406
407 #define CONFIG_GMII                     /* MII PHY management */
408
409 #define CONFIG_TSEC1
410
411 #ifdef CONFIG_TSEC1
412 #define CONFIG_HAS_ETH0
413 #define CONFIG_TSEC1_NAME               "TSEC0"
414 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
415 #define TSEC1_PHY_ADDR                  2
416 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
417 #define TSEC1_PHYIDX                    0
418 #endif
419
420 #ifdef CONFIG_TSEC2
421 #define CONFIG_HAS_ETH1
422 #define CONFIG_TSEC2_NAME               "TSEC1"
423 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
424 #define TSEC2_PHY_ADDR                  0x1c
425 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
426 #define TSEC2_PHYIDX                    0
427 #endif
428
429 /* Options are: TSEC[0-1] */
430 #define CONFIG_ETHPRIME                 "TSEC0"
431
432 #endif
433
434 /*
435  * SATA
436  */
437 #define CONFIG_SYS_SATA_MAX_DEVICE      2
438 #define CONFIG_SATA1
439 #define CONFIG_SYS_SATA1_OFFSET 0x18000
440 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
441 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
442 #define CONFIG_SATA2
443 #define CONFIG_SYS_SATA2_OFFSET 0x19000
444 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
445 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
446
447 #ifdef CONFIG_FSL_SATA
448 #define CONFIG_LBA48
449 #endif
450
451 /*
452  * Environment
453  */
454 #ifndef CONFIG_SYS_RAMBOOT
455         #define CONFIG_ENV_ADDR         \
456                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
457         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
458         #define CONFIG_ENV_SIZE         0x4000
459 #else
460         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
461         #define CONFIG_ENV_SIZE         0x2000
462 #endif
463
464 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
465 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
466
467 /*
468  * BOOTP options
469  */
470 #define CONFIG_BOOTP_BOOTFILESIZE
471 #define CONFIG_BOOTP_BOOTPATH
472 #define CONFIG_BOOTP_GATEWAY
473 #define CONFIG_BOOTP_HOSTNAME
474
475 /*
476  * Command line configuration.
477  */
478
479 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
480 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
481
482 #undef CONFIG_WATCHDOG          /* watchdog disabled */
483
484 #ifdef CONFIG_MMC
485 #define CONFIG_FSL_ESDHC
486 #define CONFIG_FSL_ESDHC_PIN_MUX
487 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
488 #endif
489
490 /*
491  * Miscellaneous configurable options
492  */
493 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
494 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
495
496 /*
497  * For booting Linux, the board info and command line data
498  * have to be in the first 256 MB of memory, since this is
499  * the maximum mapped by the Linux kernel during initialization.
500  */
501 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
502 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
503
504 /*
505  * Core HID Setup
506  */
507 #define CONFIG_SYS_HID0_INIT    0x000000000
508 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
509                                 | HID0_ENABLE_INSTRUCTION_CACHE)
510 #define CONFIG_SYS_HID2         HID2_HBE
511
512 /*
513  * MMU Setup
514  */
515
516 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
517
518 /* DDR: cache cacheable */
519 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
520 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
521
522 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
523                                 | BATL_PP_RW \
524                                 | BATL_MEMCOHERENCE)
525 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
526                                 | BATU_BL_256M \
527                                 | BATU_VS \
528                                 | BATU_VP)
529 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
530 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
531
532 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
533                                 | BATL_PP_RW \
534                                 | BATL_MEMCOHERENCE)
535 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
536                                 | BATU_BL_256M \
537                                 | BATU_VS \
538                                 | BATU_VP)
539 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
540 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
541
542 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
543 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
544                                 | BATL_PP_RW \
545                                 | BATL_CACHEINHIBIT \
546                                 | BATL_GUARDEDSTORAGE)
547 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
548                                 | BATU_BL_8M \
549                                 | BATU_VS \
550                                 | BATU_VP)
551 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
552 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
553
554 /* L2 Switch: cache-inhibit and guarded */
555 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
556                                 | BATL_PP_RW \
557                                 | BATL_CACHEINHIBIT \
558                                 | BATL_GUARDEDSTORAGE)
559 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
560                                 | BATU_BL_128K \
561                                 | BATU_VS \
562                                 | BATU_VP)
563 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
564 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
565
566 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
567 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
568                                 | BATL_PP_RW \
569                                 | BATL_MEMCOHERENCE)
570 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
571                                 | BATU_BL_32M \
572                                 | BATU_VS \
573                                 | BATU_VP)
574 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
575                                 | BATL_PP_RW \
576                                 | BATL_CACHEINHIBIT \
577                                 | BATL_GUARDEDSTORAGE)
578 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
579
580 /* Stack in dcache: cacheable, no memory coherence */
581 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
582 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
583                                 | BATU_BL_128K \
584                                 | BATU_VS \
585                                 | BATU_VP)
586 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
587 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
588
589 #ifdef CONFIG_PCI
590 /* PCI MEM space: cacheable */
591 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
592                                 | BATL_PP_RW \
593                                 | BATL_MEMCOHERENCE)
594 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
595                                 | BATU_BL_256M \
596                                 | BATU_VS \
597                                 | BATU_VP)
598 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
599 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
600 /* PCI MMIO space: cache-inhibit and guarded */
601 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
602                                 | BATL_PP_RW \
603                                 | BATL_CACHEINHIBIT \
604                                 | BATL_GUARDEDSTORAGE)
605 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
606                                 | BATU_BL_256M \
607                                 | BATU_VS \
608                                 | BATU_VP)
609 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
610 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
611 #else
612 #define CONFIG_SYS_IBAT6L       (0)
613 #define CONFIG_SYS_IBAT6U       (0)
614 #define CONFIG_SYS_IBAT7L       (0)
615 #define CONFIG_SYS_IBAT7U       (0)
616 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
617 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
618 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
619 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
620 #endif
621
622 #if defined(CONFIG_CMD_KGDB)
623 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
624 #endif
625
626 /*
627  * Environment Configuration
628  */
629 #define CONFIG_ENV_OVERWRITE
630
631 #define CONFIG_HAS_FSL_DR_USB
632 #define CONFIG_USB_EHCI_FSL
633 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
634
635 #define CONFIG_NETDEV           "eth1"
636
637 #define CONFIG_HOSTNAME         mpc837x_rdb
638 #define CONFIG_ROOTPATH         "/nfsroot"
639 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
640 #define CONFIG_BOOTFILE         "uImage"
641                                 /* U-Boot image on TFTP server */
642 #define CONFIG_UBOOTPATH        "u-boot.bin"
643 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
644
645                                 /* default location for tftp and bootm */
646 #define CONFIG_LOADADDR         800000
647
648 #define CONFIG_EXTRA_ENV_SETTINGS \
649         "netdev=" CONFIG_NETDEV "\0"                            \
650         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
651         "tftpflash=tftp $loadaddr $uboot;"                              \
652                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
653                         " +$filesize; " \
654                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
655                         " +$filesize; " \
656                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
657                         " $filesize; "  \
658                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
659                         " +$filesize; " \
660                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
661                         " $filesize\0"  \
662         "fdtaddr=780000\0"                                              \
663         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
664         "ramdiskaddr=1000000\0"                                         \
665         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
666         "console=ttyS0\0"                                               \
667         "setbootargs=setenv bootargs "                                  \
668                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
669         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
670                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
671                                                         "$netdev:off "  \
672                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
673
674 #define CONFIG_NFSBOOTCOMMAND                                           \
675         "setenv rootdev /dev/nfs;"                                      \
676         "run setbootargs;"                                              \
677         "run setipargs;"                                                \
678         "tftp $loadaddr $bootfile;"                                     \
679         "tftp $fdtaddr $fdtfile;"                                       \
680         "bootm $loadaddr - $fdtaddr"
681
682 #define CONFIG_RAMBOOTCOMMAND                                           \
683         "setenv rootdev /dev/ram;"                                      \
684         "run setbootargs;"                                              \
685         "tftp $ramdiskaddr $ramdiskfile;"                               \
686         "tftp $loadaddr $bootfile;"                                     \
687         "tftp $fdtaddr $fdtfile;"                                       \
688         "bootm $loadaddr $ramdiskaddr $fdtaddr"
689
690 #endif  /* __CONFIG_H */