Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
[platform/kernel/u-boot.git] / include / configs / MPC837XERDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
4  * Kevin Lam <kevin.lam@freescale.com>
5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6  */
7
8 #ifndef __CONFIG_H
9 #define __CONFIG_H
10
11 #include <linux/stringify.h>
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_E300             1 /* E300 family */
17
18 #define CONFIG_HWCONFIG
19
20 /*
21  * On-board devices
22  */
23 #define CONFIG_VSC7385_ENET
24
25 /* System performance - define the value i.e. CONFIG_SYS_XXX
26 */
27
28 /* System Clock Configuration Register */
29 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
30 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
31 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
32
33 /*
34  * System IO Config
35  */
36 #define CONFIG_SYS_SICRH                0x08200000
37 #define CONFIG_SYS_SICRL                0x00000000
38
39 /*
40  * Output Buffer Impedance
41  */
42 #define CONFIG_SYS_OBIR         0x30100000
43
44 /*
45  * Device configurations
46  */
47
48 /* Vitesse 7385 */
49
50 #ifdef CONFIG_VSC7385_ENET
51
52 #define CONFIG_TSEC2
53
54 /* The flash address and size of the VSC7385 firmware image */
55 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
56 #define CONFIG_VSC7385_IMAGE_SIZE       8192
57
58 #endif
59
60 /*
61  * DDR Setup
62  */
63 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
64 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
65 #define CONFIG_SYS_83XX_DDR_USES_CS0
66
67 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
68
69 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
70 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
71
72 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
73
74 /*
75  * Manually set up DDR parameters
76  */
77 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
78 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
79 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
80                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
81                                         | CSCONFIG_ROW_BIT_13 \
82                                         | CSCONFIG_COL_BIT_10)
83
84 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
85 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
86                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
87                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
88                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
89                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
90                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
91                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
92                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
93                                 /* 0x00260802 */ /* DDR400 */
94 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
95                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
96                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
97                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
98                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
99                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
100                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
101                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
102                                 /* 0x3937d322 */
103 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
104                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
105                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
106                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
107                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
108                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
109                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
110                                 /* 0x02984cc8 */
111
112 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
113                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
114                                 /* 0x06090100 */
115
116 #if defined(CONFIG_DDR_2T_TIMING)
117 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
118                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
119                                         | SDRAM_CFG_32_BE \
120                                         | SDRAM_CFG_2T_EN)
121                                         /* 0x43088000 */
122 #else
123 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
124                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
125                                         /* 0x43000000 */
126 #endif
127 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
128 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
129                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
130                                         /* 0x04400442 */ /* DDR400 */
131 #define CONFIG_SYS_DDR_MODE2            0x00000000
132
133 /*
134  * Memory test
135  */
136 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
137
138 /*
139  * The reserved memory
140  */
141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
142
143 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
144 #define CONFIG_SYS_RAMBOOT
145 #else
146 #undef  CONFIG_SYS_RAMBOOT
147 #endif
148
149 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
150 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
151
152 /*
153  * Initial RAM Base Address Setup
154  */
155 #define CONFIG_SYS_INIT_RAM_LOCK        1
156 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
157 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
158 #define CONFIG_SYS_GBL_DATA_OFFSET      \
159                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
160
161 /*
162  * FLASH on the Local Bus
163  */
164 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
165 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
166
167 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
168
169
170 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
171 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
172
173 #undef  CONFIG_SYS_FLASH_CHECKSUM
174 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
175 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
176
177 /*
178  * NAND Flash on the Local Bus
179  */
180 #define CONFIG_SYS_NAND_BASE    0xE0600000
181
182
183 /* Vitesse 7385 */
184
185 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
186
187 /*
188  * Serial Port
189  */
190 #define CONFIG_SYS_NS16550_SERIAL
191 #define CONFIG_SYS_NS16550_REG_SIZE     1
192 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
193
194 #define CONFIG_SYS_BAUDRATE_TABLE \
195                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
196
197 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
198 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
199
200 /* SERDES */
201 #define CONFIG_FSL_SERDES
202 #define CONFIG_FSL_SERDES1      0xe3000
203 #define CONFIG_FSL_SERDES2      0xe3100
204
205 /* I2C */
206 #define CONFIG_SYS_I2C
207 #define CONFIG_SYS_I2C_FSL
208 #define CONFIG_SYS_FSL_I2C_SPEED        400000
209 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
210 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
211 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
212
213 /*
214  * Config on-board RTC
215  */
216 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
217 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
218
219 /*
220  * General PCI
221  * Addresses are mapped 1-1.
222  */
223 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
224 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
225 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
226 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
227 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
228 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
229 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
230 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
231 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
232
233 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
234 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
235 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
236
237 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
238 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
239 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
240 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
241 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
242 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
243 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
244 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
245 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
246
247 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
248 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
249 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
250 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
251 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
252 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
253 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
254 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
255 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
256
257 #ifdef CONFIG_PCI
258 #define CONFIG_PCI_INDIRECT_BRIDGE
259
260 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
262 #endif  /* CONFIG_PCI */
263
264 /*
265  * TSEC
266  */
267 #ifdef CONFIG_TSEC_ENET
268
269 #define CONFIG_GMII                     /* MII PHY management */
270
271 #define CONFIG_TSEC1
272
273 #ifdef CONFIG_TSEC1
274 #define CONFIG_HAS_ETH0
275 #define CONFIG_TSEC1_NAME               "TSEC0"
276 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
277 #define TSEC1_PHY_ADDR                  2
278 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
279 #define TSEC1_PHYIDX                    0
280 #endif
281
282 #ifdef CONFIG_TSEC2
283 #define CONFIG_HAS_ETH1
284 #define CONFIG_TSEC2_NAME               "TSEC1"
285 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
286 #define TSEC2_PHY_ADDR                  0x1c
287 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
288 #define TSEC2_PHYIDX                    0
289 #endif
290
291 /* Options are: TSEC[0-1] */
292 #define CONFIG_ETHPRIME                 "TSEC0"
293
294 #endif
295
296 /*
297  * SATA
298  */
299 #define CONFIG_SYS_SATA_MAX_DEVICE      2
300 #define CONFIG_SATA1
301 #define CONFIG_SYS_SATA1_OFFSET 0x18000
302 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
303 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
304 #define CONFIG_SATA2
305 #define CONFIG_SYS_SATA2_OFFSET 0x19000
306 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
307 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
308
309 #ifdef CONFIG_FSL_SATA
310 #define CONFIG_LBA48
311 #endif
312
313 /*
314  * Environment
315  */
316
317 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
318 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
319
320 /*
321  * BOOTP options
322  */
323 #define CONFIG_BOOTP_BOOTFILESIZE
324
325 /*
326  * Command line configuration.
327  */
328
329 #undef CONFIG_WATCHDOG          /* watchdog disabled */
330
331 #ifdef CONFIG_MMC
332 #define CONFIG_FSL_ESDHC_PIN_MUX
333 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
334 #endif
335
336 /*
337  * Miscellaneous configurable options
338  */
339 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
340
341 /*
342  * For booting Linux, the board info and command line data
343  * have to be in the first 256 MB of memory, since this is
344  * the maximum mapped by the Linux kernel during initialization.
345  */
346 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
347 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
348
349 #if defined(CONFIG_CMD_KGDB)
350 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
351 #endif
352
353 /*
354  * Environment Configuration
355  */
356 #define CONFIG_ENV_OVERWRITE
357
358 #define CONFIG_HAS_FSL_DR_USB
359 #define CONFIG_USB_EHCI_FSL
360 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
361
362 #define CONFIG_NETDEV           "eth1"
363
364 #define CONFIG_HOSTNAME         "mpc837x_rdb"
365 #define CONFIG_ROOTPATH         "/nfsroot"
366 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
367 #define CONFIG_BOOTFILE         "uImage"
368                                 /* U-Boot image on TFTP server */
369 #define CONFIG_UBOOTPATH        "u-boot.bin"
370 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
371
372                                 /* default location for tftp and bootm */
373 #define CONFIG_LOADADDR         800000
374
375 #define CONFIG_EXTRA_ENV_SETTINGS \
376         "netdev=" CONFIG_NETDEV "\0"                            \
377         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
378         "tftpflash=tftp $loadaddr $uboot;"                              \
379                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
380                         " +$filesize; " \
381                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
382                         " +$filesize; " \
383                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
384                         " $filesize; "  \
385                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
386                         " +$filesize; " \
387                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
388                         " $filesize\0"  \
389         "fdtaddr=780000\0"                                              \
390         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
391         "ramdiskaddr=1000000\0"                                         \
392         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
393         "console=ttyS0\0"                                               \
394         "setbootargs=setenv bootargs "                                  \
395                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
396         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
397                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
398                                                         "$netdev:off "  \
399                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
400
401 #define CONFIG_NFSBOOTCOMMAND                                           \
402         "setenv rootdev /dev/nfs;"                                      \
403         "run setbootargs;"                                              \
404         "run setipargs;"                                                \
405         "tftp $loadaddr $bootfile;"                                     \
406         "tftp $fdtaddr $fdtfile;"                                       \
407         "bootm $loadaddr - $fdtaddr"
408
409 #define CONFIG_RAMBOOTCOMMAND                                           \
410         "setenv rootdev /dev/ram;"                                      \
411         "run setbootargs;"                                              \
412         "tftp $ramdiskaddr $ramdiskfile;"                               \
413         "tftp $loadaddr $bootfile;"                                     \
414         "tftp $fdtaddr $fdtfile;"                                       \
415         "bootm $loadaddr $ramdiskaddr $fdtaddr"
416
417 #endif  /* __CONFIG_H */