include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_HWCONFIG
  17
  18 /*
  19  * On-board devices
  20  */
  21 #define CONFIG_VSC7385_ENET
  22
  23 /*
  24  * System Clock Setup
  25  */
  26 #ifdef CONFIG_PCISLAVE
  27 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  28 #else
  29 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  30 #define CONFIG_PCIE
  31 #endif
  32
  33 #ifndef CONFIG_SYS_CLK_FREQ
  34 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  35 #endif
  36
  37 /*
  38  * Hardware Reset Configuration Word
  39  */
  40 #define CONFIG_SYS_HRCW_LOW (\
  41         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  42         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  43         HRCWL_SVCOD_DIV_2 |\
  44         HRCWL_CSB_TO_CLKIN_5X1 |\
  45         HRCWL_CORE_TO_CSB_2X1)
  46
  47 #ifdef CONFIG_PCISLAVE
  48 #define CONFIG_SYS_HRCW_HIGH (\
  49         HRCWH_PCI_AGENT |\
  50         HRCWH_PCI1_ARBITER_DISABLE |\
  51         HRCWH_CORE_ENABLE |\
  52         HRCWH_FROM_0XFFF00100 |\
  53         HRCWH_BOOTSEQ_DISABLE |\
  54         HRCWH_SW_WATCHDOG_DISABLE |\
  55         HRCWH_ROM_LOC_LOCAL_16BIT |\
  56         HRCWH_RL_EXT_LEGACY |\
  57         HRCWH_TSEC1M_IN_RGMII |\
  58         HRCWH_TSEC2M_IN_RGMII |\
  59         HRCWH_BIG_ENDIAN |\
  60         HRCWH_LDP_CLEAR)
  61 #else
  62 #define CONFIG_SYS_HRCW_HIGH (\
  63         HRCWH_PCI_HOST |\
  64         HRCWH_PCI1_ARBITER_ENABLE |\
  65         HRCWH_CORE_ENABLE |\
  66         HRCWH_FROM_0X00000100 |\
  67         HRCWH_BOOTSEQ_DISABLE |\
  68         HRCWH_SW_WATCHDOG_DISABLE |\
  69         HRCWH_ROM_LOC_LOCAL_16BIT |\
  70         HRCWH_RL_EXT_LEGACY |\
  71         HRCWH_TSEC1M_IN_RGMII |\
  72         HRCWH_TSEC2M_IN_RGMII |\
  73         HRCWH_BIG_ENDIAN |\
  74         HRCWH_LDP_CLEAR)
  75 #endif
  76
  77 /* System performance - define the value i.e. CONFIG_SYS_XXX
  78 */
  79
  80 /* Arbiter Configuration Register */
  81 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  82 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  83
  84 /* System Priority Control Regsiter */
  85 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  86
  87 /* System Clock Configuration Register */
  88 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  89 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  90 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  91
  92 /*
  93  * System IO Config
  94  */
  95 #define CONFIG_SYS_SICRH                0x08200000
  96 #define CONFIG_SYS_SICRL                0x00000000
  97
  98 /*
  99  * Output Buffer Impedance
 100  */
 101 #define CONFIG_SYS_OBIR         0x30100000
 102
 103 /*
 104  * IMMR new address
 105  */
 106 #define CONFIG_SYS_IMMR         0xE0000000
 107
 108 /*
 109  * Device configurations
 110  */
 111
 112 /* Vitesse 7385 */
 113
 114 #ifdef CONFIG_VSC7385_ENET
 115
 116 #define CONFIG_TSEC2
 117
 118 /* The flash address and size of the VSC7385 firmware image */
 119 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 120 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 121
 122 #endif
 123
 124 /*
 125  * DDR Setup
 126  */
 127 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 128 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 129 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 130 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 131 #define CONFIG_SYS_83XX_DDR_USES_CS0
 132
 133 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 134
 135 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 136 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 137
 138 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 139
 140 /*
 141  * Manually set up DDR parameters
 142  */
 143 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 144 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 145 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 146                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 147                                         | CSCONFIG_ROW_BIT_13 \
 148                                         | CSCONFIG_COL_BIT_10)
 149
 150 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 151 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 152                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 153                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 154                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 155                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 156                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 157                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 158                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 159                                 /* 0x00260802 */ /* DDR400 */
 160 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 161                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 162                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 163                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 164                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 165                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 166                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 167                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 168                                 /* 0x3937d322 */
 169 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 170                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 171                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 172                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 173                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 174                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 175                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 176                                 /* 0x02984cc8 */
 177
 178 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 179                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 180                                 /* 0x06090100 */
 181
 182 #if defined(CONFIG_DDR_2T_TIMING)
 183 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 184                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 185                                         | SDRAM_CFG_32_BE \
 186                                         | SDRAM_CFG_2T_EN)
 187                                         /* 0x43088000 */
 188 #else
 189 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 190                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 191                                         /* 0x43000000 */
 192 #endif
 193 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 194 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 195                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 196                                         /* 0x04400442 */ /* DDR400 */
 197 #define CONFIG_SYS_DDR_MODE2            0x00000000
 198
 199 /*
 200  * Memory test
 201  */
 202 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 203 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 204 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 205
 206 /*
 207  * The reserved memory
 208  */
 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 210
 211 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 212 #define CONFIG_SYS_RAMBOOT
 213 #else
 214 #undef  CONFIG_SYS_RAMBOOT
 215 #endif
 216
 217 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 218 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 219
 220 /*
 221  * Initial RAM Base Address Setup
 222  */
 223 #define CONFIG_SYS_INIT_RAM_LOCK        1
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 225 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 226 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 227                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 228
 229 /*
 230  * Local Bus Configuration & Clock Setup
 231  */
 232 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 233 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 234 #define CONFIG_SYS_LBC_LBCR             0x00000000
 235 #define CONFIG_FSL_ELBC         1
 236
 237 /*
 238  * FLASH on the Local Bus
 239  */
 240 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 241 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 242
 243 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 244
 245                                         /* Window base at flash base */
 246 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 247 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 248
 249 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 250                                 | BR_PS_16      /* 16 bit port */ \
 251                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 252                                 | BR_V)         /* valid */
 253 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 254                                 | OR_GPCM_XACS \
 255                                 | OR_GPCM_SCY_9 \
 256                                 | OR_GPCM_EHTR_SET \
 257                                 | OR_GPCM_EAD)
 258                                 /* 0xFF800191 */
 259
 260 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 261 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 262
 263 #undef  CONFIG_SYS_FLASH_CHECKSUM
 264 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 265 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 266
 267 /*
 268  * NAND Flash on the Local Bus
 269  */
 270 #define CONFIG_SYS_NAND_BASE    0xE0600000
 271 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 272                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 273                                 | BR_PS_8               /* 8 bit port */ \
 274                                 | BR_MS_FCM             /* MSEL = FCM */ \
 275                                 | BR_V)                 /* valid */
 276 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 277                                 | OR_FCM_CSCT \
 278                                 | OR_FCM_CST \
 279                                 | OR_FCM_CHT \
 280                                 | OR_FCM_SCY_1 \
 281                                 | OR_FCM_TRLX \
 282                                 | OR_FCM_EHTR)
 283 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 284 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 285
 286 /* Vitesse 7385 */
 287
 288 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 289
 290 #ifdef CONFIG_VSC7385_ENET
 291
 292 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 293                                         | BR_PS_8 \
 294                                         | BR_MS_GPCM \
 295                                         | BR_V)
 296                                         /* 0xF0000801 */
 297 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 298                                         | OR_GPCM_CSNT \
 299                                         | OR_GPCM_XACS \
 300                                         | OR_GPCM_SCY_15 \
 301                                         | OR_GPCM_SETA \
 302                                         | OR_GPCM_TRLX_SET \
 303                                         | OR_GPCM_EHTR_SET \
 304                                         | OR_GPCM_EAD)
 305                                         /* 0xfffe09ff */
 306
 307                                         /* Access Base */
 308 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 309 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 310
 311 #endif
 312
 313 /*
 314  * Serial Port
 315  */
 316 #define CONFIG_SYS_NS16550_SERIAL
 317 #define CONFIG_SYS_NS16550_REG_SIZE     1
 318 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 319
 320 #define CONFIG_SYS_BAUDRATE_TABLE \
 321                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 322
 323 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 324 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 325
 326 /* SERDES */
 327 #define CONFIG_FSL_SERDES
 328 #define CONFIG_FSL_SERDES1      0xe3000
 329 #define CONFIG_FSL_SERDES2      0xe3100
 330
 331 /* I2C */
 332 #define CONFIG_SYS_I2C
 333 #define CONFIG_SYS_I2C_FSL
 334 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 335 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 336 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 337 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 338
 339 /*
 340  * Config on-board RTC
 341  */
 342 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 343 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 344
 345 /*
 346  * General PCI
 347  * Addresses are mapped 1-1.
 348  */
 349 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 350 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 351 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 352 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 353 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 354 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 355 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 356 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 357 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 358
 359 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 360 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 361 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 362
 363 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 364 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 365 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 366 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 367 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 368 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 369 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 370 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 371 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 372
 373 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 374 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 375 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 376 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 377 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 378 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 379 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 380 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 381 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 382
 383 #ifdef CONFIG_PCI
 384 #define CONFIG_PCI_INDIRECT_BRIDGE
 385
 386 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 387 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 388 #endif  /* CONFIG_PCI */
 389
 390 /*
 391  * TSEC
 392  */
 393 #ifdef CONFIG_TSEC_ENET
 394
 395 #define CONFIG_GMII                     /* MII PHY management */
 396
 397 #define CONFIG_TSEC1
 398
 399 #ifdef CONFIG_TSEC1
 400 #define CONFIG_HAS_ETH0
 401 #define CONFIG_TSEC1_NAME               "TSEC0"
 402 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 403 #define TSEC1_PHY_ADDR                  2
 404 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 405 #define TSEC1_PHYIDX                    0
 406 #endif
 407
 408 #ifdef CONFIG_TSEC2
 409 #define CONFIG_HAS_ETH1
 410 #define CONFIG_TSEC2_NAME               "TSEC1"
 411 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 412 #define TSEC2_PHY_ADDR                  0x1c
 413 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 414 #define TSEC2_PHYIDX                    0
 415 #endif
 416
 417 /* Options are: TSEC[0-1] */
 418 #define CONFIG_ETHPRIME                 "TSEC0"
 419
 420 #endif
 421
 422 /*
 423  * SATA
 424  */
 425 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 426 #define CONFIG_SATA1
 427 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 428 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 429 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 430 #define CONFIG_SATA2
 431 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 432 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 433 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 434
 435 #ifdef CONFIG_FSL_SATA
 436 #define CONFIG_LBA48
 437 #endif
 438
 439 /*
 440  * Environment
 441  */
 442 #ifndef CONFIG_SYS_RAMBOOT
 443         #define CONFIG_ENV_ADDR         \
 444                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 445         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 446         #define CONFIG_ENV_SIZE         0x4000
 447 #else
 448         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 449         #define CONFIG_ENV_SIZE         0x2000
 450 #endif
 451
 452 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 453 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 454
 455 /*
 456  * BOOTP options
 457  */
 458 #define CONFIG_BOOTP_BOOTFILESIZE
 459
 460 /*
 461  * Command line configuration.
 462  */
 463
 464 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 465
 466 #ifdef CONFIG_MMC
 467 #define CONFIG_FSL_ESDHC_PIN_MUX
 468 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 469 #endif
 470
 471 /*
 472  * Miscellaneous configurable options
 473  */
 474 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 475
 476 /*
 477  * For booting Linux, the board info and command line data
 478  * have to be in the first 256 MB of memory, since this is
 479  * the maximum mapped by the Linux kernel during initialization.
 480  */
 481 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 482 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 483
 484 /*
 485  * Core HID Setup
 486  */
 487 #define CONFIG_SYS_HID0_INIT    0x000000000
 488 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 489                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 490 #define CONFIG_SYS_HID2         HID2_HBE
 491
 492 /*
 493  * MMU Setup
 494  */
 495
 496 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 497
 498 /* DDR: cache cacheable */
 499 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 500 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 501
 502 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 503                                 | BATL_PP_RW \
 504                                 | BATL_MEMCOHERENCE)
 505 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 506                                 | BATU_BL_256M \
 507                                 | BATU_VS \
 508                                 | BATU_VP)
 509 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 510 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 511
 512 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 513                                 | BATL_PP_RW \
 514                                 | BATL_MEMCOHERENCE)
 515 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 516                                 | BATU_BL_256M \
 517                                 | BATU_VS \
 518                                 | BATU_VP)
 519 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 520 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 521
 522 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 523 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 524                                 | BATL_PP_RW \
 525                                 | BATL_CACHEINHIBIT \
 526                                 | BATL_GUARDEDSTORAGE)
 527 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 528                                 | BATU_BL_8M \
 529                                 | BATU_VS \
 530                                 | BATU_VP)
 531 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 532 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 533
 534 /* L2 Switch: cache-inhibit and guarded */
 535 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 536                                 | BATL_PP_RW \
 537                                 | BATL_CACHEINHIBIT \
 538                                 | BATL_GUARDEDSTORAGE)
 539 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 540                                 | BATU_BL_128K \
 541                                 | BATU_VS \
 542                                 | BATU_VP)
 543 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 544 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 545
 546 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 547 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 548                                 | BATL_PP_RW \
 549                                 | BATL_MEMCOHERENCE)
 550 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 551                                 | BATU_BL_32M \
 552                                 | BATU_VS \
 553                                 | BATU_VP)
 554 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 555                                 | BATL_PP_RW \
 556                                 | BATL_CACHEINHIBIT \
 557                                 | BATL_GUARDEDSTORAGE)
 558 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 559
 560 /* Stack in dcache: cacheable, no memory coherence */
 561 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 562 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 563                                 | BATU_BL_128K \
 564                                 | BATU_VS \
 565                                 | BATU_VP)
 566 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 567 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 568
 569 #ifdef CONFIG_PCI
 570 /* PCI MEM space: cacheable */
 571 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 572                                 | BATL_PP_RW \
 573                                 | BATL_MEMCOHERENCE)
 574 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 575                                 | BATU_BL_256M \
 576                                 | BATU_VS \
 577                                 | BATU_VP)
 578 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 579 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 580 /* PCI MMIO space: cache-inhibit and guarded */
 581 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 582                                 | BATL_PP_RW \
 583                                 | BATL_CACHEINHIBIT \
 584                                 | BATL_GUARDEDSTORAGE)
 585 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 586                                 | BATU_BL_256M \
 587                                 | BATU_VS \
 588                                 | BATU_VP)
 589 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 590 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 591 #else
 592 #define CONFIG_SYS_IBAT6L       (0)
 593 #define CONFIG_SYS_IBAT6U       (0)
 594 #define CONFIG_SYS_IBAT7L       (0)
 595 #define CONFIG_SYS_IBAT7U       (0)
 596 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 597 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 598 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 599 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 600 #endif
 601
 602 #if defined(CONFIG_CMD_KGDB)
 603 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 604 #endif
 605
 606 /*
 607  * Environment Configuration
 608  */
 609 #define CONFIG_ENV_OVERWRITE
 610
 611 #define CONFIG_HAS_FSL_DR_USB
 612 #define CONFIG_USB_EHCI_FSL
 613 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 614
 615 #define CONFIG_NETDEV           "eth1"
 616
 617 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 618 #define CONFIG_ROOTPATH         "/nfsroot"
 619 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 620 #define CONFIG_BOOTFILE         "uImage"
 621                                 /* U-Boot image on TFTP server */
 622 #define CONFIG_UBOOTPATH        "u-boot.bin"
 623 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 624
 625                                 /* default location for tftp and bootm */
 626 #define CONFIG_LOADADDR         800000
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS \
 629         "netdev=" CONFIG_NETDEV "\0"                            \
 630         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 631         "tftpflash=tftp $loadaddr $uboot;"                              \
 632                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 633                         " +$filesize; " \
 634                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 635                         " +$filesize; " \
 636                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 637                         " $filesize; "  \
 638                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 639                         " +$filesize; " \
 640                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 641                         " $filesize\0"  \
 642         "fdtaddr=780000\0"                                              \
 643         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 644         "ramdiskaddr=1000000\0"                                         \
 645         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 646         "console=ttyS0\0"                                               \
 647         "setbootargs=setenv bootargs "                                  \
 648                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 649         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 650                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 651                                                         "$netdev:off "  \
 652                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 653
 654 #define CONFIG_NFSBOOTCOMMAND                                           \
 655         "setenv rootdev /dev/nfs;"                                      \
 656         "run setbootargs;"                                              \
 657         "run setipargs;"                                                \
 658         "tftp $loadaddr $bootfile;"                                     \
 659         "tftp $fdtaddr $fdtfile;"                                       \
 660         "bootm $loadaddr - $fdtaddr"
 661
 662 #define CONFIG_RAMBOOTCOMMAND                                           \
 663         "setenv rootdev /dev/ram;"                                      \
 664         "run setbootargs;"                                              \
 665         "tftp $ramdiskaddr $ramdiskfile;"                               \
 666         "tftp $loadaddr $bootfile;"                                     \
 667         "tftp $fdtaddr $fdtfile;"                                       \
 668         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 669
 670 #endif  /* __CONFIG_H */