1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
11 #include <linux/stringify.h>
14 * High Level Configuration Options
17 /* System performance - define the value i.e. CONFIG_SYS_XXX
20 /* System Clock Configuration Register */
21 #define CFG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
22 #define CFG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
23 #define CFG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
28 #define CFG_SYS_SICRH 0x08200000
29 #define CFG_SYS_SICRL 0x00000000
32 * Output Buffer Impedance
34 #define CFG_SYS_OBIR 0x30100000
37 * Device configurations
42 #ifdef CONFIG_VSC7385_ENET
44 /* The flash address and size of the VSC7385 firmware image */
45 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
46 #define CONFIG_VSC7385_IMAGE_SIZE 8192
53 #define CFG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
54 #define CFG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
56 #define CFG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
58 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
61 * Manually set up DDR parameters
63 #define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
64 #define CFG_SYS_DDR_CS0_BNDS 0x0000000f
65 #define CFG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
66 | CSCONFIG_ODT_WR_ONLY_CURRENT \
67 | CSCONFIG_ROW_BIT_13 \
68 | CSCONFIG_COL_BIT_10)
70 #define CFG_SYS_DDR_TIMING_3 0x00000000
71 #define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
72 | (0 << TIMING_CFG0_WRT_SHIFT) \
73 | (0 << TIMING_CFG0_RRT_SHIFT) \
74 | (0 << TIMING_CFG0_WWT_SHIFT) \
75 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
76 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
77 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
78 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
79 /* 0x00260802 */ /* DDR400 */
80 #define CFG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
81 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
82 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
83 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
84 | (13 << TIMING_CFG1_REFREC_SHIFT) \
85 | (3 << TIMING_CFG1_WRREC_SHIFT) \
86 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
87 | (2 << TIMING_CFG1_WRTORD_SHIFT))
89 #define CFG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
90 | (5 << TIMING_CFG2_CPO_SHIFT) \
91 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
92 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
93 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
94 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
95 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
98 #define CFG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
99 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
102 #define CFG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
103 | SDRAM_CFG_SDRAM_TYPE_DDR2)
105 #define CFG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
106 #define CFG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
107 | (0x0442 << SDRAM_MODE_SD_SHIFT))
108 /* 0x04400442 */ /* DDR400 */
109 #define CFG_SYS_DDR_MODE2 0x00000000
114 #undef CFG_SYS_DRAM_TEST /* memory test, takes time */
117 * The reserved memory
121 * Initial RAM Base Address Setup
123 #define CFG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
124 #define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
127 * FLASH on the Local Bus
129 #define CFG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
130 #define CFG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
133 * NAND Flash on the Local Bus
135 #define CFG_SYS_NAND_BASE 0xE0600000
140 #define CFG_SYS_VSC7385_BASE 0xF0000000
145 #define CFG_SYS_NS16550_CLK get_bus_freq(0)
147 #define CFG_SYS_BAUDRATE_TABLE \
148 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
150 #define CFG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
151 #define CFG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
154 #define CONFIG_FSL_SERDES1 0xe3000
155 #define CONFIG_FSL_SERDES2 0xe3100
158 #define CFG_SYS_I2C_NOPROBES { {0, 0x51} }
161 * Config on-board RTC
163 #define CFG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
167 * Addresses are mapped 1-1.
169 #define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
170 #define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
171 #define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
172 #define CFG_SYS_PCIE1_IO_PHYS 0xB8000000
174 #define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
175 #define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
176 #define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
177 #define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
180 #define CONFIG_FSL_ESDHC_PIN_MUX
181 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR
185 * Miscellaneous configurable options
189 * For booting Linux, the board info and command line data
190 * have to be in the first 256 MB of memory, since this is
191 * the maximum mapped by the Linux kernel during initialization.
193 #define CFG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
196 * Environment Configuration
199 #define CONFIG_NETDEV "eth1"
201 #define CONFIG_HOSTNAME "mpc837x_rdb"
202 #define CONFIG_ROOTPATH "/nfsroot"
203 /* U-Boot image on TFTP server */
204 #define CONFIG_UBOOTPATH "u-boot.bin"
205 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
207 #define CONFIG_EXTRA_ENV_SETTINGS \
208 "netdev=" CONFIG_NETDEV "\0" \
209 "uboot=" CONFIG_UBOOTPATH "\0" \
210 "tftpflash=tftp $loadaddr $uboot;" \
211 "protect off " __stringify(CONFIG_TEXT_BASE) \
213 "erase " __stringify(CONFIG_TEXT_BASE) \
215 "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
217 "protect on " __stringify(CONFIG_TEXT_BASE) \
219 "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) \
222 "fdtfile=" CONFIG_FDTFILE "\0" \
223 "ramdiskaddr=1000000\0" \
224 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
226 "setbootargs=setenv bootargs " \
227 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
228 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
229 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
231 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
233 #endif /* __CONFIG_H */