2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * High Level Configuration Options
28 #define CONFIG_E300 1 /* E300 family */
29 #define CONFIG_MPC83xx 1 /* MPC83xx family */
30 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */
31 #define CONFIG_MPC837XERDB 1
35 #define CONFIG_BOARD_EARLY_INIT_F
36 #define CONFIG_MISC_INIT_R
37 #define CONFIG_HWCONFIG
42 #define CONFIG_TSEC_ENET /* TSEC Ethernet support */
43 #define CONFIG_VSC7385_ENET
48 #ifdef CONFIG_PCISLAVE
49 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */
51 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
55 #ifndef CONFIG_SYS_CLK_FREQ
56 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
60 * Hardware Reset Configuration Word
62 #define CONFIG_SYS_HRCW_LOW (\
63 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
64 HRCWL_DDR_TO_SCB_CLK_1X1 |\
66 HRCWL_CSB_TO_CLKIN_5X1 |\
67 HRCWL_CORE_TO_CSB_2X1)
69 #ifdef CONFIG_PCISLAVE
70 #define CONFIG_SYS_HRCW_HIGH (\
72 HRCWH_PCI1_ARBITER_DISABLE |\
74 HRCWH_FROM_0XFFF00100 |\
75 HRCWH_BOOTSEQ_DISABLE |\
76 HRCWH_SW_WATCHDOG_DISABLE |\
77 HRCWH_ROM_LOC_LOCAL_16BIT |\
78 HRCWH_RL_EXT_LEGACY |\
79 HRCWH_TSEC1M_IN_RGMII |\
80 HRCWH_TSEC2M_IN_RGMII |\
84 #define CONFIG_SYS_HRCW_HIGH (\
86 HRCWH_PCI1_ARBITER_ENABLE |\
88 HRCWH_FROM_0X00000100 |\
89 HRCWH_BOOTSEQ_DISABLE |\
90 HRCWH_SW_WATCHDOG_DISABLE |\
91 HRCWH_ROM_LOC_LOCAL_16BIT |\
92 HRCWH_RL_EXT_LEGACY |\
93 HRCWH_TSEC1M_IN_RGMII |\
94 HRCWH_TSEC2M_IN_RGMII |\
99 /* System performance - define the value i.e. CONFIG_SYS_XXX
102 /* Arbiter Configuration Register */
103 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
104 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
106 /* System Priority Control Regsiter */
107 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
109 /* System Clock Configuration Register */
110 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
111 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
112 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
117 #define CONFIG_SYS_SICRH 0x08200000
118 #define CONFIG_SYS_SICRL 0x00000000
121 * Output Buffer Impedance
123 #define CONFIG_SYS_OBIR 0x30100000
128 #define CONFIG_SYS_IMMR 0xE0000000
131 * Device configurations
136 #ifdef CONFIG_VSC7385_ENET
140 /* The flash address and size of the VSC7385 firmware image */
141 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
142 #define CONFIG_VSC7385_IMAGE_SIZE 8192
149 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
150 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
151 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
152 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
153 #define CONFIG_SYS_83XX_DDR_USES_CS0
155 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
157 #undef CONFIG_DDR_ECC /* support DDR ECC function */
158 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
160 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
163 * Manually set up DDR parameters
165 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
166 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
167 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
168 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
170 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
171 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
172 | (0 << TIMING_CFG0_WRT_SHIFT) \
173 | (0 << TIMING_CFG0_RRT_SHIFT) \
174 | (0 << TIMING_CFG0_WWT_SHIFT) \
175 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
176 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
177 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
178 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
180 /* 0x00260802 */ /* DDR400 */
181 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
182 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
183 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
184 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
185 | (13 << TIMING_CFG1_REFREC_SHIFT) \
186 | (3 << TIMING_CFG1_WRREC_SHIFT) \
187 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
188 | (2 << TIMING_CFG1_WRTORD_SHIFT))
191 #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
193 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
194 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
197 #if defined(CONFIG_DDR_2T_TIMING)
198 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
199 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
203 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
204 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
207 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
208 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
209 | (0x0442 << SDRAM_MODE_SD_SHIFT))
210 /* 0x04400442 */ /* DDR400 */
211 #define CONFIG_SYS_DDR_MODE2 0x00000000
216 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
217 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
218 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
221 * The reserved memory
223 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
225 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
226 #define CONFIG_SYS_RAMBOOT
228 #undef CONFIG_SYS_RAMBOOT
231 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
232 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
235 * Initial RAM Base Address Setup
237 #define CONFIG_SYS_INIT_RAM_LOCK 1
238 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
239 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
240 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
241 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
244 * Local Bus Configuration & Clock Setup
246 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
247 #define CONFIG_SYS_LBC_LBCR 0x00000000
250 * FLASH on the Local Bus
252 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
253 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
254 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
255 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
257 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
258 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
259 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
261 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
262 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
264 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
265 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
267 #define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
272 /* 0xFF806FF7 TODO SLOW 8 MB flash size */
274 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
275 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
277 #undef CONFIG_SYS_FLASH_CHECKSUM
278 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
279 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
282 * NAND Flash on the Local Bus
284 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
285 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \
286 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
287 BR_PS_8 | /* Port Size = 8 bit */ \
288 BR_MS_FCM | /* MSEL = FCM */ \
290 #define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
297 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
298 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
302 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
304 #ifdef CONFIG_VSC7385_ENET
306 #define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
307 #define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
308 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */
309 #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
316 #define CONFIG_CONS_INDEX 1
317 #undef CONFIG_SERIAL_SOFTWARE_FIFO
318 #define CONFIG_SYS_NS16550
319 #define CONFIG_SYS_NS16550_SERIAL
320 #define CONFIG_SYS_NS16550_REG_SIZE 1
321 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
323 #define CONFIG_SYS_BAUDRATE_TABLE \
324 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
326 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
327 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
330 #define CONFIG_FSL_SERDES
331 #define CONFIG_FSL_SERDES1 0xe3000
332 #define CONFIG_FSL_SERDES2 0xe3100
334 /* Use the HUSH parser */
335 #define CONFIG_SYS_HUSH_PARSER
336 #ifdef CONFIG_SYS_HUSH_PARSER
337 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
340 /* Pass open firmware flat tree */
341 #define CONFIG_OF_LIBFDT 1
342 #define CONFIG_OF_BOARD_SETUP 1
343 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
345 #define CONFIG_SYS_64BIT_STRTOUL 1
346 #define CONFIG_SYS_64BIT_VSPRINTF 1
349 #define CONFIG_HARD_I2C /* I2C with hardware support */
350 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
351 #define CONFIG_FSL_I2C
352 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
353 #define CONFIG_SYS_I2C_SLAVE 0x7F
354 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
355 #define CONFIG_SYS_I2C_OFFSET 0x3000
356 #define CONFIG_SYS_I2C2_OFFSET 0x3100
359 * Config on-board RTC
361 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
362 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
366 * Addresses are mapped 1-1.
368 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
369 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
370 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
371 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
372 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
373 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
374 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
375 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
376 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
378 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
379 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
380 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
382 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
383 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
384 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
385 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
386 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
387 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
388 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
389 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
390 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
392 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
393 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
394 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
395 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
396 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
397 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
398 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
399 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
400 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
403 #define CONFIG_NET_MULTI
404 #define CONFIG_PCI_PNP /* do pci plug-and-play */
406 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
407 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
408 #endif /* CONFIG_PCI */
413 #ifdef CONFIG_TSEC_ENET
415 #define CONFIG_NET_MULTI
416 #define CONFIG_GMII /* MII PHY management */
421 #define CONFIG_HAS_ETH0
422 #define CONFIG_TSEC1_NAME "TSEC0"
423 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
424 #define TSEC1_PHY_ADDR 2
425 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
426 #define TSEC1_PHYIDX 0
430 #define CONFIG_HAS_ETH1
431 #define CONFIG_TSEC2_NAME "TSEC1"
432 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
433 #define TSEC2_PHY_ADDR 0x1c
434 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
435 #define TSEC2_PHYIDX 0
438 /* Options are: TSEC[0-1] */
439 #define CONFIG_ETHPRIME "TSEC0"
446 #define CONFIG_LIBATA
447 #define CONFIG_FSL_SATA
449 #define CONFIG_SYS_SATA_MAX_DEVICE 2
451 #define CONFIG_SYS_SATA1_OFFSET 0x18000
452 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
453 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
455 #define CONFIG_SYS_SATA2_OFFSET 0x19000
456 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
457 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
459 #ifdef CONFIG_FSL_SATA
461 #define CONFIG_CMD_SATA
462 #define CONFIG_DOS_PARTITION
463 #define CONFIG_CMD_EXT2
469 #ifndef CONFIG_SYS_RAMBOOT
470 #define CONFIG_ENV_IS_IN_FLASH 1
471 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
472 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
473 #define CONFIG_ENV_SIZE 0x4000
475 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
476 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
477 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
478 #define CONFIG_ENV_SIZE 0x2000
481 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
482 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
487 #define CONFIG_BOOTP_BOOTFILESIZE
488 #define CONFIG_BOOTP_BOOTPATH
489 #define CONFIG_BOOTP_GATEWAY
490 #define CONFIG_BOOTP_HOSTNAME
494 * Command line configuration.
496 #include <config_cmd_default.h>
498 #define CONFIG_CMD_PING
499 #define CONFIG_CMD_I2C
500 #define CONFIG_CMD_MII
501 #define CONFIG_CMD_DATE
503 #if defined(CONFIG_PCI)
504 #define CONFIG_CMD_PCI
507 #if defined(CONFIG_SYS_RAMBOOT)
508 #undef CONFIG_CMD_SAVEENV
509 #undef CONFIG_CMD_LOADS
512 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
514 #undef CONFIG_WATCHDOG /* watchdog disabled */
519 #define CONFIG_FSL_ESDHC
520 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
521 #define CONFIG_CMD_MMC
522 #define CONFIG_GENERIC_MMC
523 #define CONFIG_CMD_EXT2
524 #define CONFIG_CMD_FAT
525 #define CONFIG_DOS_PARTITION
529 * Miscellaneous configurable options
531 #define CONFIG_SYS_LONGHELP /* undef to save memory */
532 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
533 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
535 #if defined(CONFIG_CMD_KGDB)
536 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
538 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
541 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
542 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
543 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
544 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
547 * For booting Linux, the board info and command line data
548 * have to be in the first 8 MB of memory, since this is
549 * the maximum mapped by the Linux kernel during initialization.
551 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
556 #define CONFIG_SYS_HID0_INIT 0x000000000
557 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
558 #define CONFIG_SYS_HID2 HID2_HBE
564 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
566 /* DDR: cache cacheable */
567 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
568 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
570 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
571 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
572 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
573 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
575 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
576 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
577 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
578 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
580 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
581 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
582 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
583 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
584 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
585 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
587 /* L2 Switch: cache-inhibit and guarded */
588 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
589 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
591 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
592 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
594 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
595 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
596 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
597 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
598 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
599 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
601 /* Stack in dcache: cacheable, no memory coherence */
602 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
603 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
604 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
605 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
608 /* PCI MEM space: cacheable */
609 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
610 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
611 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
612 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
613 /* PCI MMIO space: cache-inhibit and guarded */
614 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
615 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
616 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
617 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
618 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
620 #define CONFIG_SYS_IBAT6L (0)
621 #define CONFIG_SYS_IBAT6U (0)
622 #define CONFIG_SYS_IBAT7L (0)
623 #define CONFIG_SYS_IBAT7U (0)
624 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
625 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
626 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
627 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
631 * Internal Definitions
635 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
636 #define BOOTFLAG_WARM 0x02 /* Software reboot */
638 #if defined(CONFIG_CMD_KGDB)
639 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
640 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
644 * Environment Configuration
646 #define CONFIG_ENV_OVERWRITE
648 #ifdef CONFIG_HAS_ETH0
649 #define CONFIG_ETHADDR 00:04:9f:ef:04:01
652 #ifdef CONFIG_HAS_ETH1
653 #define CONFIG_ETH1ADDR 00:04:9f:ef:04:02
656 #define CONFIG_HAS_FSL_DR_USB
658 #define CONFIG_IPADDR 10.0.0.2
659 #define CONFIG_SERVERIP 10.0.0.1
660 #define CONFIG_GATEWAYIP 10.0.0.1
661 #define CONFIG_NETMASK 255.0.0.0
662 #define CONFIG_NETDEV eth1
664 #define CONFIG_HOSTNAME mpc837x_rdb
665 #define CONFIG_ROOTPATH /nfsroot
666 #define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
667 #define CONFIG_BOOTFILE uImage
668 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
669 #define CONFIG_FDTFILE mpc8379_rdb.dtb
671 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
672 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
673 #define CONFIG_BAUDRATE 115200
675 #define XMK_STR(x) #x
676 #define MK_STR(x) XMK_STR(x)
678 #define CONFIG_EXTRA_ENV_SETTINGS \
679 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
680 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
681 "tftpflash=tftp $loadaddr $uboot;" \
682 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
683 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
684 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
685 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
686 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
688 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
689 "ramdiskaddr=1000000\0" \
690 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
692 "setbootargs=setenv bootargs " \
693 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
694 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
695 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
696 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
698 #define CONFIG_NFSBOOTCOMMAND \
699 "setenv rootdev /dev/nfs;" \
702 "tftp $loadaddr $bootfile;" \
703 "tftp $fdtaddr $fdtfile;" \
704 "bootm $loadaddr - $fdtaddr"
706 #define CONFIG_RAMBOOTCOMMAND \
707 "setenv rootdev /dev/ram;" \
709 "tftp $ramdiskaddr $ramdiskfile;" \
710 "tftp $loadaddr $bootfile;" \
711 "tftp $fdtaddr $fdtfile;" \
712 "bootm $loadaddr $ramdiskaddr $fdtaddr"
717 #endif /* __CONFIG_H */