1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
15 #define CONFIG_MPC837x 1 /* MPC837x CPU specific */
16 #define CONFIG_MPC837XERDB 1
18 #define CONFIG_MISC_INIT_R
19 #define CONFIG_HWCONFIG
24 #define CONFIG_VSC7385_ENET
29 #ifdef CONFIG_PCISLAVE
30 #define CONFIG_83XX_PCICLK 66666667 /* in HZ */
32 #define CONFIG_83XX_CLKIN 66666667 /* in Hz */
36 #ifndef CONFIG_SYS_CLK_FREQ
37 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
41 * Hardware Reset Configuration Word
43 #define CONFIG_SYS_HRCW_LOW (\
44 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
45 HRCWL_DDR_TO_SCB_CLK_1X1 |\
47 HRCWL_CSB_TO_CLKIN_5X1 |\
48 HRCWL_CORE_TO_CSB_2X1)
50 #ifdef CONFIG_PCISLAVE
51 #define CONFIG_SYS_HRCW_HIGH (\
53 HRCWH_PCI1_ARBITER_DISABLE |\
55 HRCWH_FROM_0XFFF00100 |\
56 HRCWH_BOOTSEQ_DISABLE |\
57 HRCWH_SW_WATCHDOG_DISABLE |\
58 HRCWH_ROM_LOC_LOCAL_16BIT |\
59 HRCWH_RL_EXT_LEGACY |\
60 HRCWH_TSEC1M_IN_RGMII |\
61 HRCWH_TSEC2M_IN_RGMII |\
65 #define CONFIG_SYS_HRCW_HIGH (\
67 HRCWH_PCI1_ARBITER_ENABLE |\
69 HRCWH_FROM_0X00000100 |\
70 HRCWH_BOOTSEQ_DISABLE |\
71 HRCWH_SW_WATCHDOG_DISABLE |\
72 HRCWH_ROM_LOC_LOCAL_16BIT |\
73 HRCWH_RL_EXT_LEGACY |\
74 HRCWH_TSEC1M_IN_RGMII |\
75 HRCWH_TSEC2M_IN_RGMII |\
80 /* System performance - define the value i.e. CONFIG_SYS_XXX
83 /* Arbiter Configuration Register */
84 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
85 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
87 /* System Priority Control Regsiter */
88 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
90 /* System Clock Configuration Register */
91 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
92 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
93 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
98 #define CONFIG_SYS_SICRH 0x08200000
99 #define CONFIG_SYS_SICRL 0x00000000
102 * Output Buffer Impedance
104 #define CONFIG_SYS_OBIR 0x30100000
109 #define CONFIG_SYS_IMMR 0xE0000000
112 * Device configurations
117 #ifdef CONFIG_VSC7385_ENET
121 /* The flash address and size of the VSC7385 firmware image */
122 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
123 #define CONFIG_VSC7385_IMAGE_SIZE 8192
130 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
132 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
133 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
134 #define CONFIG_SYS_83XX_DDR_USES_CS0
136 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
138 #undef CONFIG_DDR_ECC /* support DDR ECC function */
139 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
141 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
144 * Manually set up DDR parameters
146 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
147 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
148 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
149 | CSCONFIG_ODT_WR_ONLY_CURRENT \
150 | CSCONFIG_ROW_BIT_13 \
151 | CSCONFIG_COL_BIT_10)
153 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
154 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
155 | (0 << TIMING_CFG0_WRT_SHIFT) \
156 | (0 << TIMING_CFG0_RRT_SHIFT) \
157 | (0 << TIMING_CFG0_WWT_SHIFT) \
158 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
159 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
160 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
161 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
162 /* 0x00260802 */ /* DDR400 */
163 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
164 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
165 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
166 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
167 | (13 << TIMING_CFG1_REFREC_SHIFT) \
168 | (3 << TIMING_CFG1_WRREC_SHIFT) \
169 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
170 | (2 << TIMING_CFG1_WRTORD_SHIFT))
172 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
173 | (5 << TIMING_CFG2_CPO_SHIFT) \
174 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
175 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
176 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
177 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
178 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
181 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
182 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
185 #if defined(CONFIG_DDR_2T_TIMING)
186 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
187 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
192 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
193 | SDRAM_CFG_SDRAM_TYPE_DDR2)
196 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
197 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
198 | (0x0442 << SDRAM_MODE_SD_SHIFT))
199 /* 0x04400442 */ /* DDR400 */
200 #define CONFIG_SYS_DDR_MODE2 0x00000000
205 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
206 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
207 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
210 * The reserved memory
212 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
214 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
215 #define CONFIG_SYS_RAMBOOT
217 #undef CONFIG_SYS_RAMBOOT
220 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
221 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
224 * Initial RAM Base Address Setup
226 #define CONFIG_SYS_INIT_RAM_LOCK 1
227 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
228 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
229 #define CONFIG_SYS_GBL_DATA_OFFSET \
230 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
233 * Local Bus Configuration & Clock Setup
235 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
236 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
237 #define CONFIG_SYS_LBC_LBCR 0x00000000
238 #define CONFIG_FSL_ELBC 1
241 * FLASH on the Local Bus
243 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
244 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
245 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
246 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
248 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
249 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
250 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
252 /* Window base at flash base */
253 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
254 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
256 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
257 | BR_PS_16 /* 16 bit port */ \
258 | BR_MS_GPCM /* MSEL = GPCM */ \
260 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
267 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
268 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
270 #undef CONFIG_SYS_FLASH_CHECKSUM
271 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
272 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
275 * NAND Flash on the Local Bus
277 #define CONFIG_SYS_NAND_BASE 0xE0600000
278 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
279 | BR_DECC_CHK_GEN /* Use HW ECC */ \
280 | BR_PS_8 /* 8 bit port */ \
281 | BR_MS_FCM /* MSEL = FCM */ \
283 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
290 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
291 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
295 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
297 #ifdef CONFIG_VSC7385_ENET
299 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
304 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
315 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
316 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
327 #define CONFIG_SYS_BAUDRATE_TABLE \
328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
334 #define CONFIG_FSL_SERDES
335 #define CONFIG_FSL_SERDES1 0xe3000
336 #define CONFIG_FSL_SERDES2 0xe3100
339 #define CONFIG_SYS_I2C
340 #define CONFIG_SYS_I2C_FSL
341 #define CONFIG_SYS_FSL_I2C_SPEED 400000
342 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
343 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
344 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
347 * Config on-board RTC
349 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
350 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
354 * Addresses are mapped 1-1.
356 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
357 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
358 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
359 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
360 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
361 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
362 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
363 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
364 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
366 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
367 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
368 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
370 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
371 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
372 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
373 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
374 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
375 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
376 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
377 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
378 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
380 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
381 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
382 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
383 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
384 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
385 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
386 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
387 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
388 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
391 #define CONFIG_PCI_INDIRECT_BRIDGE
393 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
394 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
395 #endif /* CONFIG_PCI */
400 #ifdef CONFIG_TSEC_ENET
402 #define CONFIG_GMII /* MII PHY management */
407 #define CONFIG_HAS_ETH0
408 #define CONFIG_TSEC1_NAME "TSEC0"
409 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
410 #define TSEC1_PHY_ADDR 2
411 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412 #define TSEC1_PHYIDX 0
416 #define CONFIG_HAS_ETH1
417 #define CONFIG_TSEC2_NAME "TSEC1"
418 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
419 #define TSEC2_PHY_ADDR 0x1c
420 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
421 #define TSEC2_PHYIDX 0
424 /* Options are: TSEC[0-1] */
425 #define CONFIG_ETHPRIME "TSEC0"
432 #define CONFIG_SYS_SATA_MAX_DEVICE 2
434 #define CONFIG_SYS_SATA1_OFFSET 0x18000
435 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
436 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
438 #define CONFIG_SYS_SATA2_OFFSET 0x19000
439 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
440 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
442 #ifdef CONFIG_FSL_SATA
449 #ifndef CONFIG_SYS_RAMBOOT
450 #define CONFIG_ENV_ADDR \
451 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
452 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
453 #define CONFIG_ENV_SIZE 0x4000
455 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
456 #define CONFIG_ENV_SIZE 0x2000
459 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
460 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
465 #define CONFIG_BOOTP_BOOTFILESIZE
468 * Command line configuration.
471 #undef CONFIG_WATCHDOG /* watchdog disabled */
474 #define CONFIG_FSL_ESDHC_PIN_MUX
475 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
479 * Miscellaneous configurable options
481 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
484 * For booting Linux, the board info and command line data
485 * have to be in the first 256 MB of memory, since this is
486 * the maximum mapped by the Linux kernel during initialization.
488 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
489 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
494 #define CONFIG_SYS_HID0_INIT 0x000000000
495 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
496 | HID0_ENABLE_INSTRUCTION_CACHE)
497 #define CONFIG_SYS_HID2 HID2_HBE
503 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
505 /* DDR: cache cacheable */
506 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
507 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
509 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
512 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
516 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
517 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
519 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
522 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
526 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
527 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
529 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
530 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
532 | BATL_CACHEINHIBIT \
533 | BATL_GUARDEDSTORAGE)
534 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
538 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
539 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
541 /* L2 Switch: cache-inhibit and guarded */
542 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
544 | BATL_CACHEINHIBIT \
545 | BATL_GUARDEDSTORAGE)
546 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
550 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
551 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
553 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
554 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
557 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
561 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
563 | BATL_CACHEINHIBIT \
564 | BATL_GUARDEDSTORAGE)
565 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
567 /* Stack in dcache: cacheable, no memory coherence */
568 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
569 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
573 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
574 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
577 /* PCI MEM space: cacheable */
578 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
581 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
585 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
586 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
587 /* PCI MMIO space: cache-inhibit and guarded */
588 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
590 | BATL_CACHEINHIBIT \
591 | BATL_GUARDEDSTORAGE)
592 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
596 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
597 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
599 #define CONFIG_SYS_IBAT6L (0)
600 #define CONFIG_SYS_IBAT6U (0)
601 #define CONFIG_SYS_IBAT7L (0)
602 #define CONFIG_SYS_IBAT7U (0)
603 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
604 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
605 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
606 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
609 #if defined(CONFIG_CMD_KGDB)
610 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
614 * Environment Configuration
616 #define CONFIG_ENV_OVERWRITE
618 #define CONFIG_HAS_FSL_DR_USB
619 #define CONFIG_USB_EHCI_FSL
620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
622 #define CONFIG_NETDEV "eth1"
624 #define CONFIG_HOSTNAME "mpc837x_rdb"
625 #define CONFIG_ROOTPATH "/nfsroot"
626 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
627 #define CONFIG_BOOTFILE "uImage"
628 /* U-Boot image on TFTP server */
629 #define CONFIG_UBOOTPATH "u-boot.bin"
630 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
632 /* default location for tftp and bootm */
633 #define CONFIG_LOADADDR 800000
635 #define CONFIG_EXTRA_ENV_SETTINGS \
636 "netdev=" CONFIG_NETDEV "\0" \
637 "uboot=" CONFIG_UBOOTPATH "\0" \
638 "tftpflash=tftp $loadaddr $uboot;" \
639 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
641 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
643 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
645 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
647 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
650 "fdtfile=" CONFIG_FDTFILE "\0" \
651 "ramdiskaddr=1000000\0" \
652 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
654 "setbootargs=setenv bootargs " \
655 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
656 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
657 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
659 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
661 #define CONFIG_NFSBOOTCOMMAND \
662 "setenv rootdev /dev/nfs;" \
665 "tftp $loadaddr $bootfile;" \
666 "tftp $fdtaddr $fdtfile;" \
667 "bootm $loadaddr - $fdtaddr"
669 #define CONFIG_RAMBOOTCOMMAND \
670 "setenv rootdev /dev/ram;" \
672 "tftp $ramdiskaddr $ramdiskfile;" \
673 "tftp $loadaddr $bootfile;" \
674 "tftp $fdtaddr $fdtfile;" \
675 "bootm $loadaddr $ramdiskaddr $fdtaddr"
677 #endif /* __CONFIG_H */