1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_HWCONFIG
21 #define CONFIG_VSC7385_ENET
23 /* System performance - define the value i.e. CONFIG_SYS_XXX
26 /* Arbiter Configuration Register */
27 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
28 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
30 /* System Priority Control Regsiter */
31 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
33 /* System Clock Configuration Register */
34 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
35 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
36 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
41 #define CONFIG_SYS_SICRH 0x08200000
42 #define CONFIG_SYS_SICRL 0x00000000
45 * Output Buffer Impedance
47 #define CONFIG_SYS_OBIR 0x30100000
52 #define CONFIG_SYS_IMMR 0xE0000000
55 * Device configurations
60 #ifdef CONFIG_VSC7385_ENET
64 /* The flash address and size of the VSC7385 firmware image */
65 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
66 #define CONFIG_VSC7385_IMAGE_SIZE 8192
73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
77 #define CONFIG_SYS_83XX_DDR_USES_CS0
79 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
81 #undef CONFIG_DDR_ECC /* support DDR ECC function */
82 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
84 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
87 * Manually set up DDR parameters
89 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
90 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
91 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
92 | CSCONFIG_ODT_WR_ONLY_CURRENT \
93 | CSCONFIG_ROW_BIT_13 \
94 | CSCONFIG_COL_BIT_10)
96 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
97 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
98 | (0 << TIMING_CFG0_WRT_SHIFT) \
99 | (0 << TIMING_CFG0_RRT_SHIFT) \
100 | (0 << TIMING_CFG0_WWT_SHIFT) \
101 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
102 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
103 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
104 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
105 /* 0x00260802 */ /* DDR400 */
106 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
107 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
108 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
109 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
110 | (13 << TIMING_CFG1_REFREC_SHIFT) \
111 | (3 << TIMING_CFG1_WRREC_SHIFT) \
112 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
113 | (2 << TIMING_CFG1_WRTORD_SHIFT))
115 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
116 | (5 << TIMING_CFG2_CPO_SHIFT) \
117 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
118 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
119 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
120 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
121 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
124 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
125 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
128 #if defined(CONFIG_DDR_2T_TIMING)
129 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
130 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
135 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
136 | SDRAM_CFG_SDRAM_TYPE_DDR2)
139 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
140 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
141 | (0x0442 << SDRAM_MODE_SD_SHIFT))
142 /* 0x04400442 */ /* DDR400 */
143 #define CONFIG_SYS_DDR_MODE2 0x00000000
148 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
149 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
150 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
153 * The reserved memory
155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
157 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
158 #define CONFIG_SYS_RAMBOOT
160 #undef CONFIG_SYS_RAMBOOT
163 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
164 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
167 * Initial RAM Base Address Setup
169 #define CONFIG_SYS_INIT_RAM_LOCK 1
170 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
171 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
172 #define CONFIG_SYS_GBL_DATA_OFFSET \
173 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
176 * Local Bus Configuration & Clock Setup
178 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
179 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
180 #define CONFIG_SYS_LBC_LBCR 0x00000000
181 #define CONFIG_FSL_ELBC 1
184 * FLASH on the Local Bus
186 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
187 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
189 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
191 /* Window base at flash base */
192 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
193 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
195 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
196 | BR_PS_16 /* 16 bit port */ \
197 | BR_MS_GPCM /* MSEL = GPCM */ \
199 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
206 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
207 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
209 #undef CONFIG_SYS_FLASH_CHECKSUM
210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
214 * NAND Flash on the Local Bus
216 #define CONFIG_SYS_NAND_BASE 0xE0600000
217 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
218 | BR_DECC_CHK_GEN /* Use HW ECC */ \
219 | BR_PS_8 /* 8 bit port */ \
220 | BR_MS_FCM /* MSEL = FCM */ \
222 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
229 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
230 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
234 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
236 #ifdef CONFIG_VSC7385_ENET
238 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
243 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
254 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
255 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
262 #define CONFIG_SYS_NS16550_SERIAL
263 #define CONFIG_SYS_NS16550_REG_SIZE 1
264 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
266 #define CONFIG_SYS_BAUDRATE_TABLE \
267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
269 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
270 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
273 #define CONFIG_FSL_SERDES
274 #define CONFIG_FSL_SERDES1 0xe3000
275 #define CONFIG_FSL_SERDES2 0xe3100
278 #define CONFIG_SYS_I2C
279 #define CONFIG_SYS_I2C_FSL
280 #define CONFIG_SYS_FSL_I2C_SPEED 400000
281 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
282 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
283 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
286 * Config on-board RTC
288 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
289 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
293 * Addresses are mapped 1-1.
295 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
296 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
297 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
298 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
299 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
300 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
301 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
302 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
303 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
305 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
306 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
307 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
309 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
310 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
311 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
312 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
313 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
314 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
315 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
316 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
317 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
319 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
320 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
321 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
322 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
323 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
324 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
325 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
326 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
327 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
330 #define CONFIG_PCI_INDIRECT_BRIDGE
332 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
333 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
334 #endif /* CONFIG_PCI */
339 #ifdef CONFIG_TSEC_ENET
341 #define CONFIG_GMII /* MII PHY management */
346 #define CONFIG_HAS_ETH0
347 #define CONFIG_TSEC1_NAME "TSEC0"
348 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
349 #define TSEC1_PHY_ADDR 2
350 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
351 #define TSEC1_PHYIDX 0
355 #define CONFIG_HAS_ETH1
356 #define CONFIG_TSEC2_NAME "TSEC1"
357 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
358 #define TSEC2_PHY_ADDR 0x1c
359 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
360 #define TSEC2_PHYIDX 0
363 /* Options are: TSEC[0-1] */
364 #define CONFIG_ETHPRIME "TSEC0"
371 #define CONFIG_SYS_SATA_MAX_DEVICE 2
373 #define CONFIG_SYS_SATA1_OFFSET 0x18000
374 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
375 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
377 #define CONFIG_SYS_SATA2_OFFSET 0x19000
378 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
379 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
381 #ifdef CONFIG_FSL_SATA
388 #ifndef CONFIG_SYS_RAMBOOT
389 #define CONFIG_ENV_ADDR \
390 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
391 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
392 #define CONFIG_ENV_SIZE 0x4000
394 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
395 #define CONFIG_ENV_SIZE 0x2000
398 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
399 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
404 #define CONFIG_BOOTP_BOOTFILESIZE
407 * Command line configuration.
410 #undef CONFIG_WATCHDOG /* watchdog disabled */
413 #define CONFIG_FSL_ESDHC_PIN_MUX
414 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
418 * Miscellaneous configurable options
420 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
423 * For booting Linux, the board info and command line data
424 * have to be in the first 256 MB of memory, since this is
425 * the maximum mapped by the Linux kernel during initialization.
427 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
428 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
433 #define CONFIG_SYS_HID0_INIT 0x000000000
434 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
435 | HID0_ENABLE_INSTRUCTION_CACHE)
436 #define CONFIG_SYS_HID2 HID2_HBE
438 #if defined(CONFIG_CMD_KGDB)
439 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
443 * Environment Configuration
445 #define CONFIG_ENV_OVERWRITE
447 #define CONFIG_HAS_FSL_DR_USB
448 #define CONFIG_USB_EHCI_FSL
449 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
451 #define CONFIG_NETDEV "eth1"
453 #define CONFIG_HOSTNAME "mpc837x_rdb"
454 #define CONFIG_ROOTPATH "/nfsroot"
455 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
456 #define CONFIG_BOOTFILE "uImage"
457 /* U-Boot image on TFTP server */
458 #define CONFIG_UBOOTPATH "u-boot.bin"
459 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
461 /* default location for tftp and bootm */
462 #define CONFIG_LOADADDR 800000
464 #define CONFIG_EXTRA_ENV_SETTINGS \
465 "netdev=" CONFIG_NETDEV "\0" \
466 "uboot=" CONFIG_UBOOTPATH "\0" \
467 "tftpflash=tftp $loadaddr $uboot;" \
468 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
470 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
472 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
474 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
476 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
479 "fdtfile=" CONFIG_FDTFILE "\0" \
480 "ramdiskaddr=1000000\0" \
481 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
483 "setbootargs=setenv bootargs " \
484 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
485 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
486 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
488 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
490 #define CONFIG_NFSBOOTCOMMAND \
491 "setenv rootdev /dev/nfs;" \
494 "tftp $loadaddr $bootfile;" \
495 "tftp $fdtaddr $fdtfile;" \
496 "bootm $loadaddr - $fdtaddr"
498 #define CONFIG_RAMBOOTCOMMAND \
499 "setenv rootdev /dev/ram;" \
501 "tftp $ramdiskaddr $ramdiskfile;" \
502 "tftp $loadaddr $bootfile;" \
503 "tftp $fdtaddr $fdtfile;" \
504 "bootm $loadaddr $ramdiskaddr $fdtaddr"
506 #endif /* __CONFIG_H */