include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15
  16 #define CONFIG_HWCONFIG
  17
  18 /*
  19  * On-board devices
  20  */
  21 #define CONFIG_VSC7385_ENET
  22
  23 /* System performance - define the value i.e. CONFIG_SYS_XXX
  24 */
  25
  26 /* System Priority Control Regsiter */
  27 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  28
  29 /* System Clock Configuration Register */
  30 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  31 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  32 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  33
  34 /*
  35  * System IO Config
  36  */
  37 #define CONFIG_SYS_SICRH                0x08200000
  38 #define CONFIG_SYS_SICRL                0x00000000
  39
  40 /*
  41  * Output Buffer Impedance
  42  */
  43 #define CONFIG_SYS_OBIR         0x30100000
  44
  45 /*
  46  * Device configurations
  47  */
  48
  49 /* Vitesse 7385 */
  50
  51 #ifdef CONFIG_VSC7385_ENET
  52
  53 #define CONFIG_TSEC2
  54
  55 /* The flash address and size of the VSC7385 firmware image */
  56 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
  57 #define CONFIG_VSC7385_IMAGE_SIZE       8192
  58
  59 #endif
  60
  61 /*
  62  * DDR Setup
  63  */
  64 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  65 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  67 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
  68 #define CONFIG_SYS_83XX_DDR_USES_CS0
  69
  70 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
  71
  72 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
  73 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
  74
  75 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
  76
  77 /*
  78  * Manually set up DDR parameters
  79  */
  80 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  81 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  82 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  83                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
  84                                         | CSCONFIG_ROW_BIT_13 \
  85                                         | CSCONFIG_COL_BIT_10)
  86
  87 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  88 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  89                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  90                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  91                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  92                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  93                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  94                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  95                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  96                                 /* 0x00260802 */ /* DDR400 */
  97 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
  98                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  99                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 100                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 101                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 102                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 103                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 104                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 105                                 /* 0x3937d322 */
 106 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 107                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 108                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 109                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 110                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 111                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 112                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 113                                 /* 0x02984cc8 */
 114
 115 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 116                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 117                                 /* 0x06090100 */
 118
 119 #if defined(CONFIG_DDR_2T_TIMING)
 120 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 121                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 122                                         | SDRAM_CFG_32_BE \
 123                                         | SDRAM_CFG_2T_EN)
 124                                         /* 0x43088000 */
 125 #else
 126 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 127                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 128                                         /* 0x43000000 */
 129 #endif
 130 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 131 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 132                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 133                                         /* 0x04400442 */ /* DDR400 */
 134 #define CONFIG_SYS_DDR_MODE2            0x00000000
 135
 136 /*
 137  * Memory test
 138  */
 139 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 140 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 141 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 142
 143 /*
 144  * The reserved memory
 145  */
 146 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 147
 148 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 149 #define CONFIG_SYS_RAMBOOT
 150 #else
 151 #undef  CONFIG_SYS_RAMBOOT
 152 #endif
 153
 154 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 155 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 156
 157 /*
 158  * Initial RAM Base Address Setup
 159  */
 160 #define CONFIG_SYS_INIT_RAM_LOCK        1
 161 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 162 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 163 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 164                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 165
 166 /*
 167  * Local Bus Configuration & Clock Setup
 168  */
 169 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 170 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 171 #define CONFIG_SYS_LBC_LBCR             0x00000000
 172 #define CONFIG_FSL_ELBC         1
 173
 174 /*
 175  * FLASH on the Local Bus
 176  */
 177 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 178 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 179
 180 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 181
 182
 183 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 184 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 185
 186 #undef  CONFIG_SYS_FLASH_CHECKSUM
 187 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 188 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 189
 190 /*
 191  * NAND Flash on the Local Bus
 192  */
 193 #define CONFIG_SYS_NAND_BASE    0xE0600000
 194
 195
 196 /* Vitesse 7385 */
 197
 198 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 199
 200 #ifdef CONFIG_VSC7385_ENET
 201
 202
 203 #endif
 204
 205 /*
 206  * Serial Port
 207  */
 208 #define CONFIG_SYS_NS16550_SERIAL
 209 #define CONFIG_SYS_NS16550_REG_SIZE     1
 210 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 211
 212 #define CONFIG_SYS_BAUDRATE_TABLE \
 213                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 214
 215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 216 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 217
 218 /* SERDES */
 219 #define CONFIG_FSL_SERDES
 220 #define CONFIG_FSL_SERDES1      0xe3000
 221 #define CONFIG_FSL_SERDES2      0xe3100
 222
 223 /* I2C */
 224 #define CONFIG_SYS_I2C
 225 #define CONFIG_SYS_I2C_FSL
 226 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 227 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 228 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 229 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 230
 231 /*
 232  * Config on-board RTC
 233  */
 234 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 235 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 236
 237 /*
 238  * General PCI
 239  * Addresses are mapped 1-1.
 240  */
 241 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 242 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 243 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 244 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 245 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 246 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 247 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 248 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 249 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 250
 251 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 252 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 253 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 254
 255 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 256 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 257 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 258 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 259 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 260 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 261 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 262 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 263 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 264
 265 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 266 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 267 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 268 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 269 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 270 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 271 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 272 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 273 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 274
 275 #ifdef CONFIG_PCI
 276 #define CONFIG_PCI_INDIRECT_BRIDGE
 277
 278 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 279 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 280 #endif  /* CONFIG_PCI */
 281
 282 /*
 283  * TSEC
 284  */
 285 #ifdef CONFIG_TSEC_ENET
 286
 287 #define CONFIG_GMII                     /* MII PHY management */
 288
 289 #define CONFIG_TSEC1
 290
 291 #ifdef CONFIG_TSEC1
 292 #define CONFIG_HAS_ETH0
 293 #define CONFIG_TSEC1_NAME               "TSEC0"
 294 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 295 #define TSEC1_PHY_ADDR                  2
 296 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 297 #define TSEC1_PHYIDX                    0
 298 #endif
 299
 300 #ifdef CONFIG_TSEC2
 301 #define CONFIG_HAS_ETH1
 302 #define CONFIG_TSEC2_NAME               "TSEC1"
 303 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 304 #define TSEC2_PHY_ADDR                  0x1c
 305 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 306 #define TSEC2_PHYIDX                    0
 307 #endif
 308
 309 /* Options are: TSEC[0-1] */
 310 #define CONFIG_ETHPRIME                 "TSEC0"
 311
 312 #endif
 313
 314 /*
 315  * SATA
 316  */
 317 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 318 #define CONFIG_SATA1
 319 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 320 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 321 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 322 #define CONFIG_SATA2
 323 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 324 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 325 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 326
 327 #ifdef CONFIG_FSL_SATA
 328 #define CONFIG_LBA48
 329 #endif
 330
 331 /*
 332  * Environment
 333  */
 334 #ifndef CONFIG_SYS_RAMBOOT
 335         #define CONFIG_ENV_ADDR         \
 336                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 337         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 338         #define CONFIG_ENV_SIZE         0x4000
 339 #else
 340         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 341         #define CONFIG_ENV_SIZE         0x2000
 342 #endif
 343
 344 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 346
 347 /*
 348  * BOOTP options
 349  */
 350 #define CONFIG_BOOTP_BOOTFILESIZE
 351
 352 /*
 353  * Command line configuration.
 354  */
 355
 356 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 357
 358 #ifdef CONFIG_MMC
 359 #define CONFIG_FSL_ESDHC_PIN_MUX
 360 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 361 #endif
 362
 363 /*
 364  * Miscellaneous configurable options
 365  */
 366 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 367
 368 /*
 369  * For booting Linux, the board info and command line data
 370  * have to be in the first 256 MB of memory, since this is
 371  * the maximum mapped by the Linux kernel during initialization.
 372  */
 373 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 374 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 375
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 378 #endif
 379
 380 /*
 381  * Environment Configuration
 382  */
 383 #define CONFIG_ENV_OVERWRITE
 384
 385 #define CONFIG_HAS_FSL_DR_USB
 386 #define CONFIG_USB_EHCI_FSL
 387 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 388
 389 #define CONFIG_NETDEV           "eth1"
 390
 391 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 392 #define CONFIG_ROOTPATH         "/nfsroot"
 393 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 394 #define CONFIG_BOOTFILE         "uImage"
 395                                 /* U-Boot image on TFTP server */
 396 #define CONFIG_UBOOTPATH        "u-boot.bin"
 397 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 398
 399                                 /* default location for tftp and bootm */
 400 #define CONFIG_LOADADDR         800000
 401
 402 #define CONFIG_EXTRA_ENV_SETTINGS \
 403         "netdev=" CONFIG_NETDEV "\0"                            \
 404         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 405         "tftpflash=tftp $loadaddr $uboot;"                              \
 406                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 407                         " +$filesize; " \
 408                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 409                         " +$filesize; " \
 410                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 411                         " $filesize; "  \
 412                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 413                         " +$filesize; " \
 414                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 415                         " $filesize\0"  \
 416         "fdtaddr=780000\0"                                              \
 417         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 418         "ramdiskaddr=1000000\0"                                         \
 419         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 420         "console=ttyS0\0"                                               \
 421         "setbootargs=setenv bootargs "                                  \
 422                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 423         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 424                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 425                                                         "$netdev:off "  \
 426                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 427
 428 #define CONFIG_NFSBOOTCOMMAND                                           \
 429         "setenv rootdev /dev/nfs;"                                      \
 430         "run setbootargs;"                                              \
 431         "run setipargs;"                                                \
 432         "tftp $loadaddr $bootfile;"                                     \
 433         "tftp $fdtaddr $fdtfile;"                                       \
 434         "bootm $loadaddr - $fdtaddr"
 435
 436 #define CONFIG_RAMBOOTCOMMAND                                           \
 437         "setenv rootdev /dev/ram;"                                      \
 438         "run setbootargs;"                                              \
 439         "tftp $ramdiskaddr $ramdiskfile;"                               \
 440         "tftp $loadaddr $bootfile;"                                     \
 441         "tftp $fdtaddr $fdtfile;"                                       \
 442         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 443
 444 #endif  /* __CONFIG_H */