include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC837XERDB      1
  16
  17 #define CONFIG_HWCONFIG
  18
  19 /*
  20  * On-board devices
  21  */
  22 #define CONFIG_VSC7385_ENET
  23
  24 /*
  25  * System Clock Setup
  26  */
  27 #ifdef CONFIG_PCISLAVE
  28 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  29 #else
  30 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  31 #define CONFIG_PCIE
  32 #endif
  33
  34 #ifndef CONFIG_SYS_CLK_FREQ
  35 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  36 #endif
  37
  38 /*
  39  * Hardware Reset Configuration Word
  40  */
  41 #define CONFIG_SYS_HRCW_LOW (\
  42         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  43         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  44         HRCWL_SVCOD_DIV_2 |\
  45         HRCWL_CSB_TO_CLKIN_5X1 |\
  46         HRCWL_CORE_TO_CSB_2X1)
  47
  48 #ifdef CONFIG_PCISLAVE
  49 #define CONFIG_SYS_HRCW_HIGH (\
  50         HRCWH_PCI_AGENT |\
  51         HRCWH_PCI1_ARBITER_DISABLE |\
  52         HRCWH_CORE_ENABLE |\
  53         HRCWH_FROM_0XFFF00100 |\
  54         HRCWH_BOOTSEQ_DISABLE |\
  55         HRCWH_SW_WATCHDOG_DISABLE |\
  56         HRCWH_ROM_LOC_LOCAL_16BIT |\
  57         HRCWH_RL_EXT_LEGACY |\
  58         HRCWH_TSEC1M_IN_RGMII |\
  59         HRCWH_TSEC2M_IN_RGMII |\
  60         HRCWH_BIG_ENDIAN |\
  61         HRCWH_LDP_CLEAR)
  62 #else
  63 #define CONFIG_SYS_HRCW_HIGH (\
  64         HRCWH_PCI_HOST |\
  65         HRCWH_PCI1_ARBITER_ENABLE |\
  66         HRCWH_CORE_ENABLE |\
  67         HRCWH_FROM_0X00000100 |\
  68         HRCWH_BOOTSEQ_DISABLE |\
  69         HRCWH_SW_WATCHDOG_DISABLE |\
  70         HRCWH_ROM_LOC_LOCAL_16BIT |\
  71         HRCWH_RL_EXT_LEGACY |\
  72         HRCWH_TSEC1M_IN_RGMII |\
  73         HRCWH_TSEC2M_IN_RGMII |\
  74         HRCWH_BIG_ENDIAN |\
  75         HRCWH_LDP_CLEAR)
  76 #endif
  77
  78 /* System performance - define the value i.e. CONFIG_SYS_XXX
  79 */
  80
  81 /* Arbiter Configuration Register */
  82 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  83 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  84
  85 /* System Priority Control Regsiter */
  86 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  87
  88 /* System Clock Configuration Register */
  89 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  90 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  91 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  92
  93 /*
  94  * System IO Config
  95  */
  96 #define CONFIG_SYS_SICRH                0x08200000
  97 #define CONFIG_SYS_SICRL                0x00000000
  98
  99 /*
 100  * Output Buffer Impedance
 101  */
 102 #define CONFIG_SYS_OBIR         0x30100000
 103
 104 /*
 105  * IMMR new address
 106  */
 107 #define CONFIG_SYS_IMMR         0xE0000000
 108
 109 /*
 110  * Device configurations
 111  */
 112
 113 /* Vitesse 7385 */
 114
 115 #ifdef CONFIG_VSC7385_ENET
 116
 117 #define CONFIG_TSEC2
 118
 119 /* The flash address and size of the VSC7385 firmware image */
 120 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 121 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 122
 123 #endif
 124
 125 /*
 126  * DDR Setup
 127  */
 128 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 129 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 130 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 131 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 132 #define CONFIG_SYS_83XX_DDR_USES_CS0
 133
 134 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 135
 136 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 137 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 138
 139 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 140
 141 /*
 142  * Manually set up DDR parameters
 143  */
 144 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 145 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 146 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 147                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 148                                         | CSCONFIG_ROW_BIT_13 \
 149                                         | CSCONFIG_COL_BIT_10)
 150
 151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 152 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 153                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 154                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 155                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 156                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 157                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 158                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 159                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 160                                 /* 0x00260802 */ /* DDR400 */
 161 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 162                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 163                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 164                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 165                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 166                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 167                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 168                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 169                                 /* 0x3937d322 */
 170 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 171                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 172                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 173                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 174                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 175                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 176                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 177                                 /* 0x02984cc8 */
 178
 179 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 180                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 181                                 /* 0x06090100 */
 182
 183 #if defined(CONFIG_DDR_2T_TIMING)
 184 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 185                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 186                                         | SDRAM_CFG_32_BE \
 187                                         | SDRAM_CFG_2T_EN)
 188                                         /* 0x43088000 */
 189 #else
 190 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 191                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 192                                         /* 0x43000000 */
 193 #endif
 194 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 195 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 196                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 197                                         /* 0x04400442 */ /* DDR400 */
 198 #define CONFIG_SYS_DDR_MODE2            0x00000000
 199
 200 /*
 201  * Memory test
 202  */
 203 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 204 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 205 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 206
 207 /*
 208  * The reserved memory
 209  */
 210 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 211
 212 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 213 #define CONFIG_SYS_RAMBOOT
 214 #else
 215 #undef  CONFIG_SYS_RAMBOOT
 216 #endif
 217
 218 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 219 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 220
 221 /*
 222  * Initial RAM Base Address Setup
 223  */
 224 #define CONFIG_SYS_INIT_RAM_LOCK        1
 225 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 226 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 227 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 228                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229
 230 /*
 231  * Local Bus Configuration & Clock Setup
 232  */
 233 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 234 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 235 #define CONFIG_SYS_LBC_LBCR             0x00000000
 236 #define CONFIG_FSL_ELBC         1
 237
 238 /*
 239  * FLASH on the Local Bus
 240  */
 241 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 242 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 243
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 245
 246                                         /* Window base at flash base */
 247 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 248 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 249
 250 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 251                                 | BR_PS_16      /* 16 bit port */ \
 252                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 253                                 | BR_V)         /* valid */
 254 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 255                                 | OR_GPCM_XACS \
 256                                 | OR_GPCM_SCY_9 \
 257                                 | OR_GPCM_EHTR_SET \
 258                                 | OR_GPCM_EAD)
 259                                 /* 0xFF800191 */
 260
 261 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 262 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 263
 264 #undef  CONFIG_SYS_FLASH_CHECKSUM
 265 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 266 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 267
 268 /*
 269  * NAND Flash on the Local Bus
 270  */
 271 #define CONFIG_SYS_NAND_BASE    0xE0600000
 272 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 273                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 274                                 | BR_PS_8               /* 8 bit port */ \
 275                                 | BR_MS_FCM             /* MSEL = FCM */ \
 276                                 | BR_V)                 /* valid */
 277 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 278                                 | OR_FCM_CSCT \
 279                                 | OR_FCM_CST \
 280                                 | OR_FCM_CHT \
 281                                 | OR_FCM_SCY_1 \
 282                                 | OR_FCM_TRLX \
 283                                 | OR_FCM_EHTR)
 284 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 285 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 286
 287 /* Vitesse 7385 */
 288
 289 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 290
 291 #ifdef CONFIG_VSC7385_ENET
 292
 293 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 294                                         | BR_PS_8 \
 295                                         | BR_MS_GPCM \
 296                                         | BR_V)
 297                                         /* 0xF0000801 */
 298 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 299                                         | OR_GPCM_CSNT \
 300                                         | OR_GPCM_XACS \
 301                                         | OR_GPCM_SCY_15 \
 302                                         | OR_GPCM_SETA \
 303                                         | OR_GPCM_TRLX_SET \
 304                                         | OR_GPCM_EHTR_SET \
 305                                         | OR_GPCM_EAD)
 306                                         /* 0xfffe09ff */
 307
 308                                         /* Access Base */
 309 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 310 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 311
 312 #endif
 313
 314 /*
 315  * Serial Port
 316  */
 317 #define CONFIG_SYS_NS16550_SERIAL
 318 #define CONFIG_SYS_NS16550_REG_SIZE     1
 319 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 320
 321 #define CONFIG_SYS_BAUDRATE_TABLE \
 322                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 323
 324 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 325 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 326
 327 /* SERDES */
 328 #define CONFIG_FSL_SERDES
 329 #define CONFIG_FSL_SERDES1      0xe3000
 330 #define CONFIG_FSL_SERDES2      0xe3100
 331
 332 /* I2C */
 333 #define CONFIG_SYS_I2C
 334 #define CONFIG_SYS_I2C_FSL
 335 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 336 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 337 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 338 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 339
 340 /*
 341  * Config on-board RTC
 342  */
 343 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 344 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 345
 346 /*
 347  * General PCI
 348  * Addresses are mapped 1-1.
 349  */
 350 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 351 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 352 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 353 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 354 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 355 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 356 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 357 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 358 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 359
 360 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 361 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 362 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 363
 364 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 365 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 366 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 367 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 368 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 369 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 370 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 371 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 372 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 373
 374 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 375 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 376 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 377 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 378 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 379 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 380 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 381 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 382 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 383
 384 #ifdef CONFIG_PCI
 385 #define CONFIG_PCI_INDIRECT_BRIDGE
 386
 387 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 388 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 389 #endif  /* CONFIG_PCI */
 390
 391 /*
 392  * TSEC
 393  */
 394 #ifdef CONFIG_TSEC_ENET
 395
 396 #define CONFIG_GMII                     /* MII PHY management */
 397
 398 #define CONFIG_TSEC1
 399
 400 #ifdef CONFIG_TSEC1
 401 #define CONFIG_HAS_ETH0
 402 #define CONFIG_TSEC1_NAME               "TSEC0"
 403 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 404 #define TSEC1_PHY_ADDR                  2
 405 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 406 #define TSEC1_PHYIDX                    0
 407 #endif
 408
 409 #ifdef CONFIG_TSEC2
 410 #define CONFIG_HAS_ETH1
 411 #define CONFIG_TSEC2_NAME               "TSEC1"
 412 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 413 #define TSEC2_PHY_ADDR                  0x1c
 414 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 415 #define TSEC2_PHYIDX                    0
 416 #endif
 417
 418 /* Options are: TSEC[0-1] */
 419 #define CONFIG_ETHPRIME                 "TSEC0"
 420
 421 #endif
 422
 423 /*
 424  * SATA
 425  */
 426 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 427 #define CONFIG_SATA1
 428 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 429 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 430 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 431 #define CONFIG_SATA2
 432 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 433 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 434 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 435
 436 #ifdef CONFIG_FSL_SATA
 437 #define CONFIG_LBA48
 438 #endif
 439
 440 /*
 441  * Environment
 442  */
 443 #ifndef CONFIG_SYS_RAMBOOT
 444         #define CONFIG_ENV_ADDR         \
 445                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 446         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 447         #define CONFIG_ENV_SIZE         0x4000
 448 #else
 449         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 450         #define CONFIG_ENV_SIZE         0x2000
 451 #endif
 452
 453 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 454 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 455
 456 /*
 457  * BOOTP options
 458  */
 459 #define CONFIG_BOOTP_BOOTFILESIZE
 460
 461 /*
 462  * Command line configuration.
 463  */
 464
 465 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 466
 467 #ifdef CONFIG_MMC
 468 #define CONFIG_FSL_ESDHC_PIN_MUX
 469 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 470 #endif
 471
 472 /*
 473  * Miscellaneous configurable options
 474  */
 475 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 476
 477 /*
 478  * For booting Linux, the board info and command line data
 479  * have to be in the first 256 MB of memory, since this is
 480  * the maximum mapped by the Linux kernel during initialization.
 481  */
 482 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 483 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 484
 485 /*
 486  * Core HID Setup
 487  */
 488 #define CONFIG_SYS_HID0_INIT    0x000000000
 489 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 490                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 491 #define CONFIG_SYS_HID2         HID2_HBE
 492
 493 /*
 494  * MMU Setup
 495  */
 496
 497 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 498
 499 /* DDR: cache cacheable */
 500 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 501 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 502
 503 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 504                                 | BATL_PP_RW \
 505                                 | BATL_MEMCOHERENCE)
 506 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 507                                 | BATU_BL_256M \
 508                                 | BATU_VS \
 509                                 | BATU_VP)
 510 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 511 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 512
 513 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 514                                 | BATL_PP_RW \
 515                                 | BATL_MEMCOHERENCE)
 516 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 517                                 | BATU_BL_256M \
 518                                 | BATU_VS \
 519                                 | BATU_VP)
 520 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 521 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 522
 523 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 524 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 525                                 | BATL_PP_RW \
 526                                 | BATL_CACHEINHIBIT \
 527                                 | BATL_GUARDEDSTORAGE)
 528 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 529                                 | BATU_BL_8M \
 530                                 | BATU_VS \
 531                                 | BATU_VP)
 532 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 533 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 534
 535 /* L2 Switch: cache-inhibit and guarded */
 536 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 537                                 | BATL_PP_RW \
 538                                 | BATL_CACHEINHIBIT \
 539                                 | BATL_GUARDEDSTORAGE)
 540 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 541                                 | BATU_BL_128K \
 542                                 | BATU_VS \
 543                                 | BATU_VP)
 544 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 545 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 546
 547 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 548 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 549                                 | BATL_PP_RW \
 550                                 | BATL_MEMCOHERENCE)
 551 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 552                                 | BATU_BL_32M \
 553                                 | BATU_VS \
 554                                 | BATU_VP)
 555 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 556                                 | BATL_PP_RW \
 557                                 | BATL_CACHEINHIBIT \
 558                                 | BATL_GUARDEDSTORAGE)
 559 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 560
 561 /* Stack in dcache: cacheable, no memory coherence */
 562 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 563 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 564                                 | BATU_BL_128K \
 565                                 | BATU_VS \
 566                                 | BATU_VP)
 567 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 568 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 569
 570 #ifdef CONFIG_PCI
 571 /* PCI MEM space: cacheable */
 572 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 573                                 | BATL_PP_RW \
 574                                 | BATL_MEMCOHERENCE)
 575 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 576                                 | BATU_BL_256M \
 577                                 | BATU_VS \
 578                                 | BATU_VP)
 579 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 580 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 581 /* PCI MMIO space: cache-inhibit and guarded */
 582 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 583                                 | BATL_PP_RW \
 584                                 | BATL_CACHEINHIBIT \
 585                                 | BATL_GUARDEDSTORAGE)
 586 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 587                                 | BATU_BL_256M \
 588                                 | BATU_VS \
 589                                 | BATU_VP)
 590 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 591 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 592 #else
 593 #define CONFIG_SYS_IBAT6L       (0)
 594 #define CONFIG_SYS_IBAT6U       (0)
 595 #define CONFIG_SYS_IBAT7L       (0)
 596 #define CONFIG_SYS_IBAT7U       (0)
 597 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 598 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 599 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 600 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 601 #endif
 602
 603 #if defined(CONFIG_CMD_KGDB)
 604 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 605 #endif
 606
 607 /*
 608  * Environment Configuration
 609  */
 610 #define CONFIG_ENV_OVERWRITE
 611
 612 #define CONFIG_HAS_FSL_DR_USB
 613 #define CONFIG_USB_EHCI_FSL
 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 615
 616 #define CONFIG_NETDEV           "eth1"
 617
 618 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 619 #define CONFIG_ROOTPATH         "/nfsroot"
 620 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 621 #define CONFIG_BOOTFILE         "uImage"
 622                                 /* U-Boot image on TFTP server */
 623 #define CONFIG_UBOOTPATH        "u-boot.bin"
 624 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 625
 626                                 /* default location for tftp and bootm */
 627 #define CONFIG_LOADADDR         800000
 628
 629 #define CONFIG_EXTRA_ENV_SETTINGS \
 630         "netdev=" CONFIG_NETDEV "\0"                            \
 631         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 632         "tftpflash=tftp $loadaddr $uboot;"                              \
 633                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 634                         " +$filesize; " \
 635                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 636                         " +$filesize; " \
 637                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 638                         " $filesize; "  \
 639                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 640                         " +$filesize; " \
 641                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 642                         " $filesize\0"  \
 643         "fdtaddr=780000\0"                                              \
 644         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 645         "ramdiskaddr=1000000\0"                                         \
 646         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 647         "console=ttyS0\0"                                               \
 648         "setbootargs=setenv bootargs "                                  \
 649                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 650         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 651                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 652                                                         "$netdev:off "  \
 653                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 654
 655 #define CONFIG_NFSBOOTCOMMAND                                           \
 656         "setenv rootdev /dev/nfs;"                                      \
 657         "run setbootargs;"                                              \
 658         "run setipargs;"                                                \
 659         "tftp $loadaddr $bootfile;"                                     \
 660         "tftp $fdtaddr $fdtfile;"                                       \
 661         "bootm $loadaddr - $fdtaddr"
 662
 663 #define CONFIG_RAMBOOTCOMMAND                                           \
 664         "setenv rootdev /dev/ram;"                                      \
 665         "run setbootargs;"                                              \
 666         "tftp $ramdiskaddr $ramdiskfile;"                               \
 667         "tftp $loadaddr $bootfile;"                                     \
 668         "tftp $fdtaddr $fdtfile;"                                       \
 669         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 670
 671 #endif  /* __CONFIG_H */