include/configs/MPC837XERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Kevin Lam <kevin.lam@freescale.com>
   5  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  */
  14 #define CONFIG_E300             1 /* E300 family */
  15 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
  16 #define CONFIG_MPC837XERDB      1
  17
  18 #define CONFIG_HWCONFIG
  19
  20 /*
  21  * On-board devices
  22  */
  23 #define CONFIG_VSC7385_ENET
  24
  25 /*
  26  * System Clock Setup
  27  */
  28 #ifdef CONFIG_PCISLAVE
  29 #define CONFIG_83XX_PCICLK      66666667 /* in HZ */
  30 #else
  31 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  32 #define CONFIG_PCIE
  33 #endif
  34
  35 #ifndef CONFIG_SYS_CLK_FREQ
  36 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  37 #endif
  38
  39 /*
  40  * Hardware Reset Configuration Word
  41  */
  42 #define CONFIG_SYS_HRCW_LOW (\
  43         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  44         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  45         HRCWL_SVCOD_DIV_2 |\
  46         HRCWL_CSB_TO_CLKIN_5X1 |\
  47         HRCWL_CORE_TO_CSB_2X1)
  48
  49 #ifdef CONFIG_PCISLAVE
  50 #define CONFIG_SYS_HRCW_HIGH (\
  51         HRCWH_PCI_AGENT |\
  52         HRCWH_PCI1_ARBITER_DISABLE |\
  53         HRCWH_CORE_ENABLE |\
  54         HRCWH_FROM_0XFFF00100 |\
  55         HRCWH_BOOTSEQ_DISABLE |\
  56         HRCWH_SW_WATCHDOG_DISABLE |\
  57         HRCWH_ROM_LOC_LOCAL_16BIT |\
  58         HRCWH_RL_EXT_LEGACY |\
  59         HRCWH_TSEC1M_IN_RGMII |\
  60         HRCWH_TSEC2M_IN_RGMII |\
  61         HRCWH_BIG_ENDIAN |\
  62         HRCWH_LDP_CLEAR)
  63 #else
  64 #define CONFIG_SYS_HRCW_HIGH (\
  65         HRCWH_PCI_HOST |\
  66         HRCWH_PCI1_ARBITER_ENABLE |\
  67         HRCWH_CORE_ENABLE |\
  68         HRCWH_FROM_0X00000100 |\
  69         HRCWH_BOOTSEQ_DISABLE |\
  70         HRCWH_SW_WATCHDOG_DISABLE |\
  71         HRCWH_ROM_LOC_LOCAL_16BIT |\
  72         HRCWH_RL_EXT_LEGACY |\
  73         HRCWH_TSEC1M_IN_RGMII |\
  74         HRCWH_TSEC2M_IN_RGMII |\
  75         HRCWH_BIG_ENDIAN |\
  76         HRCWH_LDP_CLEAR)
  77 #endif
  78
  79 /* System performance - define the value i.e. CONFIG_SYS_XXX
  80 */
  81
  82 /* Arbiter Configuration Register */
  83 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  84 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  85
  86 /* System Priority Control Regsiter */
  87 #define CONFIG_SYS_SPCR_TSECEP  3       /* eTSEC1&2 emergency priority (0-3) */
  88
  89 /* System Clock Configuration Register */
  90 #define CONFIG_SYS_SCCR_TSEC1CM 1               /* eTSEC1 clock mode (0-3) */
  91 #define CONFIG_SYS_SCCR_TSEC2CM 1               /* eTSEC2 clock mode (0-3) */
  92 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
  93
  94 /*
  95  * System IO Config
  96  */
  97 #define CONFIG_SYS_SICRH                0x08200000
  98 #define CONFIG_SYS_SICRL                0x00000000
  99
 100 /*
 101  * Output Buffer Impedance
 102  */
 103 #define CONFIG_SYS_OBIR         0x30100000
 104
 105 /*
 106  * IMMR new address
 107  */
 108 #define CONFIG_SYS_IMMR         0xE0000000
 109
 110 /*
 111  * Device configurations
 112  */
 113
 114 /* Vitesse 7385 */
 115
 116 #ifdef CONFIG_VSC7385_ENET
 117
 118 #define CONFIG_TSEC2
 119
 120 /* The flash address and size of the VSC7385 firmware image */
 121 #define CONFIG_VSC7385_IMAGE            0xFE7FE000
 122 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 123
 124 #endif
 125
 126 /*
 127  * DDR Setup
 128  */
 129 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 130 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 131 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 132 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   0x03000000
 133 #define CONFIG_SYS_83XX_DDR_USES_CS0
 134
 135 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
 136
 137 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 138 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 139
 140 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU   /* Never assert ODT to internal IOs */
 141
 142 /*
 143  * Manually set up DDR parameters
 144  */
 145 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 146 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 147 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 148                                         | CSCONFIG_ODT_WR_ONLY_CURRENT \
 149                                         | CSCONFIG_ROW_BIT_13 \
 150                                         | CSCONFIG_COL_BIT_10)
 151
 152 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 153 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 154                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 155                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 156                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 157                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 158                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 159                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 160                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 161                                 /* 0x00260802 */ /* DDR400 */
 162 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 163                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 164                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 165                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
 166                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 167                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 168                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 169                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 170                                 /* 0x3937d322 */
 171 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 172                                 | (5 << TIMING_CFG2_CPO_SHIFT) \
 173                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 174                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 175                                 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 176                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 177                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 178                                 /* 0x02984cc8 */
 179
 180 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 181                                 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 182                                 /* 0x06090100 */
 183
 184 #if defined(CONFIG_DDR_2T_TIMING)
 185 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 186                                         | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 187                                         | SDRAM_CFG_32_BE \
 188                                         | SDRAM_CFG_2T_EN)
 189                                         /* 0x43088000 */
 190 #else
 191 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 192                                         | SDRAM_CFG_SDRAM_TYPE_DDR2)
 193                                         /* 0x43000000 */
 194 #endif
 195 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 196 #define CONFIG_SYS_DDR_MODE             ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 197                                         | (0x0442 << SDRAM_MODE_SD_SHIFT))
 198                                         /* 0x04400442 */ /* DDR400 */
 199 #define CONFIG_SYS_DDR_MODE2            0x00000000
 200
 201 /*
 202  * Memory test
 203  */
 204 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 205 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 206 #define CONFIG_SYS_MEMTEST_END          0x0ef70010
 207
 208 /*
 209  * The reserved memory
 210  */
 211 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 212
 213 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 214 #define CONFIG_SYS_RAMBOOT
 215 #else
 216 #undef  CONFIG_SYS_RAMBOOT
 217 #endif
 218
 219 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 220 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 221
 222 /*
 223  * Initial RAM Base Address Setup
 224  */
 225 #define CONFIG_SYS_INIT_RAM_LOCK        1
 226 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 227 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 229                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 230
 231 /*
 232  * Local Bus Configuration & Clock Setup
 233  */
 234 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 235 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 236 #define CONFIG_SYS_LBC_LBCR             0x00000000
 237 #define CONFIG_FSL_ELBC         1
 238
 239 /*
 240  * FLASH on the Local Bus
 241  */
 242 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 243 #define CONFIG_SYS_FLASH_SIZE           8 /* max FLASH size is 32M */
 244
 245 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* display empty sectors */
 246
 247                                         /* Window base at flash base */
 248 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 249 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 250
 251 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 252                                 | BR_PS_16      /* 16 bit port */ \
 253                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 254                                 | BR_V)         /* valid */
 255 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 256                                 | OR_GPCM_XACS \
 257                                 | OR_GPCM_SCY_9 \
 258                                 | OR_GPCM_EHTR_SET \
 259                                 | OR_GPCM_EAD)
 260                                 /* 0xFF800191 */
 261
 262 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 263 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 264
 265 #undef  CONFIG_SYS_FLASH_CHECKSUM
 266 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 267 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 268
 269 /*
 270  * NAND Flash on the Local Bus
 271  */
 272 #define CONFIG_SYS_NAND_BASE    0xE0600000
 273 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_NAND_BASE \
 274                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 275                                 | BR_PS_8               /* 8 bit port */ \
 276                                 | BR_MS_FCM             /* MSEL = FCM */ \
 277                                 | BR_V)                 /* valid */
 278 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 279                                 | OR_FCM_CSCT \
 280                                 | OR_FCM_CST \
 281                                 | OR_FCM_CHT \
 282                                 | OR_FCM_SCY_1 \
 283                                 | OR_FCM_TRLX \
 284                                 | OR_FCM_EHTR)
 285 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 286 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 287
 288 /* Vitesse 7385 */
 289
 290 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
 291
 292 #ifdef CONFIG_VSC7385_ENET
 293
 294 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_VSC7385_BASE \
 295                                         | BR_PS_8 \
 296                                         | BR_MS_GPCM \
 297                                         | BR_V)
 298                                         /* 0xF0000801 */
 299 #define CONFIG_SYS_OR2_PRELIM           (OR_AM_128KB \
 300                                         | OR_GPCM_CSNT \
 301                                         | OR_GPCM_XACS \
 302                                         | OR_GPCM_SCY_15 \
 303                                         | OR_GPCM_SETA \
 304                                         | OR_GPCM_TRLX_SET \
 305                                         | OR_GPCM_EHTR_SET \
 306                                         | OR_GPCM_EAD)
 307                                         /* 0xfffe09ff */
 308
 309                                         /* Access Base */
 310 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_VSC7385_BASE
 311 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 312
 313 #endif
 314
 315 /*
 316  * Serial Port
 317  */
 318 #define CONFIG_SYS_NS16550_SERIAL
 319 #define CONFIG_SYS_NS16550_REG_SIZE     1
 320 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 321
 322 #define CONFIG_SYS_BAUDRATE_TABLE \
 323                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 324
 325 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 326 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 327
 328 /* SERDES */
 329 #define CONFIG_FSL_SERDES
 330 #define CONFIG_FSL_SERDES1      0xe3000
 331 #define CONFIG_FSL_SERDES2      0xe3100
 332
 333 /* I2C */
 334 #define CONFIG_SYS_I2C
 335 #define CONFIG_SYS_I2C_FSL
 336 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 337 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 338 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 339 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 340
 341 /*
 342  * Config on-board RTC
 343  */
 344 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 345 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 346
 347 /*
 348  * General PCI
 349  * Addresses are mapped 1-1.
 350  */
 351 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 352 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 353 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 354 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 355 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 356 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 357 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 358 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 359 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 360
 361 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 362 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 363 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 364
 365 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 366 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 367 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 368 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 369 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 370 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 371 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 372 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 373 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 374
 375 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 376 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 377 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 378 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 379 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 380 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 381 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 382 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 383 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 384
 385 #ifdef CONFIG_PCI
 386 #define CONFIG_PCI_INDIRECT_BRIDGE
 387
 388 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 389 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 390 #endif  /* CONFIG_PCI */
 391
 392 /*
 393  * TSEC
 394  */
 395 #ifdef CONFIG_TSEC_ENET
 396
 397 #define CONFIG_GMII                     /* MII PHY management */
 398
 399 #define CONFIG_TSEC1
 400
 401 #ifdef CONFIG_TSEC1
 402 #define CONFIG_HAS_ETH0
 403 #define CONFIG_TSEC1_NAME               "TSEC0"
 404 #define CONFIG_SYS_TSEC1_OFFSET         0x24000
 405 #define TSEC1_PHY_ADDR                  2
 406 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 407 #define TSEC1_PHYIDX                    0
 408 #endif
 409
 410 #ifdef CONFIG_TSEC2
 411 #define CONFIG_HAS_ETH1
 412 #define CONFIG_TSEC2_NAME               "TSEC1"
 413 #define CONFIG_SYS_TSEC2_OFFSET         0x25000
 414 #define TSEC2_PHY_ADDR                  0x1c
 415 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 416 #define TSEC2_PHYIDX                    0
 417 #endif
 418
 419 /* Options are: TSEC[0-1] */
 420 #define CONFIG_ETHPRIME                 "TSEC0"
 421
 422 #endif
 423
 424 /*
 425  * SATA
 426  */
 427 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 428 #define CONFIG_SATA1
 429 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 430 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 431 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 432 #define CONFIG_SATA2
 433 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 434 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 435 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 436
 437 #ifdef CONFIG_FSL_SATA
 438 #define CONFIG_LBA48
 439 #endif
 440
 441 /*
 442  * Environment
 443  */
 444 #ifndef CONFIG_SYS_RAMBOOT
 445         #define CONFIG_ENV_ADDR         \
 446                         (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
 447         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K (one sector) for env */
 448         #define CONFIG_ENV_SIZE         0x4000
 449 #else
 450         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-0x1000)
 451         #define CONFIG_ENV_SIZE         0x2000
 452 #endif
 453
 454 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 455 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 456
 457 /*
 458  * BOOTP options
 459  */
 460 #define CONFIG_BOOTP_BOOTFILESIZE
 461
 462 /*
 463  * Command line configuration.
 464  */
 465
 466 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 467
 468 #ifdef CONFIG_MMC
 469 #define CONFIG_FSL_ESDHC_PIN_MUX
 470 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 471 #endif
 472
 473 /*
 474  * Miscellaneous configurable options
 475  */
 476 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 477
 478 /*
 479  * For booting Linux, the board info and command line data
 480  * have to be in the first 256 MB of memory, since this is
 481  * the maximum mapped by the Linux kernel during initialization.
 482  */
 483 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 484 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 485
 486 /*
 487  * Core HID Setup
 488  */
 489 #define CONFIG_SYS_HID0_INIT    0x000000000
 490 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 491                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 492 #define CONFIG_SYS_HID2         HID2_HBE
 493
 494 /*
 495  * MMU Setup
 496  */
 497
 498 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 499
 500 /* DDR: cache cacheable */
 501 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 502 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 503
 504 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 505                                 | BATL_PP_RW \
 506                                 | BATL_MEMCOHERENCE)
 507 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 508                                 | BATU_BL_256M \
 509                                 | BATU_VS \
 510                                 | BATU_VP)
 511 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 512 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 513
 514 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 515                                 | BATL_PP_RW \
 516                                 | BATL_MEMCOHERENCE)
 517 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 518                                 | BATU_BL_256M \
 519                                 | BATU_VS \
 520                                 | BATU_VP)
 521 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 522 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 523
 524 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 525 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 526                                 | BATL_PP_RW \
 527                                 | BATL_CACHEINHIBIT \
 528                                 | BATL_GUARDEDSTORAGE)
 529 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 530                                 | BATU_BL_8M \
 531                                 | BATU_VS \
 532                                 | BATU_VP)
 533 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 534 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 535
 536 /* L2 Switch: cache-inhibit and guarded */
 537 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_VSC7385_BASE \
 538                                 | BATL_PP_RW \
 539                                 | BATL_CACHEINHIBIT \
 540                                 | BATL_GUARDEDSTORAGE)
 541 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_VSC7385_BASE \
 542                                 | BATU_BL_128K \
 543                                 | BATU_VS \
 544                                 | BATU_VP)
 545 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 546 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 547
 548 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 549 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 550                                 | BATL_PP_RW \
 551                                 | BATL_MEMCOHERENCE)
 552 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 553                                 | BATU_BL_32M \
 554                                 | BATU_VS \
 555                                 | BATU_VP)
 556 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 557                                 | BATL_PP_RW \
 558                                 | BATL_CACHEINHIBIT \
 559                                 | BATL_GUARDEDSTORAGE)
 560 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 561
 562 /* Stack in dcache: cacheable, no memory coherence */
 563 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 564 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 565                                 | BATU_BL_128K \
 566                                 | BATU_VS \
 567                                 | BATU_VP)
 568 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 569 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 570
 571 #ifdef CONFIG_PCI
 572 /* PCI MEM space: cacheable */
 573 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 574                                 | BATL_PP_RW \
 575                                 | BATL_MEMCOHERENCE)
 576 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 577                                 | BATU_BL_256M \
 578                                 | BATU_VS \
 579                                 | BATU_VP)
 580 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 581 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 582 /* PCI MMIO space: cache-inhibit and guarded */
 583 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 584                                 | BATL_PP_RW \
 585                                 | BATL_CACHEINHIBIT \
 586                                 | BATL_GUARDEDSTORAGE)
 587 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 588                                 | BATU_BL_256M \
 589                                 | BATU_VS \
 590                                 | BATU_VP)
 591 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 592 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 593 #else
 594 #define CONFIG_SYS_IBAT6L       (0)
 595 #define CONFIG_SYS_IBAT6U       (0)
 596 #define CONFIG_SYS_IBAT7L       (0)
 597 #define CONFIG_SYS_IBAT7U       (0)
 598 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 599 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 600 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 601 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 602 #endif
 603
 604 #if defined(CONFIG_CMD_KGDB)
 605 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 606 #endif
 607
 608 /*
 609  * Environment Configuration
 610  */
 611 #define CONFIG_ENV_OVERWRITE
 612
 613 #define CONFIG_HAS_FSL_DR_USB
 614 #define CONFIG_USB_EHCI_FSL
 615 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 616
 617 #define CONFIG_NETDEV           "eth1"
 618
 619 #define CONFIG_HOSTNAME         "mpc837x_rdb"
 620 #define CONFIG_ROOTPATH         "/nfsroot"
 621 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 622 #define CONFIG_BOOTFILE         "uImage"
 623                                 /* U-Boot image on TFTP server */
 624 #define CONFIG_UBOOTPATH        "u-boot.bin"
 625 #define CONFIG_FDTFILE          "mpc8379_rdb.dtb"
 626
 627                                 /* default location for tftp and bootm */
 628 #define CONFIG_LOADADDR         800000
 629
 630 #define CONFIG_EXTRA_ENV_SETTINGS \
 631         "netdev=" CONFIG_NETDEV "\0"                            \
 632         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 633         "tftpflash=tftp $loadaddr $uboot;"                              \
 634                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 635                         " +$filesize; " \
 636                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 637                         " +$filesize; " \
 638                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 639                         " $filesize; "  \
 640                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 641                         " +$filesize; " \
 642                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 643                         " $filesize\0"  \
 644         "fdtaddr=780000\0"                                              \
 645         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 646         "ramdiskaddr=1000000\0"                                         \
 647         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 648         "console=ttyS0\0"                                               \
 649         "setbootargs=setenv bootargs "                                  \
 650                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 651         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 652                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 653                                                         "$netdev:off "  \
 654                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 655
 656 #define CONFIG_NFSBOOTCOMMAND                                           \
 657         "setenv rootdev /dev/nfs;"                                      \
 658         "run setbootargs;"                                              \
 659         "run setipargs;"                                                \
 660         "tftp $loadaddr $bootfile;"                                     \
 661         "tftp $fdtaddr $fdtfile;"                                       \
 662         "bootm $loadaddr - $fdtaddr"
 663
 664 #define CONFIG_RAMBOOTCOMMAND                                           \
 665         "setenv rootdev /dev/ram;"                                      \
 666         "run setbootargs;"                                              \
 667         "tftp $ramdiskaddr $ramdiskfile;"                               \
 668         "tftp $loadaddr $bootfile;"                                     \
 669         "tftp $fdtaddr $fdtfile;"                                       \
 670         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 671
 672 #endif  /* __CONFIG_H */