1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_HWCONFIG
21 #define CONFIG_VSC7385_ENET
23 /* System performance - define the value i.e. CONFIG_SYS_XXX
26 /* System Clock Configuration Register */
27 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
28 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
29 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
34 #define CONFIG_SYS_SICRH 0x08200000
35 #define CONFIG_SYS_SICRL 0x00000000
38 * Output Buffer Impedance
40 #define CONFIG_SYS_OBIR 0x30100000
43 * Device configurations
48 #ifdef CONFIG_VSC7385_ENET
52 /* The flash address and size of the VSC7385 firmware image */
53 #define CONFIG_VSC7385_IMAGE 0xFE7FE000
54 #define CONFIG_VSC7385_IMAGE_SIZE 8192
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
62 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
63 #define CONFIG_SYS_83XX_DDR_USES_CS0
65 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
67 #undef CONFIG_DDR_ECC /* support DDR ECC function */
68 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
70 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
73 * Manually set up DDR parameters
75 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
76 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
77 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
78 | CSCONFIG_ODT_WR_ONLY_CURRENT \
79 | CSCONFIG_ROW_BIT_13 \
80 | CSCONFIG_COL_BIT_10)
82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
83 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
84 | (0 << TIMING_CFG0_WRT_SHIFT) \
85 | (0 << TIMING_CFG0_RRT_SHIFT) \
86 | (0 << TIMING_CFG0_WWT_SHIFT) \
87 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
88 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
89 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
90 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
91 /* 0x00260802 */ /* DDR400 */
92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
93 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
94 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
95 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
96 | (13 << TIMING_CFG1_REFREC_SHIFT) \
97 | (3 << TIMING_CFG1_WRREC_SHIFT) \
98 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
99 | (2 << TIMING_CFG1_WRTORD_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
102 | (5 << TIMING_CFG2_CPO_SHIFT) \
103 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
104 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
105 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
106 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
107 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
110 #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
111 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
114 #if defined(CONFIG_DDR_2T_TIMING)
115 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
116 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
121 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
122 | SDRAM_CFG_SDRAM_TYPE_DDR2)
125 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
126 #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
127 | (0x0442 << SDRAM_MODE_SD_SHIFT))
128 /* 0x04400442 */ /* DDR400 */
129 #define CONFIG_SYS_DDR_MODE2 0x00000000
134 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
135 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
136 #define CONFIG_SYS_MEMTEST_END 0x0ef70010
139 * The reserved memory
141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
143 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
144 #define CONFIG_SYS_RAMBOOT
146 #undef CONFIG_SYS_RAMBOOT
149 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
150 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
153 * Initial RAM Base Address Setup
155 #define CONFIG_SYS_INIT_RAM_LOCK 1
156 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
157 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
158 #define CONFIG_SYS_GBL_DATA_OFFSET \
159 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
161 #define CONFIG_FSL_ELBC 1
164 * FLASH on the Local Bus
166 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
167 #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
169 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
172 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
173 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
175 #undef CONFIG_SYS_FLASH_CHECKSUM
176 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
177 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
180 * NAND Flash on the Local Bus
182 #define CONFIG_SYS_NAND_BASE 0xE0600000
187 #define CONFIG_SYS_VSC7385_BASE 0xF0000000
192 #define CONFIG_SYS_NS16550_SERIAL
193 #define CONFIG_SYS_NS16550_REG_SIZE 1
194 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
196 #define CONFIG_SYS_BAUDRATE_TABLE \
197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
199 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
200 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
203 #define CONFIG_FSL_SERDES
204 #define CONFIG_FSL_SERDES1 0xe3000
205 #define CONFIG_FSL_SERDES2 0xe3100
208 #define CONFIG_SYS_I2C
209 #define CONFIG_SYS_I2C_FSL
210 #define CONFIG_SYS_FSL_I2C_SPEED 400000
211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
213 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
216 * Config on-board RTC
218 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
219 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
223 * Addresses are mapped 1-1.
225 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
226 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
227 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
228 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
229 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
230 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
231 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
232 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
233 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
235 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
236 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
237 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
239 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
240 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
241 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
242 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
244 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
245 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
246 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
247 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
249 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
250 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
251 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
252 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
253 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
254 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
255 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
256 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
257 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
260 #define CONFIG_PCI_INDIRECT_BRIDGE
262 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
263 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
264 #endif /* CONFIG_PCI */
269 #ifdef CONFIG_TSEC_ENET
271 #define CONFIG_GMII /* MII PHY management */
276 #define CONFIG_HAS_ETH0
277 #define CONFIG_TSEC1_NAME "TSEC0"
278 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
279 #define TSEC1_PHY_ADDR 2
280 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
281 #define TSEC1_PHYIDX 0
285 #define CONFIG_HAS_ETH1
286 #define CONFIG_TSEC2_NAME "TSEC1"
287 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
288 #define TSEC2_PHY_ADDR 0x1c
289 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
290 #define TSEC2_PHYIDX 0
293 /* Options are: TSEC[0-1] */
294 #define CONFIG_ETHPRIME "TSEC0"
301 #define CONFIG_SYS_SATA_MAX_DEVICE 2
303 #define CONFIG_SYS_SATA1_OFFSET 0x18000
304 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
305 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
307 #define CONFIG_SYS_SATA2_OFFSET 0x19000
308 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
309 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
311 #ifdef CONFIG_FSL_SATA
318 #ifndef CONFIG_SYS_RAMBOOT
319 #define CONFIG_ENV_ADDR \
320 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
321 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
322 #define CONFIG_ENV_SIZE 0x4000
324 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
325 #define CONFIG_ENV_SIZE 0x2000
328 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
329 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
334 #define CONFIG_BOOTP_BOOTFILESIZE
337 * Command line configuration.
340 #undef CONFIG_WATCHDOG /* watchdog disabled */
343 #define CONFIG_FSL_ESDHC_PIN_MUX
344 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
348 * Miscellaneous configurable options
350 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
353 * For booting Linux, the board info and command line data
354 * have to be in the first 256 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
357 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
358 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
360 #if defined(CONFIG_CMD_KGDB)
361 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
365 * Environment Configuration
367 #define CONFIG_ENV_OVERWRITE
369 #define CONFIG_HAS_FSL_DR_USB
370 #define CONFIG_USB_EHCI_FSL
371 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
373 #define CONFIG_NETDEV "eth1"
375 #define CONFIG_HOSTNAME "mpc837x_rdb"
376 #define CONFIG_ROOTPATH "/nfsroot"
377 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
378 #define CONFIG_BOOTFILE "uImage"
379 /* U-Boot image on TFTP server */
380 #define CONFIG_UBOOTPATH "u-boot.bin"
381 #define CONFIG_FDTFILE "mpc8379_rdb.dtb"
383 /* default location for tftp and bootm */
384 #define CONFIG_LOADADDR 800000
386 #define CONFIG_EXTRA_ENV_SETTINGS \
387 "netdev=" CONFIG_NETDEV "\0" \
388 "uboot=" CONFIG_UBOOTPATH "\0" \
389 "tftpflash=tftp $loadaddr $uboot;" \
390 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
392 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
394 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
396 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
398 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
401 "fdtfile=" CONFIG_FDTFILE "\0" \
402 "ramdiskaddr=1000000\0" \
403 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
405 "setbootargs=setenv bootargs " \
406 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
407 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
408 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
410 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
412 #define CONFIG_NFSBOOTCOMMAND \
413 "setenv rootdev /dev/nfs;" \
416 "tftp $loadaddr $bootfile;" \
417 "tftp $fdtaddr $fdtfile;" \
418 "bootm $loadaddr - $fdtaddr"
420 #define CONFIG_RAMBOOTCOMMAND \
421 "setenv rootdev /dev/ram;" \
423 "tftp $ramdiskaddr $ramdiskfile;" \
424 "tftp $loadaddr $bootfile;" \
425 "tftp $fdtaddr $fdtfile;" \
426 "bootm $loadaddr $ramdiskaddr $fdtaddr"
428 #endif /* __CONFIG_H */