include/configs/MPC837XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Dave Liu <daveliu@freescale.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * High Level Configuration Options
  12  */
  13 #define CONFIG_E300             1 /* E300 family */
  14
  15 /*
  16  * Hardware Reset Configuration Word
  17  * if CLKIN is 66MHz, then
  18  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  19  */
  20 #define CONFIG_SYS_HRCW_LOW (\
  21         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  22         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  23         HRCWL_SVCOD_DIV_2 |\
  24         HRCWL_CSB_TO_CLKIN_6X1 |\
  25         HRCWL_CORE_TO_CSB_1_5X1)
  26
  27 #ifdef CONFIG_PCISLAVE
  28 #define CONFIG_SYS_HRCW_HIGH (\
  29         HRCWH_PCI_AGENT |\
  30         HRCWH_PCI1_ARBITER_DISABLE |\
  31         HRCWH_CORE_ENABLE |\
  32         HRCWH_FROM_0XFFF00100 |\
  33         HRCWH_BOOTSEQ_DISABLE |\
  34         HRCWH_SW_WATCHDOG_DISABLE |\
  35         HRCWH_ROM_LOC_LOCAL_16BIT |\
  36         HRCWH_RL_EXT_LEGACY |\
  37         HRCWH_TSEC1M_IN_RGMII |\
  38         HRCWH_TSEC2M_IN_RGMII |\
  39         HRCWH_BIG_ENDIAN |\
  40         HRCWH_LDP_CLEAR)
  41 #else
  42 #define CONFIG_SYS_HRCW_HIGH (\
  43         HRCWH_PCI_HOST |\
  44         HRCWH_PCI1_ARBITER_ENABLE |\
  45         HRCWH_CORE_ENABLE |\
  46         HRCWH_FROM_0X00000100 |\
  47         HRCWH_BOOTSEQ_DISABLE |\
  48         HRCWH_SW_WATCHDOG_DISABLE |\
  49         HRCWH_ROM_LOC_LOCAL_16BIT |\
  50         HRCWH_RL_EXT_LEGACY |\
  51         HRCWH_TSEC1M_IN_RGMII |\
  52         HRCWH_TSEC2M_IN_RGMII |\
  53         HRCWH_BIG_ENDIAN |\
  54         HRCWH_LDP_CLEAR)
  55 #endif
  56
  57 /* Arbiter Configuration Register */
  58 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  59 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
  60
  61 /* System Priority Control Register */
  62 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
  63
  64 /*
  65  * IP blocks clock configuration
  66  */
  67 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  68 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  69 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
  70
  71 /*
  72  * System IO Config
  73  */
  74 #define CONFIG_SYS_SICRH                0x00000000
  75 #define CONFIG_SYS_SICRL                0x00000000
  76
  77 /*
  78  * Output Buffer Impedance
  79  */
  80 #define CONFIG_SYS_OBIR         0x31100000
  81
  82 #define CONFIG_HWCONFIG
  83
  84 /*
  85  * IMMR new address
  86  */
  87 #define CONFIG_SYS_IMMR         0xE0000000
  88
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  96 #define CONFIG_SYS_83XX_DDR_USES_CS0
  97 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
  98                                         | DDRCDR_ODT \
  99                                         | DDRCDR_Q_DRN)
 100                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
 101
 102 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 103 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 104
 105 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 106 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 107
 108 #if defined(CONFIG_SPD_EEPROM)
 109 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 110 #else
 111 /*
 112  * Manually set up DDR parameters
 113  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 114  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 115  */
 116 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
 118 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 119                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
 120                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
 121                         | CSCONFIG_ROW_BIT_14 \
 122                         | CSCONFIG_COL_BIT_10)
 123                         /* 0x80010202 */
 124 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 125 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 126                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 127                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 128                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 129                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 130                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 131                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 132                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 133                                 /* 0x00620802 */
 134 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 135                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 136                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 137                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 138                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 139                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 140                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 141                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 142                                 /* 0x3935d322 */
 143 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 144                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
 145                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 146                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 147                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 148                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 149                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 150                                 /* 0x131088c8 */
 151 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
 152                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 153                                 /* 0x03E00100 */
 154 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 155 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 156 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 157                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
 158                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 159 #define CONFIG_SYS_DDR_MODE2    0x00000000
 160 #endif
 161
 162 /*
 163  * Memory test
 164  */
 165 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 166 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 167 #define CONFIG_SYS_MEMTEST_END          0x00140000
 168
 169 /*
 170  * The reserved memory
 171  */
 172 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 173
 174 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 175 #define CONFIG_SYS_RAMBOOT
 176 #else
 177 #undef CONFIG_SYS_RAMBOOT
 178 #endif
 179
 180 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 181 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 182 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 183
 184 /*
 185  * Initial RAM Base Address Setup
 186  */
 187 #define CONFIG_SYS_INIT_RAM_LOCK        1
 188 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 189 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 190 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 191                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 192
 193 /*
 194  * Local Bus Configuration & Clock Setup
 195  */
 196 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 197 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 198 #define CONFIG_SYS_LBC_LBCR             0x00000000
 199 #define CONFIG_FSL_ELBC         1
 200
 201 /*
 202  * FLASH on the Local Bus
 203  */
 204 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 205 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 206
 207                                         /* Window base at flash base */
 208 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 209 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 210
 211 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 212                                 | BR_PS_16      /* 16 bit port */ \
 213                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 214                                 | BR_V)         /* valid */
 215 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 216                                 | OR_UPM_XAM \
 217                                 | OR_GPCM_CSNT \
 218                                 | OR_GPCM_ACS_DIV2 \
 219                                 | OR_GPCM_XACS \
 220                                 | OR_GPCM_SCY_15 \
 221                                 | OR_GPCM_TRLX_SET \
 222                                 | OR_GPCM_EHTR_SET \
 223                                 | OR_GPCM_EAD)
 224                                 /* 0xFE000FF7 */
 225
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 227 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 228
 229 #undef CONFIG_SYS_FLASH_CHECKSUM
 230 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 231 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 232
 233 /*
 234  * BCSR on the Local Bus
 235  */
 236 #define CONFIG_SYS_BCSR         0xF8000000
 237                                         /* Access window base at BCSR base */
 238 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 239 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 240
 241 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
 242                                 | BR_PS_8 \
 243                                 | BR_MS_GPCM \
 244                                 | BR_V)
 245                                 /* 0xF8000801 */
 246 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 247                                 | OR_GPCM_XAM \
 248                                 | OR_GPCM_CSNT \
 249                                 | OR_GPCM_XACS \
 250                                 | OR_GPCM_SCY_15 \
 251                                 | OR_GPCM_TRLX_SET \
 252                                 | OR_GPCM_EHTR_SET \
 253                                 | OR_GPCM_EAD)
 254                                 /* 0xFFFFE9F7 */
 255
 256 /*
 257  * NAND Flash on the Local Bus
 258  */
 259 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 260 #define CONFIG_NAND_FSL_ELBC    1
 261
 262 #define CONFIG_SYS_NAND_BASE    0xE0600000
 263 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE \
 264                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 265                                 | BR_PS_8               /* 8 bit port */ \
 266                                 | BR_MS_FCM             /* MSEL = FCM */ \
 267                                 | BR_V)                 /* valid */
 268 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32KB \
 269                                 | OR_FCM_BCTLD \
 270                                 | OR_FCM_CST \
 271                                 | OR_FCM_CHT \
 272                                 | OR_FCM_SCY_1 \
 273                                 | OR_FCM_RST \
 274                                 | OR_FCM_TRLX \
 275                                 | OR_FCM_EHTR)
 276                                 /* 0xFFFF919E */
 277
 278 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
 279 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 280
 281 /*
 282  * Serial Port
 283  */
 284 #define CONFIG_SYS_NS16550_SERIAL
 285 #define CONFIG_SYS_NS16550_REG_SIZE     1
 286 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 287
 288 #define CONFIG_SYS_BAUDRATE_TABLE  \
 289                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 290
 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 293
 294 /* I2C */
 295 #define CONFIG_SYS_I2C
 296 #define CONFIG_SYS_I2C_FSL
 297 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 298 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 299 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 300 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 301
 302 /*
 303  * Config on-board RTC
 304  */
 305 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 306 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 307
 308 /*
 309  * General PCI
 310  * Addresses are mapped 1-1.
 311  */
 312 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 313 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 314 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 315 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 316 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 317 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 318 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 319 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 320 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 321
 322 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 323 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 324 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 325
 326 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 327 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 328 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 329 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 330 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 331 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 332 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 333 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 334 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 335
 336 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 337 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 338 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 339 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 340 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 341 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 342 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 343 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 344 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 345
 346 #ifdef CONFIG_PCI
 347 #define CONFIG_PCI_INDIRECT_BRIDGE
 348 #ifndef __ASSEMBLY__
 349 extern int board_pci_host_broken(void);
 350 #endif
 351 #define CONFIG_PCIE
 352 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 353
 354 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 355 #define CONFIG_USB_EHCI_FSL
 356 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 357
 358 #undef CONFIG_EEPRO100
 359 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 360 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 361 #endif /* CONFIG_PCI */
 362
 363 /*
 364  * TSEC
 365  */
 366 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 367 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 368 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 369 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 370
 371 /*
 372  * TSEC ethernet configuration
 373  */
 374 #define CONFIG_TSEC1            1
 375 #define CONFIG_TSEC1_NAME       "eTSEC0"
 376 #define CONFIG_TSEC2            1
 377 #define CONFIG_TSEC2_NAME       "eTSEC1"
 378 #define TSEC1_PHY_ADDR          2
 379 #define TSEC2_PHY_ADDR          3
 380 #define TSEC1_PHY_ADDR_SGMII    8
 381 #define TSEC2_PHY_ADDR_SGMII    4
 382 #define TSEC1_PHYIDX            0
 383 #define TSEC2_PHYIDX            0
 384 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 385 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 386
 387 /* Options are: TSEC[0-1] */
 388 #define CONFIG_ETHPRIME         "eTSEC1"
 389
 390 /* SERDES */
 391 #define CONFIG_FSL_SERDES
 392 #define CONFIG_FSL_SERDES1      0xe3000
 393 #define CONFIG_FSL_SERDES2      0xe3100
 394
 395 /*
 396  * SATA
 397  */
 398 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 399 #define CONFIG_SATA1
 400 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 401 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 402 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 403 #define CONFIG_SATA2
 404 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 405 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 406 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 407
 408 #ifdef CONFIG_FSL_SATA
 409 #define CONFIG_LBA48
 410 #endif
 411
 412 /*
 413  * Environment
 414  */
 415 #ifndef CONFIG_SYS_RAMBOOT
 416         #define CONFIG_ENV_ADDR         \
 417                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 418         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 419         #define CONFIG_ENV_SIZE         0x2000
 420 #else
 421         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 422         #define CONFIG_ENV_SIZE         0x2000
 423 #endif
 424
 425 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 426 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 427
 428 /*
 429  * BOOTP options
 430  */
 431 #define CONFIG_BOOTP_BOOTFILESIZE
 432
 433 /*
 434  * Command line configuration.
 435  */
 436
 437 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 438
 439 #ifdef CONFIG_MMC
 440 #define CONFIG_FSL_ESDHC_PIN_MUX
 441 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 442 #endif
 443
 444 /*
 445  * Miscellaneous configurable options
 446  */
 447 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 448
 449 /*
 450  * For booting Linux, the board info and command line data
 451  * have to be in the first 256 MB of memory, since this is
 452  * the maximum mapped by the Linux kernel during initialization.
 453  */
 454 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 455 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 456
 457 /*
 458  * Core HID Setup
 459  */
 460 #define CONFIG_SYS_HID0_INIT    0x000000000
 461 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 462                                  HID0_ENABLE_INSTRUCTION_CACHE)
 463 #define CONFIG_SYS_HID2         HID2_HBE
 464
 465 /*
 466  * MMU Setup
 467  */
 468 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 469
 470 /* DDR: cache cacheable */
 471 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 472 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 473
 474 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 475                                 | BATL_PP_RW \
 476                                 | BATL_MEMCOHERENCE)
 477 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 478                                 | BATU_BL_256M \
 479                                 | BATU_VS \
 480                                 | BATU_VP)
 481 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 482 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 483
 484 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 485                                 | BATL_PP_RW \
 486                                 | BATL_MEMCOHERENCE)
 487 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 488                                 | BATU_BL_256M \
 489                                 | BATU_VS \
 490                                 | BATU_VP)
 491 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 492 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 493
 494 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 495 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 496                                 | BATL_PP_RW \
 497                                 | BATL_CACHEINHIBIT \
 498                                 | BATL_GUARDEDSTORAGE)
 499 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 500                                 | BATU_BL_8M \
 501                                 | BATU_VS \
 502                                 | BATU_VP)
 503 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 504 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 505
 506 /* BCSR: cache-inhibit and guarded */
 507 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR \
 508                                 | BATL_PP_RW \
 509                                 | BATL_CACHEINHIBIT \
 510                                 | BATL_GUARDEDSTORAGE)
 511 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR \
 512                                 | BATU_BL_128K \
 513                                 | BATU_VS \
 514                                 | BATU_VP)
 515 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 516 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 517
 518 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 519 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 520                                 | BATL_PP_RW \
 521                                 | BATL_MEMCOHERENCE)
 522 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 523                                 | BATU_BL_32M \
 524                                 | BATU_VS \
 525                                 | BATU_VP)
 526 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 527                                 | BATL_PP_RW \
 528                                 | BATL_CACHEINHIBIT \
 529                                 | BATL_GUARDEDSTORAGE)
 530 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 531
 532 /* Stack in dcache: cacheable, no memory coherence */
 533 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 534 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 535                                 | BATU_BL_128K \
 536                                 | BATU_VS \
 537                                 | BATU_VP)
 538 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 539 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 540
 541 #ifdef CONFIG_PCI
 542 /* PCI MEM space: cacheable */
 543 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 544                                 | BATL_PP_RW \
 545                                 | BATL_MEMCOHERENCE)
 546 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 547                                 | BATU_BL_256M \
 548                                 | BATU_VS \
 549                                 | BATU_VP)
 550 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 551 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 552 /* PCI MMIO space: cache-inhibit and guarded */
 553 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 554                                 | BATL_PP_RW \
 555                                 | BATL_CACHEINHIBIT \
 556                                 | BATL_GUARDEDSTORAGE)
 557 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 558                                 | BATU_BL_256M \
 559                                 | BATU_VS \
 560                                 | BATU_VP)
 561 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 562 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 563 #else
 564 #define CONFIG_SYS_IBAT6L       (0)
 565 #define CONFIG_SYS_IBAT6U       (0)
 566 #define CONFIG_SYS_IBAT7L       (0)
 567 #define CONFIG_SYS_IBAT7U       (0)
 568 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 569 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 570 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 571 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 572 #endif
 573
 574 #if defined(CONFIG_CMD_KGDB)
 575 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 576 #endif
 577
 578 /*
 579  * Environment Configuration
 580  */
 581
 582 #define CONFIG_ENV_OVERWRITE
 583
 584 #if defined(CONFIG_TSEC_ENET)
 585 #define CONFIG_HAS_ETH0
 586 #define CONFIG_HAS_ETH1
 587 #endif
 588
 589 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 590
 591 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 592         "netdev=eth0\0"                                                 \
 593         "consoledev=ttyS0\0"                                            \
 594         "ramdiskaddr=1000000\0"                                         \
 595         "ramdiskfile=ramfs.83xx\0"                                      \
 596         "fdtaddr=780000\0"                                              \
 597         "fdtfile=mpc8379_mds.dtb\0"                                     \
 598         ""
 599
 600 #define CONFIG_NFSBOOTCOMMAND                                           \
 601         "setenv bootargs root=/dev/nfs rw "                             \
 602                 "nfsroot=$serverip:$rootpath "                          \
 603                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 604                                                         "$netdev:off "  \
 605                 "console=$consoledev,$baudrate $othbootargs;"           \
 606         "tftp $loadaddr $bootfile;"                                     \
 607         "tftp $fdtaddr $fdtfile;"                                       \
 608         "bootm $loadaddr - $fdtaddr"
 609
 610 #define CONFIG_RAMBOOTCOMMAND                                           \
 611         "setenv bootargs root=/dev/ram rw "                             \
 612                 "console=$consoledev,$baudrate $othbootargs;"           \
 613         "tftp $ramdiskaddr $ramdiskfile;"                               \
 614         "tftp $loadaddr $bootfile;"                                     \
 615         "tftp $fdtaddr $fdtfile;"                                       \
 616         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 617
 618 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 619
 620 #endif  /* __CONFIG_H */