1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
11 * High Level Configuration Options
13 #define CONFIG_E300 1 /* E300 family */
15 /* Arbiter Configuration Register */
16 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
17 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
19 /* System Priority Control Register */
20 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
23 * IP blocks clock configuration
25 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
26 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
27 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
32 #define CONFIG_SYS_SICRH 0x00000000
33 #define CONFIG_SYS_SICRL 0x00000000
36 * Output Buffer Impedance
38 #define CONFIG_SYS_OBIR 0x31100000
40 #define CONFIG_HWCONFIG
45 #define CONFIG_SYS_IMMR 0xE0000000
50 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
52 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
54 #define CONFIG_SYS_83XX_DDR_USES_CS0
55 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
58 /* 0x80080001 */ /* ODT 150ohm on SoC */
60 #undef CONFIG_DDR_ECC /* support DDR ECC function */
61 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
64 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
66 #if defined(CONFIG_SPD_EEPROM)
67 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
70 * Manually set up DDR parameters
71 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
72 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
74 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
75 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
76 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
77 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
78 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
79 | CSCONFIG_ROW_BIT_14 \
80 | CSCONFIG_COL_BIT_10)
82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
83 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
84 | (0 << TIMING_CFG0_WRT_SHIFT) \
85 | (0 << TIMING_CFG0_RRT_SHIFT) \
86 | (0 << TIMING_CFG0_WWT_SHIFT) \
87 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
88 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
89 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
90 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
93 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
94 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
95 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
96 | (13 << TIMING_CFG1_REFREC_SHIFT) \
97 | (3 << TIMING_CFG1_WRREC_SHIFT) \
98 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
99 | (2 << TIMING_CFG1_WRTORD_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
102 | (6 << TIMING_CFG2_CPO_SHIFT) \
103 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
104 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
105 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
106 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
107 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
109 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
110 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
112 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
113 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
114 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
115 | (0x1432 << SDRAM_MODE_SD_SHIFT))
116 /* ODT 150ohm CL=3, AL=1 on SDRAM */
117 #define CONFIG_SYS_DDR_MODE2 0x00000000
123 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
124 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
125 #define CONFIG_SYS_MEMTEST_END 0x00140000
128 * The reserved memory
130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
133 #define CONFIG_SYS_RAMBOOT
135 #undef CONFIG_SYS_RAMBOOT
138 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
139 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
140 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
143 * Initial RAM Base Address Setup
145 #define CONFIG_SYS_INIT_RAM_LOCK 1
146 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
148 #define CONFIG_SYS_GBL_DATA_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 * Local Bus Configuration & Clock Setup
154 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
155 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
156 #define CONFIG_SYS_LBC_LBCR 0x00000000
157 #define CONFIG_FSL_ELBC 1
160 * FLASH on the Local Bus
162 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
163 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
165 /* Window base at flash base */
166 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
167 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
169 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
170 | BR_PS_16 /* 16 bit port */ \
171 | BR_MS_GPCM /* MSEL = GPCM */ \
173 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
187 #undef CONFIG_SYS_FLASH_CHECKSUM
188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
192 * BCSR on the Local Bus
194 #define CONFIG_SYS_BCSR 0xF8000000
195 /* Access window base at BCSR base */
196 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
197 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
199 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
204 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
215 * NAND Flash on the Local Bus
217 #define CONFIG_SYS_MAX_NAND_DEVICE 1
218 #define CONFIG_NAND_FSL_ELBC 1
220 #define CONFIG_SYS_NAND_BASE 0xE0600000
221 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
222 | BR_DECC_CHK_GEN /* Use HW ECC */ \
223 | BR_PS_8 /* 8 bit port */ \
224 | BR_MS_FCM /* MSEL = FCM */ \
226 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
236 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
237 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
242 #define CONFIG_SYS_NS16550_SERIAL
243 #define CONFIG_SYS_NS16550_REG_SIZE 1
244 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
246 #define CONFIG_SYS_BAUDRATE_TABLE \
247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
253 #define CONFIG_SYS_I2C
254 #define CONFIG_SYS_I2C_FSL
255 #define CONFIG_SYS_FSL_I2C_SPEED 400000
256 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
257 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
258 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
261 * Config on-board RTC
263 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
264 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
268 * Addresses are mapped 1-1.
270 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
271 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
272 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
273 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
274 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
275 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
276 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
277 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
278 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
280 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
281 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
282 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
284 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
285 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
286 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
287 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
289 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
290 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
292 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
294 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
295 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
296 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
297 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
298 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
299 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
300 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
301 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
302 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
305 #define CONFIG_PCI_INDIRECT_BRIDGE
307 extern int board_pci_host_broken(void);
310 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
312 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
313 #define CONFIG_USB_EHCI_FSL
314 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
316 #undef CONFIG_EEPRO100
317 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
318 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
319 #endif /* CONFIG_PCI */
324 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
325 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
326 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
327 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
330 * TSEC ethernet configuration
332 #define CONFIG_TSEC1 1
333 #define CONFIG_TSEC1_NAME "eTSEC0"
334 #define CONFIG_TSEC2 1
335 #define CONFIG_TSEC2_NAME "eTSEC1"
336 #define TSEC1_PHY_ADDR 2
337 #define TSEC2_PHY_ADDR 3
338 #define TSEC1_PHY_ADDR_SGMII 8
339 #define TSEC2_PHY_ADDR_SGMII 4
340 #define TSEC1_PHYIDX 0
341 #define TSEC2_PHYIDX 0
342 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
343 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
345 /* Options are: TSEC[0-1] */
346 #define CONFIG_ETHPRIME "eTSEC1"
349 #define CONFIG_FSL_SERDES
350 #define CONFIG_FSL_SERDES1 0xe3000
351 #define CONFIG_FSL_SERDES2 0xe3100
356 #define CONFIG_SYS_SATA_MAX_DEVICE 2
358 #define CONFIG_SYS_SATA1_OFFSET 0x18000
359 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
360 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
362 #define CONFIG_SYS_SATA2_OFFSET 0x19000
363 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
364 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
366 #ifdef CONFIG_FSL_SATA
373 #ifndef CONFIG_SYS_RAMBOOT
374 #define CONFIG_ENV_ADDR \
375 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
376 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
377 #define CONFIG_ENV_SIZE 0x2000
379 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
380 #define CONFIG_ENV_SIZE 0x2000
383 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
384 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
389 #define CONFIG_BOOTP_BOOTFILESIZE
392 * Command line configuration.
395 #undef CONFIG_WATCHDOG /* watchdog disabled */
398 #define CONFIG_FSL_ESDHC_PIN_MUX
399 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
403 * Miscellaneous configurable options
405 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
408 * For booting Linux, the board info and command line data
409 * have to be in the first 256 MB of memory, since this is
410 * the maximum mapped by the Linux kernel during initialization.
412 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
413 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
418 #define CONFIG_SYS_HID0_INIT 0x000000000
419 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
420 HID0_ENABLE_INSTRUCTION_CACHE)
421 #define CONFIG_SYS_HID2 HID2_HBE
427 /* DDR: cache cacheable */
428 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
429 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
431 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
434 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
438 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
439 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
441 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
444 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
448 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
449 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
451 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
452 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
454 | BATL_CACHEINHIBIT \
455 | BATL_GUARDEDSTORAGE)
456 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
460 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
461 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
463 /* BCSR: cache-inhibit and guarded */
464 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
466 | BATL_CACHEINHIBIT \
467 | BATL_GUARDEDSTORAGE)
468 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
472 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
473 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
475 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
476 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
479 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
483 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
485 | BATL_CACHEINHIBIT \
486 | BATL_GUARDEDSTORAGE)
487 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
489 /* Stack in dcache: cacheable, no memory coherence */
490 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
491 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
495 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
496 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
499 /* PCI MEM space: cacheable */
500 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
503 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
507 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
508 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
509 /* PCI MMIO space: cache-inhibit and guarded */
510 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
512 | BATL_CACHEINHIBIT \
513 | BATL_GUARDEDSTORAGE)
514 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
518 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
519 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
521 #define CONFIG_SYS_IBAT6L (0)
522 #define CONFIG_SYS_IBAT6U (0)
523 #define CONFIG_SYS_IBAT7L (0)
524 #define CONFIG_SYS_IBAT7U (0)
525 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
526 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
527 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
528 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
531 #if defined(CONFIG_CMD_KGDB)
532 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
536 * Environment Configuration
539 #define CONFIG_ENV_OVERWRITE
541 #if defined(CONFIG_TSEC_ENET)
542 #define CONFIG_HAS_ETH0
543 #define CONFIG_HAS_ETH1
546 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
548 #define CONFIG_EXTRA_ENV_SETTINGS \
550 "consoledev=ttyS0\0" \
551 "ramdiskaddr=1000000\0" \
552 "ramdiskfile=ramfs.83xx\0" \
554 "fdtfile=mpc8379_mds.dtb\0" \
557 #define CONFIG_NFSBOOTCOMMAND \
558 "setenv bootargs root=/dev/nfs rw " \
559 "nfsroot=$serverip:$rootpath " \
560 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
562 "console=$consoledev,$baudrate $othbootargs;" \
563 "tftp $loadaddr $bootfile;" \
564 "tftp $fdtaddr $fdtfile;" \
565 "bootm $loadaddr - $fdtaddr"
567 #define CONFIG_RAMBOOTCOMMAND \
568 "setenv bootargs root=/dev/ram rw " \
569 "console=$consoledev,$baudrate $othbootargs;" \
570 "tftp $ramdiskaddr $ramdiskfile;" \
571 "tftp $loadaddr $bootfile;" \
572 "tftp $fdtaddr $fdtfile;" \
573 "bootm $loadaddr $ramdiskaddr $fdtaddr"
575 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
577 #endif /* __CONFIG_H */