include/configs/MPC837XEMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   4  * Dave Liu <daveliu@freescale.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * High Level Configuration Options
  12  */
  13 #define CONFIG_E300             1 /* E300 family */
  14
  15 /*
  16  * System Clock Setup
  17  */
  18 #ifdef CONFIG_PCISLAVE
  19 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  20 #else
  21 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  22 #endif
  23
  24 #ifndef CONFIG_SYS_CLK_FREQ
  25 #define CONFIG_SYS_CLK_FREQ     66000000
  26 #endif
  27
  28 /*
  29  * Hardware Reset Configuration Word
  30  * if CLKIN is 66MHz, then
  31  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  32  */
  33 #define CONFIG_SYS_HRCW_LOW (\
  34         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  35         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  36         HRCWL_SVCOD_DIV_2 |\
  37         HRCWL_CSB_TO_CLKIN_6X1 |\
  38         HRCWL_CORE_TO_CSB_1_5X1)
  39
  40 #ifdef CONFIG_PCISLAVE
  41 #define CONFIG_SYS_HRCW_HIGH (\
  42         HRCWH_PCI_AGENT |\
  43         HRCWH_PCI1_ARBITER_DISABLE |\
  44         HRCWH_CORE_ENABLE |\
  45         HRCWH_FROM_0XFFF00100 |\
  46         HRCWH_BOOTSEQ_DISABLE |\
  47         HRCWH_SW_WATCHDOG_DISABLE |\
  48         HRCWH_ROM_LOC_LOCAL_16BIT |\
  49         HRCWH_RL_EXT_LEGACY |\
  50         HRCWH_TSEC1M_IN_RGMII |\
  51         HRCWH_TSEC2M_IN_RGMII |\
  52         HRCWH_BIG_ENDIAN |\
  53         HRCWH_LDP_CLEAR)
  54 #else
  55 #define CONFIG_SYS_HRCW_HIGH (\
  56         HRCWH_PCI_HOST |\
  57         HRCWH_PCI1_ARBITER_ENABLE |\
  58         HRCWH_CORE_ENABLE |\
  59         HRCWH_FROM_0X00000100 |\
  60         HRCWH_BOOTSEQ_DISABLE |\
  61         HRCWH_SW_WATCHDOG_DISABLE |\
  62         HRCWH_ROM_LOC_LOCAL_16BIT |\
  63         HRCWH_RL_EXT_LEGACY |\
  64         HRCWH_TSEC1M_IN_RGMII |\
  65         HRCWH_TSEC2M_IN_RGMII |\
  66         HRCWH_BIG_ENDIAN |\
  67         HRCWH_LDP_CLEAR)
  68 #endif
  69
  70 /* Arbiter Configuration Register */
  71 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  72 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count is 4 */
  73
  74 /* System Priority Control Register */
  75 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC1/2 emergency has highest priority */
  76
  77 /*
  78  * IP blocks clock configuration
  79  */
  80 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  81 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  82 #define CONFIG_SYS_SCCR_SATACM  SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
  83
  84 /*
  85  * System IO Config
  86  */
  87 #define CONFIG_SYS_SICRH                0x00000000
  88 #define CONFIG_SYS_SICRL                0x00000000
  89
  90 /*
  91  * Output Buffer Impedance
  92  */
  93 #define CONFIG_SYS_OBIR         0x31100000
  94
  95 #define CONFIG_HWCONFIG
  96
  97 /*
  98  * IMMR new address
  99  */
 100 #define CONFIG_SYS_IMMR         0xE0000000
 101
 102 /*
 103  * DDR Setup
 104  */
 105 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 106 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 107 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 108 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 109 #define CONFIG_SYS_83XX_DDR_USES_CS0
 110 #define CONFIG_SYS_DDRCDR_VALUE         (DDRCDR_DHC_EN \
 111                                         | DDRCDR_ODT \
 112                                         | DDRCDR_Q_DRN)
 113                                         /* 0x80080001 */ /* ODT 150ohm on SoC */
 114
 115 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 116 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 117
 118 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 119 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 120
 121 #if defined(CONFIG_SPD_EEPROM)
 122 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 123 #else
 124 /*
 125  * Manually set up DDR parameters
 126  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 127  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 128  */
 129 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
 131 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 132                         | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
 133                         | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
 134                         | CSCONFIG_ROW_BIT_14 \
 135                         | CSCONFIG_COL_BIT_10)
 136                         /* 0x80010202 */
 137 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 138 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 139                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 140                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 141                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 142                                 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 143                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 144                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 145                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 146                                 /* 0x00620802 */
 147 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 148                                 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 149                                 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 150                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 151                                 | (13 << TIMING_CFG1_REFREC_SHIFT) \
 152                                 | (3 << TIMING_CFG1_WRREC_SHIFT) \
 153                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 154                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 155                                 /* 0x3935d322 */
 156 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 157                                 | (6 << TIMING_CFG2_CPO_SHIFT) \
 158                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 159                                 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 160                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 161                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 162                                 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 163                                 /* 0x131088c8 */
 164 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
 165                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 166                                 /* 0x03E00100 */
 167 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 168 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 169 #define CONFIG_SYS_DDR_MODE     ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 170                                 | (0x1432 << SDRAM_MODE_SD_SHIFT))
 171                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 172 #define CONFIG_SYS_DDR_MODE2    0x00000000
 173 #endif
 174
 175 /*
 176  * Memory test
 177  */
 178 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 179 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 180 #define CONFIG_SYS_MEMTEST_END          0x00140000
 181
 182 /*
 183  * The reserved memory
 184  */
 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 186
 187 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 188 #define CONFIG_SYS_RAMBOOT
 189 #else
 190 #undef CONFIG_SYS_RAMBOOT
 191 #endif
 192
 193 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 194 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 195 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 196
 197 /*
 198  * Initial RAM Base Address Setup
 199  */
 200 #define CONFIG_SYS_INIT_RAM_LOCK        1
 201 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 202 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 204                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 205
 206 /*
 207  * Local Bus Configuration & Clock Setup
 208  */
 209 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 210 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
 211 #define CONFIG_SYS_LBC_LBCR             0x00000000
 212 #define CONFIG_FSL_ELBC         1
 213
 214 /*
 215  * FLASH on the Local Bus
 216  */
 217 #define CONFIG_SYS_FLASH_BASE   0xFE000000 /* FLASH base address */
 218 #define CONFIG_SYS_FLASH_SIZE   32 /* max FLASH size is 32M */
 219
 220                                         /* Window base at flash base */
 221 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 222 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 223
 224 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 225                                 | BR_PS_16      /* 16 bit port */ \
 226                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 227                                 | BR_V)         /* valid */
 228 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 229                                 | OR_UPM_XAM \
 230                                 | OR_GPCM_CSNT \
 231                                 | OR_GPCM_ACS_DIV2 \
 232                                 | OR_GPCM_XACS \
 233                                 | OR_GPCM_SCY_15 \
 234                                 | OR_GPCM_TRLX_SET \
 235                                 | OR_GPCM_EHTR_SET \
 236                                 | OR_GPCM_EAD)
 237                                 /* 0xFE000FF7 */
 238
 239 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 240 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 241
 242 #undef CONFIG_SYS_FLASH_CHECKSUM
 243 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 244 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 245
 246 /*
 247  * BCSR on the Local Bus
 248  */
 249 #define CONFIG_SYS_BCSR         0xF8000000
 250                                         /* Access window base at BCSR base */
 251 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 252 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 253
 254 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
 255                                 | BR_PS_8 \
 256                                 | BR_MS_GPCM \
 257                                 | BR_V)
 258                                 /* 0xF8000801 */
 259 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
 260                                 | OR_GPCM_XAM \
 261                                 | OR_GPCM_CSNT \
 262                                 | OR_GPCM_XACS \
 263                                 | OR_GPCM_SCY_15 \
 264                                 | OR_GPCM_TRLX_SET \
 265                                 | OR_GPCM_EHTR_SET \
 266                                 | OR_GPCM_EAD)
 267                                 /* 0xFFFFE9F7 */
 268
 269 /*
 270  * NAND Flash on the Local Bus
 271  */
 272 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 273 #define CONFIG_NAND_FSL_ELBC    1
 274
 275 #define CONFIG_SYS_NAND_BASE    0xE0600000
 276 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE \
 277                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 278                                 | BR_PS_8               /* 8 bit port */ \
 279                                 | BR_MS_FCM             /* MSEL = FCM */ \
 280                                 | BR_V)                 /* valid */
 281 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_32KB \
 282                                 | OR_FCM_BCTLD \
 283                                 | OR_FCM_CST \
 284                                 | OR_FCM_CHT \
 285                                 | OR_FCM_SCY_1 \
 286                                 | OR_FCM_RST \
 287                                 | OR_FCM_TRLX \
 288                                 | OR_FCM_EHTR)
 289                                 /* 0xFFFF919E */
 290
 291 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
 292 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 293
 294 /*
 295  * Serial Port
 296  */
 297 #define CONFIG_SYS_NS16550_SERIAL
 298 #define CONFIG_SYS_NS16550_REG_SIZE     1
 299 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 300
 301 #define CONFIG_SYS_BAUDRATE_TABLE  \
 302                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 303
 304 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 305 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 306
 307 /* I2C */
 308 #define CONFIG_SYS_I2C
 309 #define CONFIG_SYS_I2C_FSL
 310 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 311 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 312 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 313 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 314
 315 /*
 316  * Config on-board RTC
 317  */
 318 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 319 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 320
 321 /*
 322  * General PCI
 323  * Addresses are mapped 1-1.
 324  */
 325 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 326 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 327 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 328 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 329 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 330 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 331 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 332 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 333 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 334
 335 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 336 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 337 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 338
 339 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 340 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 341 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 342 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 343 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 344 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 345 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 346 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 347 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 348
 349 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 350 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 351 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 352 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 353 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 354 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 355 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 356 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 357 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 358
 359 #ifdef CONFIG_PCI
 360 #define CONFIG_PCI_INDIRECT_BRIDGE
 361 #ifndef __ASSEMBLY__
 362 extern int board_pci_host_broken(void);
 363 #endif
 364 #define CONFIG_PCIE
 365 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 366
 367 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 368 #define CONFIG_USB_EHCI_FSL
 369 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 370
 371 #undef CONFIG_EEPRO100
 372 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 373 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 374 #endif /* CONFIG_PCI */
 375
 376 /*
 377  * TSEC
 378  */
 379 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 380 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 381 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 382 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 383
 384 /*
 385  * TSEC ethernet configuration
 386  */
 387 #define CONFIG_TSEC1            1
 388 #define CONFIG_TSEC1_NAME       "eTSEC0"
 389 #define CONFIG_TSEC2            1
 390 #define CONFIG_TSEC2_NAME       "eTSEC1"
 391 #define TSEC1_PHY_ADDR          2
 392 #define TSEC2_PHY_ADDR          3
 393 #define TSEC1_PHY_ADDR_SGMII    8
 394 #define TSEC2_PHY_ADDR_SGMII    4
 395 #define TSEC1_PHYIDX            0
 396 #define TSEC2_PHYIDX            0
 397 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 398 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 399
 400 /* Options are: TSEC[0-1] */
 401 #define CONFIG_ETHPRIME         "eTSEC1"
 402
 403 /* SERDES */
 404 #define CONFIG_FSL_SERDES
 405 #define CONFIG_FSL_SERDES1      0xe3000
 406 #define CONFIG_FSL_SERDES2      0xe3100
 407
 408 /*
 409  * SATA
 410  */
 411 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 412 #define CONFIG_SATA1
 413 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 414 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 415 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 416 #define CONFIG_SATA2
 417 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 418 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 419 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 420
 421 #ifdef CONFIG_FSL_SATA
 422 #define CONFIG_LBA48
 423 #endif
 424
 425 /*
 426  * Environment
 427  */
 428 #ifndef CONFIG_SYS_RAMBOOT
 429         #define CONFIG_ENV_ADDR         \
 430                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 431         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 432         #define CONFIG_ENV_SIZE         0x2000
 433 #else
 434         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 435         #define CONFIG_ENV_SIZE         0x2000
 436 #endif
 437
 438 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 439 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 440
 441 /*
 442  * BOOTP options
 443  */
 444 #define CONFIG_BOOTP_BOOTFILESIZE
 445
 446 /*
 447  * Command line configuration.
 448  */
 449
 450 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 451
 452 #ifdef CONFIG_MMC
 453 #define CONFIG_FSL_ESDHC_PIN_MUX
 454 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 455 #endif
 456
 457 /*
 458  * Miscellaneous configurable options
 459  */
 460 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 461
 462 /*
 463  * For booting Linux, the board info and command line data
 464  * have to be in the first 256 MB of memory, since this is
 465  * the maximum mapped by the Linux kernel during initialization.
 466  */
 467 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 468 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 469
 470 /*
 471  * Core HID Setup
 472  */
 473 #define CONFIG_SYS_HID0_INIT    0x000000000
 474 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 475                                  HID0_ENABLE_INSTRUCTION_CACHE)
 476 #define CONFIG_SYS_HID2         HID2_HBE
 477
 478 /*
 479  * MMU Setup
 480  */
 481 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 482
 483 /* DDR: cache cacheable */
 484 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 485 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 486
 487 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER \
 488                                 | BATL_PP_RW \
 489                                 | BATL_MEMCOHERENCE)
 490 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER \
 491                                 | BATU_BL_256M \
 492                                 | BATU_VS \
 493                                 | BATU_VP)
 494 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 495 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 496
 497 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER \
 498                                 | BATL_PP_RW \
 499                                 | BATL_MEMCOHERENCE)
 500 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER \
 501                                 | BATU_BL_256M \
 502                                 | BATU_VS \
 503                                 | BATU_VP)
 504 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 505 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 506
 507 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 508 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR \
 509                                 | BATL_PP_RW \
 510                                 | BATL_CACHEINHIBIT \
 511                                 | BATL_GUARDEDSTORAGE)
 512 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR \
 513                                 | BATU_BL_8M \
 514                                 | BATU_VS \
 515                                 | BATU_VP)
 516 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 517 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 518
 519 /* BCSR: cache-inhibit and guarded */
 520 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR \
 521                                 | BATL_PP_RW \
 522                                 | BATL_CACHEINHIBIT \
 523                                 | BATL_GUARDEDSTORAGE)
 524 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR \
 525                                 | BATU_BL_128K \
 526                                 | BATU_VS \
 527                                 | BATU_VP)
 528 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 529 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 530
 531 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 532 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE \
 533                                 | BATL_PP_RW \
 534                                 | BATL_MEMCOHERENCE)
 535 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE \
 536                                 | BATU_BL_32M \
 537                                 | BATU_VS \
 538                                 | BATU_VP)
 539 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE \
 540                                 | BATL_PP_RW \
 541                                 | BATL_CACHEINHIBIT \
 542                                 | BATL_GUARDEDSTORAGE)
 543 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 544
 545 /* Stack in dcache: cacheable, no memory coherence */
 546 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 547 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 548                                 | BATU_BL_128K \
 549                                 | BATU_VS \
 550                                 | BATU_VP)
 551 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 552 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 553
 554 #ifdef CONFIG_PCI
 555 /* PCI MEM space: cacheable */
 556 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS \
 557                                 | BATL_PP_RW \
 558                                 | BATL_MEMCOHERENCE)
 559 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS \
 560                                 | BATU_BL_256M \
 561                                 | BATU_VS \
 562                                 | BATU_VP)
 563 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 564 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 565 /* PCI MMIO space: cache-inhibit and guarded */
 566 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS \
 567                                 | BATL_PP_RW \
 568                                 | BATL_CACHEINHIBIT \
 569                                 | BATL_GUARDEDSTORAGE)
 570 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS \
 571                                 | BATU_BL_256M \
 572                                 | BATU_VS \
 573                                 | BATU_VP)
 574 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 575 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 576 #else
 577 #define CONFIG_SYS_IBAT6L       (0)
 578 #define CONFIG_SYS_IBAT6U       (0)
 579 #define CONFIG_SYS_IBAT7L       (0)
 580 #define CONFIG_SYS_IBAT7U       (0)
 581 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 582 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 583 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 584 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 585 #endif
 586
 587 #if defined(CONFIG_CMD_KGDB)
 588 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 589 #endif
 590
 591 /*
 592  * Environment Configuration
 593  */
 594
 595 #define CONFIG_ENV_OVERWRITE
 596
 597 #if defined(CONFIG_TSEC_ENET)
 598 #define CONFIG_HAS_ETH0
 599 #define CONFIG_HAS_ETH1
 600 #endif
 601
 602 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 603
 604 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 605         "netdev=eth0\0"                                                 \
 606         "consoledev=ttyS0\0"                                            \
 607         "ramdiskaddr=1000000\0"                                         \
 608         "ramdiskfile=ramfs.83xx\0"                                      \
 609         "fdtaddr=780000\0"                                              \
 610         "fdtfile=mpc8379_mds.dtb\0"                                     \
 611         ""
 612
 613 #define CONFIG_NFSBOOTCOMMAND                                           \
 614         "setenv bootargs root=/dev/nfs rw "                             \
 615                 "nfsroot=$serverip:$rootpath "                          \
 616                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 617                                                         "$netdev:off "  \
 618                 "console=$consoledev,$baudrate $othbootargs;"           \
 619         "tftp $loadaddr $bootfile;"                                     \
 620         "tftp $fdtaddr $fdtfile;"                                       \
 621         "bootm $loadaddr - $fdtaddr"
 622
 623 #define CONFIG_RAMBOOTCOMMAND                                           \
 624         "setenv bootargs root=/dev/ram rw "                             \
 625                 "console=$consoledev,$baudrate $othbootargs;"           \
 626         "tftp $ramdiskaddr $ramdiskfile;"                               \
 627         "tftp $loadaddr $bootfile;"                                     \
 628         "tftp $fdtaddr $fdtfile;"                                       \
 629         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 630
 631 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 632
 633 #endif  /* __CONFIG_H */