2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * High Level Configuration Options
27 #define CONFIG_E300 1 /* E300 family */
28 #define CONFIG_MPC83XX 1 /* MPC83XX family */
29 #define CONFIG_MPC837X 1 /* MPC837X CPU specific */
30 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
35 #ifdef CONFIG_PCISLAVE
36 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
38 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
41 #ifndef CONFIG_SYS_CLK_FREQ
42 #define CONFIG_SYS_CLK_FREQ 66000000
46 * Hardware Reset Configuration Word
47 * if CLKIN is 66MHz, then
48 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
50 #define CONFIG_SYS_HRCW_LOW (\
51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_1X1 |\
54 HRCWL_CSB_TO_CLKIN_6X1 |\
55 HRCWL_CORE_TO_CSB_1_5X1)
57 #ifdef CONFIG_PCISLAVE
58 #define CONFIG_SYS_HRCW_HIGH (\
60 HRCWH_PCI1_ARBITER_DISABLE |\
62 HRCWH_FROM_0XFFF00100 |\
63 HRCWH_BOOTSEQ_DISABLE |\
64 HRCWH_SW_WATCHDOG_DISABLE |\
65 HRCWH_ROM_LOC_LOCAL_16BIT |\
66 HRCWH_RL_EXT_LEGACY |\
67 HRCWH_TSEC1M_IN_RGMII |\
68 HRCWH_TSEC2M_IN_RGMII |\
72 #define CONFIG_SYS_HRCW_HIGH (\
74 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
87 /* Arbiter Configuration Register */
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
89 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
91 /* System Priority Control Register */
92 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
95 * IP blocks clock configuration
97 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
98 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
99 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
104 #define CONFIG_SYS_SICRH 0x00000000
105 #define CONFIG_SYS_SICRL 0x00000000
108 * Output Buffer Impedance
110 #define CONFIG_SYS_OBIR 0x31100000
112 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
113 #define CONFIG_BOARD_EARLY_INIT_R
118 #define CONFIG_SYS_IMMR 0xE0000000
123 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
125 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
126 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
127 #define CONFIG_SYS_83XX_DDR_USES_CS0
128 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
130 #undef CONFIG_DDR_ECC /* support DDR ECC function */
131 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
133 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
134 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
136 #if defined(CONFIG_SPD_EEPROM)
137 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
140 * Manually set up DDR parameters
141 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
142 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
144 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
145 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
146 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \
147 | 0x00010000 /* ODT_WR to CSn */ \
148 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
150 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
151 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
152 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
153 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
154 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
155 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
156 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
157 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
158 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
160 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
161 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
162 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
163 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
164 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
165 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
166 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
167 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
169 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
170 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
171 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
172 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
173 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
174 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
175 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
177 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
178 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
180 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
181 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
182 #define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
183 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
184 /* ODT 150ohm CL=3, AL=1 on SDRAM */
185 #define CONFIG_SYS_DDR_MODE2 0x00000000
191 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
192 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
193 #define CONFIG_SYS_MEMTEST_END 0x00140000
196 * The reserved memory
198 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
200 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_RAMBOOT
203 #undef CONFIG_SYS_RAMBOOT
206 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
207 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
208 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
211 * Initial RAM Base Address Setup
213 #define CONFIG_SYS_INIT_RAM_LOCK 1
214 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
215 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
216 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
217 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
220 * Local Bus Configuration & Clock Setup
222 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
223 #define CONFIG_SYS_LBC_LBCR 0x00000000
226 * FLASH on the Local Bus
228 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
229 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
230 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
231 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
232 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
234 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
235 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
237 #define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
238 | (2 << BR_PS_SHIFT) /* 16 bit port size */ \
240 #define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
252 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
254 #undef CONFIG_SYS_FLASH_CHECKSUM
255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
259 * BCSR on the Local Bus
261 #define CONFIG_SYS_BCSR 0xF8000000
262 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
263 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
265 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
266 #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
269 * NAND Flash on the Local Bus
271 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
272 #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
273 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
274 | BR_PS_8 /* Port Size = 8 bit */ \
275 | BR_MS_FCM /* MSEL = FCM */ \
277 #define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
286 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
287 #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
292 #define CONFIG_CONS_INDEX 1
293 #undef CONFIG_SERIAL_SOFTWARE_FIFO
294 #define CONFIG_SYS_NS16550
295 #define CONFIG_SYS_NS16550_SERIAL
296 #define CONFIG_SYS_NS16550_REG_SIZE 1
297 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
299 #define CONFIG_SYS_BAUDRATE_TABLE \
300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
305 /* Use the HUSH parser */
306 #define CONFIG_SYS_HUSH_PARSER
307 #ifdef CONFIG_SYS_HUSH_PARSER
308 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
311 /* Pass open firmware flat tree */
312 #define CONFIG_OF_LIBFDT 1
313 #define CONFIG_OF_BOARD_SETUP 1
314 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
317 #define CONFIG_HARD_I2C /* I2C with hardware support */
318 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
319 #define CONFIG_FSL_I2C
320 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
321 #define CONFIG_SYS_I2C_SLAVE 0x7F
322 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
323 #define CONFIG_SYS_I2C_OFFSET 0x3000
324 #define CONFIG_SYS_I2C2_OFFSET 0x3100
327 * Config on-board RTC
329 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
330 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
334 * Addresses are mapped 1-1.
336 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
337 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
338 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
339 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
340 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
341 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
342 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
343 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
344 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
346 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
347 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
348 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
352 extern int board_pci_host_broken(void);
354 #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
355 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
357 #define CONFIG_NET_MULTI
358 #define CONFIG_PCI_PNP /* do pci plug-and-play */
360 #undef CONFIG_EEPRO100
361 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
362 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
363 #endif /* CONFIG_PCI */
365 #ifndef CONFIG_NET_MULTI
366 #define CONFIG_NET_MULTI 1
372 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
373 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
374 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
375 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
376 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
379 * TSEC ethernet configuration
381 #define CONFIG_MII 1 /* MII PHY management */
382 #define CONFIG_TSEC1 1
383 #define CONFIG_TSEC1_NAME "eTSEC0"
384 #define CONFIG_TSEC2 1
385 #define CONFIG_TSEC2_NAME "eTSEC1"
386 #define TSEC1_PHY_ADDR 2
387 #define TSEC2_PHY_ADDR 3
388 #define TSEC1_PHY_ADDR_SGMII 8
389 #define TSEC2_PHY_ADDR_SGMII 4
390 #define TSEC1_PHYIDX 0
391 #define TSEC2_PHYIDX 0
392 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
393 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
395 /* Options are: TSEC[0-1] */
396 #define CONFIG_ETHPRIME "eTSEC1"
399 #define CONFIG_FSL_SERDES
400 #define CONFIG_FSL_SERDES1 0xe3000
401 #define CONFIG_FSL_SERDES2 0xe3100
406 #define CONFIG_LIBATA
407 #define CONFIG_FSL_SATA
409 #define CONFIG_SYS_SATA_MAX_DEVICE 2
411 #define CONFIG_SYS_SATA1_OFFSET 0x18000
412 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
413 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
415 #define CONFIG_SYS_SATA2_OFFSET 0x19000
416 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
417 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
419 #ifdef CONFIG_FSL_SATA
421 #define CONFIG_CMD_SATA
422 #define CONFIG_DOS_PARTITION
423 #define CONFIG_CMD_EXT2
429 #ifndef CONFIG_SYS_RAMBOOT
430 #define CONFIG_ENV_IS_IN_FLASH 1
431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
433 #define CONFIG_ENV_SIZE 0x2000
435 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
436 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
438 #define CONFIG_ENV_SIZE 0x2000
441 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
442 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
447 #define CONFIG_BOOTP_BOOTFILESIZE
448 #define CONFIG_BOOTP_BOOTPATH
449 #define CONFIG_BOOTP_GATEWAY
450 #define CONFIG_BOOTP_HOSTNAME
454 * Command line configuration.
456 #include <config_cmd_default.h>
458 #define CONFIG_CMD_PING
459 #define CONFIG_CMD_I2C
460 #define CONFIG_CMD_MII
461 #define CONFIG_CMD_DATE
463 #if defined(CONFIG_PCI)
464 #define CONFIG_CMD_PCI
467 #if defined(CONFIG_SYS_RAMBOOT)
468 #undef CONFIG_CMD_ENV
469 #undef CONFIG_CMD_LOADS
472 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
474 #undef CONFIG_WATCHDOG /* watchdog disabled */
477 * Miscellaneous configurable options
479 #define CONFIG_SYS_LONGHELP /* undef to save memory */
480 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
481 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
483 #if defined(CONFIG_CMD_KGDB)
484 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
486 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
489 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
490 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
491 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
492 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
495 * For booting Linux, the board info and command line data
496 * have to be in the first 8 MB of memory, since this is
497 * the maximum mapped by the Linux kernel during initialization.
499 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
504 #define CONFIG_SYS_HID0_INIT 0x000000000
505 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
506 #define CONFIG_SYS_HID2 HID2_HBE
511 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
513 /* DDR: cache cacheable */
514 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
515 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
517 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
518 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
519 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
520 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
522 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
523 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
524 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
525 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
527 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
528 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
529 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
530 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
531 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
532 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
534 /* BCSR: cache-inhibit and guarded */
535 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \
536 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
537 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
538 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
539 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
541 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
542 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
543 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
544 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
545 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
546 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
548 /* Stack in dcache: cacheable, no memory coherence */
549 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
550 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
551 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
552 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
555 /* PCI MEM space: cacheable */
556 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
557 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
558 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
559 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
560 /* PCI MMIO space: cache-inhibit and guarded */
561 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
562 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
563 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
564 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
565 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
567 #define CONFIG_SYS_IBAT6L (0)
568 #define CONFIG_SYS_IBAT6U (0)
569 #define CONFIG_SYS_IBAT7L (0)
570 #define CONFIG_SYS_IBAT7U (0)
571 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
572 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
573 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
574 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
578 * Internal Definitions
582 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
583 #define BOOTFLAG_WARM 0x02 /* Software reboot */
585 #if defined(CONFIG_CMD_KGDB)
586 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
587 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
591 * Environment Configuration
594 #define CONFIG_ENV_OVERWRITE
596 #if defined(CONFIG_TSEC_ENET)
597 #define CONFIG_HAS_ETH0
598 #define CONFIG_ETHADDR 00:E0:0C:00:83:79
599 #define CONFIG_HAS_ETH1
600 #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
603 #define CONFIG_BAUDRATE 115200
605 #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
607 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
608 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
610 #define CONFIG_EXTRA_ENV_SETTINGS \
612 "consoledev=ttyS0\0" \
613 "ramdiskaddr=1000000\0" \
614 "ramdiskfile=ramfs.83xx\0" \
616 "fdtfile=mpc8379_mds.dtb\0" \
619 #define CONFIG_NFSBOOTCOMMAND \
620 "setenv bootargs root=/dev/nfs rw " \
621 "nfsroot=$serverip:$rootpath " \
622 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
623 "console=$consoledev,$baudrate $othbootargs;" \
624 "tftp $loadaddr $bootfile;" \
625 "tftp $fdtaddr $fdtfile;" \
626 "bootm $loadaddr - $fdtaddr"
628 #define CONFIG_RAMBOOTCOMMAND \
629 "setenv bootargs root=/dev/ram rw " \
630 "console=$consoledev,$baudrate $othbootargs;" \
631 "tftp $ramdiskaddr $ramdiskfile;" \
632 "tftp $loadaddr $bootfile;" \
633 "tftp $fdtaddr $fdtfile;" \
634 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
639 #endif /* __CONFIG_H */