1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
11 * High Level Configuration Options
13 #define CONFIG_E300 1 /* E300 family */
15 /* Arbiter Configuration Register */
16 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
17 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
19 /* System Priority Control Register */
20 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
23 * IP blocks clock configuration
25 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
26 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
27 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
32 #define CONFIG_SYS_SICRH 0x00000000
33 #define CONFIG_SYS_SICRL 0x00000000
36 * Output Buffer Impedance
38 #define CONFIG_SYS_OBIR 0x31100000
40 #define CONFIG_HWCONFIG
45 #define CONFIG_SYS_IMMR 0xE0000000
50 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
51 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
52 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
54 #define CONFIG_SYS_83XX_DDR_USES_CS0
55 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
58 /* 0x80080001 */ /* ODT 150ohm on SoC */
60 #undef CONFIG_DDR_ECC /* support DDR ECC function */
61 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
64 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
66 #if defined(CONFIG_SPD_EEPROM)
67 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
70 * Manually set up DDR parameters
71 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
72 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
74 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
75 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
76 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
77 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
78 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
79 | CSCONFIG_ROW_BIT_14 \
80 | CSCONFIG_COL_BIT_10)
82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
83 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
84 | (0 << TIMING_CFG0_WRT_SHIFT) \
85 | (0 << TIMING_CFG0_RRT_SHIFT) \
86 | (0 << TIMING_CFG0_WWT_SHIFT) \
87 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
88 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
89 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
90 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
92 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
93 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
94 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
95 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
96 | (13 << TIMING_CFG1_REFREC_SHIFT) \
97 | (3 << TIMING_CFG1_WRREC_SHIFT) \
98 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
99 | (2 << TIMING_CFG1_WRTORD_SHIFT))
101 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
102 | (6 << TIMING_CFG2_CPO_SHIFT) \
103 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
104 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
105 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
106 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
107 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
109 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
110 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
112 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
113 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
114 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
115 | (0x1432 << SDRAM_MODE_SD_SHIFT))
116 /* ODT 150ohm CL=3, AL=1 on SDRAM */
117 #define CONFIG_SYS_DDR_MODE2 0x00000000
123 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
124 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
125 #define CONFIG_SYS_MEMTEST_END 0x00140000
128 * The reserved memory
130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
133 #define CONFIG_SYS_RAMBOOT
135 #undef CONFIG_SYS_RAMBOOT
138 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
139 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
140 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
143 * Initial RAM Base Address Setup
145 #define CONFIG_SYS_INIT_RAM_LOCK 1
146 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
147 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
148 #define CONFIG_SYS_GBL_DATA_OFFSET \
149 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
152 * Local Bus Configuration & Clock Setup
154 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
155 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
156 #define CONFIG_SYS_LBC_LBCR 0x00000000
157 #define CONFIG_FSL_ELBC 1
160 * FLASH on the Local Bus
162 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
163 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
166 #define CONFIG_SYS_BR0_PRELIM (0xFE000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
167 #define CONFIG_SYS_OR0_PRELIM (OR_AM_32MB | OR_UPM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
169 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
172 #undef CONFIG_SYS_FLASH_CHECKSUM
173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
177 * BCSR on the Local Bus
179 #define CONFIG_SYS_BCSR 0xF8000000
180 /* Access window base at BCSR base */
182 #define CONFIG_SYS_BR1_PRELIM (0xF8000000 | BR_PS_8 | BR_MS_GPCM | BR_V)
183 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
186 * NAND Flash on the Local Bus
188 #define CONFIG_SYS_MAX_NAND_DEVICE 1
189 #define CONFIG_NAND_FSL_ELBC 1
191 #define CONFIG_SYS_NAND_BASE 0xE0600000
194 #define CONFIG_SYS_BR3_PRELIM (0xE0600000 | BR_DECC_CHK_GEN | BR_PS_8 | BR_MS_FCM | BR_V)
195 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST | OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST | OR_FCM_TRLX | OR_FCM_EHTR)
200 #define CONFIG_SYS_NS16550_SERIAL
201 #define CONFIG_SYS_NS16550_REG_SIZE 1
202 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
204 #define CONFIG_SYS_BAUDRATE_TABLE \
205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
211 #define CONFIG_SYS_I2C
212 #define CONFIG_SYS_I2C_FSL
213 #define CONFIG_SYS_FSL_I2C_SPEED 400000
214 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
215 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
216 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
219 * Config on-board RTC
221 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
222 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
226 * Addresses are mapped 1-1.
228 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
229 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
230 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
231 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
232 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
233 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
234 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
235 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
236 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
238 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
239 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
240 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
242 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
243 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
244 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
245 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
247 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
248 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
250 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
252 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
253 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
254 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
255 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
256 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
257 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
258 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
259 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
260 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
263 #define CONFIG_PCI_INDIRECT_BRIDGE
265 extern int board_pci_host_broken(void);
268 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
270 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
271 #define CONFIG_USB_EHCI_FSL
272 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
274 #undef CONFIG_EEPRO100
275 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
276 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
277 #endif /* CONFIG_PCI */
282 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
283 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
284 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
285 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
288 * TSEC ethernet configuration
290 #define CONFIG_TSEC1 1
291 #define CONFIG_TSEC1_NAME "eTSEC0"
292 #define CONFIG_TSEC2 1
293 #define CONFIG_TSEC2_NAME "eTSEC1"
294 #define TSEC1_PHY_ADDR 2
295 #define TSEC2_PHY_ADDR 3
296 #define TSEC1_PHY_ADDR_SGMII 8
297 #define TSEC2_PHY_ADDR_SGMII 4
298 #define TSEC1_PHYIDX 0
299 #define TSEC2_PHYIDX 0
300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
303 /* Options are: TSEC[0-1] */
304 #define CONFIG_ETHPRIME "eTSEC1"
307 #define CONFIG_FSL_SERDES
308 #define CONFIG_FSL_SERDES1 0xe3000
309 #define CONFIG_FSL_SERDES2 0xe3100
314 #define CONFIG_SYS_SATA_MAX_DEVICE 2
316 #define CONFIG_SYS_SATA1_OFFSET 0x18000
317 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
318 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
320 #define CONFIG_SYS_SATA2_OFFSET 0x19000
321 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
322 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
324 #ifdef CONFIG_FSL_SATA
331 #ifndef CONFIG_SYS_RAMBOOT
332 #define CONFIG_ENV_ADDR \
333 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
334 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
335 #define CONFIG_ENV_SIZE 0x2000
337 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
338 #define CONFIG_ENV_SIZE 0x2000
341 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
342 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
347 #define CONFIG_BOOTP_BOOTFILESIZE
350 * Command line configuration.
353 #undef CONFIG_WATCHDOG /* watchdog disabled */
356 #define CONFIG_FSL_ESDHC_PIN_MUX
357 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
361 * Miscellaneous configurable options
363 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
366 * For booting Linux, the board info and command line data
367 * have to be in the first 256 MB of memory, since this is
368 * the maximum mapped by the Linux kernel during initialization.
370 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
371 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
376 #define CONFIG_SYS_HID0_INIT 0x000000000
377 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
378 HID0_ENABLE_INSTRUCTION_CACHE)
379 #define CONFIG_SYS_HID2 HID2_HBE
381 #if defined(CONFIG_CMD_KGDB)
382 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
386 * Environment Configuration
389 #define CONFIG_ENV_OVERWRITE
391 #if defined(CONFIG_TSEC_ENET)
392 #define CONFIG_HAS_ETH0
393 #define CONFIG_HAS_ETH1
396 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
398 #define CONFIG_EXTRA_ENV_SETTINGS \
400 "consoledev=ttyS0\0" \
401 "ramdiskaddr=1000000\0" \
402 "ramdiskfile=ramfs.83xx\0" \
404 "fdtfile=mpc8379_mds.dtb\0" \
407 #define CONFIG_NFSBOOTCOMMAND \
408 "setenv bootargs root=/dev/nfs rw " \
409 "nfsroot=$serverip:$rootpath " \
410 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
412 "console=$consoledev,$baudrate $othbootargs;" \
413 "tftp $loadaddr $bootfile;" \
414 "tftp $fdtaddr $fdtfile;" \
415 "bootm $loadaddr - $fdtaddr"
417 #define CONFIG_RAMBOOTCOMMAND \
418 "setenv bootargs root=/dev/ram rw " \
419 "console=$consoledev,$baudrate $othbootargs;" \
420 "tftp $ramdiskaddr $ramdiskfile;" \
421 "tftp $loadaddr $bootfile;" \
422 "tftp $fdtaddr $fdtfile;" \
423 "bootm $loadaddr $ramdiskaddr $fdtaddr"
425 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
427 #endif /* __CONFIG_H */