include/configs/MPC837XEMDS.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  * Dave Liu <daveliu@freescale.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #ifndef __CONFIG_H
  22 #define __CONFIG_H
  23
  24 /*
  25  * High Level Configuration Options
  26  */
  27 #define CONFIG_E300             1 /* E300 family */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC837x          1 /* MPC837x CPU specific */
  30 #define CONFIG_MPC837XEMDS      1 /* MPC837XEMDS board specific */
  31
  32 /*
  33  * System Clock Setup
  34  */
  35 #ifdef CONFIG_PCISLAVE
  36 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  37 #else
  38 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  39 #endif
  40
  41 #ifndef CONFIG_SYS_CLK_FREQ
  42 #define CONFIG_SYS_CLK_FREQ     66000000
  43 #endif
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  * if CLKIN is 66MHz, then
  48  * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
  49  */
  50 #define CONFIG_SYS_HRCW_LOW (\
  51         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  52         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  53         HRCWL_SVCOD_DIV_2 |\
  54         HRCWL_CSB_TO_CLKIN_6X1 |\
  55         HRCWL_CORE_TO_CSB_1_5X1)
  56
  57 #ifdef CONFIG_PCISLAVE
  58 #define CONFIG_SYS_HRCW_HIGH (\
  59         HRCWH_PCI_AGENT |\
  60         HRCWH_PCI1_ARBITER_DISABLE |\
  61         HRCWH_CORE_ENABLE |\
  62         HRCWH_FROM_0XFFF00100 |\
  63         HRCWH_BOOTSEQ_DISABLE |\
  64         HRCWH_SW_WATCHDOG_DISABLE |\
  65         HRCWH_ROM_LOC_LOCAL_16BIT |\
  66         HRCWH_RL_EXT_LEGACY |\
  67         HRCWH_TSEC1M_IN_RGMII |\
  68         HRCWH_TSEC2M_IN_RGMII |\
  69         HRCWH_BIG_ENDIAN |\
  70         HRCWH_LDP_CLEAR)
  71 #else
  72 #define CONFIG_SYS_HRCW_HIGH (\
  73         HRCWH_PCI_HOST |\
  74         HRCWH_PCI1_ARBITER_ENABLE |\
  75         HRCWH_CORE_ENABLE |\
  76         HRCWH_FROM_0X00000100 |\
  77         HRCWH_BOOTSEQ_DISABLE |\
  78         HRCWH_SW_WATCHDOG_DISABLE |\
  79         HRCWH_ROM_LOC_LOCAL_16BIT |\
  80         HRCWH_RL_EXT_LEGACY |\
  81         HRCWH_TSEC1M_IN_RGMII |\
  82         HRCWH_TSEC2M_IN_RGMII |\
  83         HRCWH_BIG_ENDIAN |\
  84         HRCWH_LDP_CLEAR)
  85 #endif
  86
  87 /* Arbiter Configuration Register */
  88 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth is 4 */
  89 #define CONFIG_SYS_ACR_RPTCNT           3       /* Arbiter repeat count is 4 */
  90
  91 /* System Priority Control Register */
  92 #define CONFIG_SYS_SPCR_TSECEP          3       /* eTSEC1/2 emergency has highest priority */
  93
  94 /*
  95  * IP blocks clock configuration
  96  */
  97 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* CSB:eTSEC1 = 1:1 */
  98 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* CSB:eTSEC2 = 1:1 */
  99 #define CONFIG_SYS_SCCR_SATACM          SCCR_SATACM_2   /* CSB:SATA[0:3] = 2:1 */
 100
 101 /*
 102  * System IO Config
 103  */
 104 #define CONFIG_SYS_SICRH                0x00000000
 105 #define CONFIG_SYS_SICRL                0x00000000
 106
 107 /*
 108  * Output Buffer Impedance
 109  */
 110 #define CONFIG_SYS_OBIR         0x31100000
 111
 112 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 113 #define CONFIG_BOARD_EARLY_INIT_R
 114 #define CONFIG_HWCONFIG
 115
 116 /*
 117  * IMMR new address
 118  */
 119 #define CONFIG_SYS_IMMR         0xE0000000
 120
 121 /*
 122  * DDR Setup
 123  */
 124 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
 125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 126 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 127 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 128 #define CONFIG_SYS_83XX_DDR_USES_CS0
 129 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
 130
 131 #undef CONFIG_DDR_ECC           /* support DDR ECC function */
 132 #undef CONFIG_DDR_ECC_CMD       /* Use DDR ECC user commands */
 133
 134 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 135 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
 136
 137 #if defined(CONFIG_SPD_EEPROM)
 138 #define SPD_EEPROM_ADDRESS      0x51 /* I2C address of DDR SODIMM SPD */
 139 #else
 140 /*
 141  * Manually set up DDR parameters
 142  * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 143  * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 144  */
 145 #define CONFIG_SYS_DDR_SIZE             512 /* MB */
 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
 147 #define CONFIG_SYS_DDR_CS0_CONFIG       ( CSCONFIG_EN \
 148                                 | 0x00010000  /* ODT_WR to CSn */ \
 149                                 | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
 150                                 /* 0x80010202 */
 151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 152 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
 153                                 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
 154                                 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
 155                                 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
 156                                 | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
 157                                 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
 158                                 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
 159                                 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
 160                                 /* 0x00620802 */
 161 #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
 162                                 | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
 163                                 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
 164                                 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
 165                                 | (13 << TIMING_CFG1_REFREC_SHIFT ) \
 166                                 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
 167                                 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
 168                                 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
 169                                 /* 0x3935d322 */
 170 #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
 171                                 | ( 6 << TIMING_CFG2_CPO_SHIFT ) \
 172                                 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
 173                                 | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
 174                                 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
 175                                 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
 176                                 | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
 177                                 /* 0x131088c8 */
 178 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
 179                                 | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
 180                                 /* 0x03E00100 */
 181 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 182 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00001000 /* 1 posted refresh */
 183 #define CONFIG_SYS_DDR_MODE             ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
 184                                 | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
 185                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 186 #define CONFIG_SYS_DDR_MODE2            0x00000000
 187 #endif
 188
 189 /*
 190  * Memory test
 191  */
 192 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 193 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 194 #define CONFIG_SYS_MEMTEST_END          0x00140000
 195
 196 /*
 197  * The reserved memory
 198  */
 199 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 200
 201 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 202 #define CONFIG_SYS_RAMBOOT
 203 #else
 204 #undef CONFIG_SYS_RAMBOOT
 205 #endif
 206
 207 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 208 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 209 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024) /* Reserved for malloc */
 210
 211 /*
 212  * Initial RAM Base Address Setup
 213  */
 214 #define CONFIG_SYS_INIT_RAM_LOCK        1
 215 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 216 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 217 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 218 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 219
 220 /*
 221  * Local Bus Configuration & Clock Setup
 222  */
 223 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_CLKDIV_8)
 224 #define CONFIG_SYS_LBC_LBCR             0x00000000
 225
 226 /*
 227  * FLASH on the Local Bus
 228  */
 229 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 230 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 231 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 232 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 233 #define CONFIG_SYS_FLASH_PROTECTION     1               /* Use h/w Flash protection. */
 234
 235 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 236 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 237
 238 #define CONFIG_SYS_BR0_PRELIM           ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
 239                                 | (2 << BR_PS_SHIFT)    /* 16 bit port size */ \
 240                                 | BR_V )                /* valid */
 241 #define CONFIG_SYS_OR0_PRELIM           ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 242                                 | OR_UPM_XAM \
 243                                 | OR_GPCM_CSNT \
 244                                 | OR_GPCM_ACS_DIV2 \
 245                                 | OR_GPCM_XACS \
 246                                 | OR_GPCM_SCY_15 \
 247                                 | OR_GPCM_TRLX \
 248                                 | OR_GPCM_EHTR \
 249                                 | OR_GPCM_EAD )
 250                                 /* 0xFE000FF7 */
 251
 252 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 253 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 254
 255 #undef CONFIG_SYS_FLASH_CHECKSUM
 256 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 257 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 258
 259 /*
 260  * BCSR on the Local Bus
 261  */
 262 #define CONFIG_SYS_BCSR         0xF8000000
 263 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR /* Access window base at BCSR base */
 264 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000E /* Access window size 32K */
 265
 266 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
 267 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7 /* length 32K */
 268
 269 /*
 270  * NAND Flash on the Local Bus
 271  */
 272 #define CONFIG_CMD_NAND         1
 273 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 274 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 275 #define CONFIG_NAND_FSL_ELBC    1
 276
 277 #define CONFIG_SYS_NAND_BASE            0xE0600000      /* 0xE0600000 */
 278 #define CONFIG_SYS_BR3_PRELIM           ( CONFIG_SYS_NAND_BASE \
 279                                 | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 280                                 | BR_PS_8               /* Port Size = 8 bit */ \
 281                                 | BR_MS_FCM             /* MSEL = FCM */ \
 282                                 | BR_V )                /* valid */
 283 #define CONFIG_SYS_OR3_PRELIM           ( 0xFFFF8000            /* length 32K */ \
 284                                 | OR_FCM_BCTLD \
 285                                 | OR_FCM_CST \
 286                                 | OR_FCM_CHT \
 287                                 | OR_FCM_SCY_1 \
 288                                 | OR_FCM_RST \
 289                                 | OR_FCM_TRLX \
 290                                 | OR_FCM_EHTR )
 291                                 /* 0xFFFF919E */
 292
 293 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_NAND_BASE
 294 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000E      /* 32KB  */
 295
 296 /*
 297  * Serial Port
 298  */
 299 #define CONFIG_CONS_INDEX       1
 300 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 301 #define CONFIG_SYS_NS16550
 302 #define CONFIG_SYS_NS16550_SERIAL
 303 #define CONFIG_SYS_NS16550_REG_SIZE     1
 304 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 305
 306 #define CONFIG_SYS_BAUDRATE_TABLE  \
 307         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 308
 309 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 310 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 311
 312 /* Use the HUSH parser */
 313 #define CONFIG_SYS_HUSH_PARSER
 314 #ifdef CONFIG_SYS_HUSH_PARSER
 315 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 316 #endif
 317
 318 /* Pass open firmware flat tree */
 319 #define CONFIG_OF_LIBFDT        1
 320 #define CONFIG_OF_BOARD_SETUP   1
 321 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 322
 323 #define CONFIG_SYS_64BIT_STRTOUL                1
 324 #define CONFIG_SYS_64BIT_VSPRINTF               1
 325
 326 /* I2C */
 327 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 328 #undef CONFIG_SOFT_I2C          /* I2C bit-banged */
 329 #define CONFIG_FSL_I2C
 330 #define CONFIG_SYS_I2C_SPEED            400000 /* I2C speed and slave address */
 331 #define CONFIG_SYS_I2C_SLAVE            0x7F
 332 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
 333 #define CONFIG_SYS_I2C_OFFSET           0x3000
 334 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 335
 336 /*
 337  * Config on-board RTC
 338  */
 339 #define CONFIG_RTC_DS1374       /* use ds1374 rtc via i2c */
 340 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 341
 342 /*
 343  * General PCI
 344  * Addresses are mapped 1-1.
 345  */
 346 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
 347 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 348 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
 349 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 350 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 351 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 352 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 353 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 354 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 355
 356 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 357 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 358 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 359
 360 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 361 #define CONFIG_SYS_PCIE1_CFG_BASE       0xA0000000
 362 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x08000000
 363 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA8000000
 364 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA8000000
 365 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 366 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 367 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB8000000
 368 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 369
 370 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 371 #define CONFIG_SYS_PCIE2_CFG_BASE       0xC0000000
 372 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x08000000
 373 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC8000000
 374 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC8000000
 375 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 376 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 377 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD8000000
 378 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 379
 380 #ifdef CONFIG_PCI
 381 #ifndef __ASSEMBLY__
 382 extern int board_pci_host_broken(void);
 383 #endif
 384 #define CONFIG_PCIE
 385 #define CONFIG_PQ_MDS_PIB       1 /* PQ MDS Platform IO Board */
 386
 387 #define CONFIG_HAS_FSL_DR_USB   1 /* fixup device tree for the DR USB */
 388
 389 #define CONFIG_NET_MULTI
 390 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 391
 392 #undef CONFIG_EEPRO100
 393 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 394 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 395 #endif /* CONFIG_PCI */
 396
 397 #ifndef CONFIG_NET_MULTI
 398 #define CONFIG_NET_MULTI        1
 399 #endif
 400
 401 /*
 402  * TSEC
 403  */
 404 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 405 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 406 #define CONFIG_SYS_TSEC1                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 407 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 408 #define CONFIG_SYS_TSEC2                (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 409
 410 /*
 411  * TSEC ethernet configuration
 412  */
 413 #define CONFIG_MII              1 /* MII PHY management */
 414 #define CONFIG_TSEC1            1
 415 #define CONFIG_TSEC1_NAME       "eTSEC0"
 416 #define CONFIG_TSEC2            1
 417 #define CONFIG_TSEC2_NAME       "eTSEC1"
 418 #define TSEC1_PHY_ADDR          2
 419 #define TSEC2_PHY_ADDR          3
 420 #define TSEC1_PHY_ADDR_SGMII    8
 421 #define TSEC2_PHY_ADDR_SGMII    4
 422 #define TSEC1_PHYIDX            0
 423 #define TSEC2_PHYIDX            0
 424 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 425 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 426
 427 /* Options are: TSEC[0-1] */
 428 #define CONFIG_ETHPRIME         "eTSEC1"
 429
 430 /* SERDES */
 431 #define CONFIG_FSL_SERDES
 432 #define CONFIG_FSL_SERDES1      0xe3000
 433 #define CONFIG_FSL_SERDES2      0xe3100
 434
 435 /*
 436  * SATA
 437  */
 438 #define CONFIG_LIBATA
 439 #define CONFIG_FSL_SATA
 440
 441 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 442 #define CONFIG_SATA1
 443 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 444 #define CONFIG_SYS_SATA1                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 445 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 446 #define CONFIG_SATA2
 447 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 448 #define CONFIG_SYS_SATA2                (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 449 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 450
 451 #ifdef CONFIG_FSL_SATA
 452 #define CONFIG_LBA48
 453 #define CONFIG_CMD_SATA
 454 #define CONFIG_DOS_PARTITION
 455 #define CONFIG_CMD_EXT2
 456 #endif
 457
 458 /*
 459  * Environment
 460  */
 461 #ifndef CONFIG_SYS_RAMBOOT
 462         #define CONFIG_ENV_IS_IN_FLASH  1
 463         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 464         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 465         #define CONFIG_ENV_SIZE         0x2000
 466 #else
 467         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 468         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 469         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 470         #define CONFIG_ENV_SIZE         0x2000
 471 #endif
 472
 473 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 474 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 475
 476 /*
 477  * BOOTP options
 478  */
 479 #define CONFIG_BOOTP_BOOTFILESIZE
 480 #define CONFIG_BOOTP_BOOTPATH
 481 #define CONFIG_BOOTP_GATEWAY
 482 #define CONFIG_BOOTP_HOSTNAME
 483
 484
 485 /*
 486  * Command line configuration.
 487  */
 488 #include <config_cmd_default.h>
 489
 490 #define CONFIG_CMD_PING
 491 #define CONFIG_CMD_I2C
 492 #define CONFIG_CMD_MII
 493 #define CONFIG_CMD_DATE
 494
 495 #if defined(CONFIG_PCI)
 496     #define CONFIG_CMD_PCI
 497 #endif
 498
 499 #if defined(CONFIG_SYS_RAMBOOT)
 500     #undef CONFIG_CMD_SAVEENV
 501     #undef CONFIG_CMD_LOADS
 502 #endif
 503
 504 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 505
 506 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 507
 508 #define CONFIG_MMC     1
 509
 510 #ifdef CONFIG_MMC
 511 #define CONFIG_FSL_ESDHC
 512 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
 513 #define CONFIG_CMD_MMC
 514 #define CONFIG_GENERIC_MMC
 515 #define CONFIG_CMD_EXT2
 516 #define CONFIG_CMD_FAT
 517 #define CONFIG_DOS_PARTITION
 518 #endif
 519
 520 /*
 521  * Miscellaneous configurable options
 522  */
 523 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 524 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 525 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 526
 527 #if defined(CONFIG_CMD_KGDB)
 528         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 529 #else
 530         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 531 #endif
 532
 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 534 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 535 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 536 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 537
 538 /*
 539  * For booting Linux, the board info and command line data
 540  * have to be in the first 8 MB of memory, since this is
 541  * the maximum mapped by the Linux kernel during initialization.
 542  */
 543 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 544
 545 /*
 546  * Core HID Setup
 547  */
 548 #define CONFIG_SYS_HID0_INIT            0x000000000
 549 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 550 #define CONFIG_SYS_HID2         HID2_HBE
 551
 552 /*
 553  * MMU Setup
 554  */
 555 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 556
 557 /* DDR: cache cacheable */
 558 #define CONFIG_SYS_SDRAM_LOWER          CONFIG_SYS_SDRAM_BASE
 559 #define CONFIG_SYS_SDRAM_UPPER          (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 560
 561 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
 562 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
 563 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 564 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 565
 566 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
 567 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
 568 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 569 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 570
 571 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 572 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 573                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 574 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
 575 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 576 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 577
 578 /* BCSR: cache-inhibit and guarded */
 579 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_BCSR | BATL_PP_10 | \
 580                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 581 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
 582 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 583 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 584
 585 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 586 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 587 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
 588 #define CONFIG_SYS_DBAT4L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 589                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 590 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 591
 592 /* Stack in dcache: cacheable, no memory coherence */
 593 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 594 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 595 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 596 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 597
 598 #ifdef CONFIG_PCI
 599 /* PCI MEM space: cacheable */
 600 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 601 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 602 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 603 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 604 /* PCI MMIO space: cache-inhibit and guarded */
 605 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
 606                         BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 607 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 608 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 609 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 610 #else
 611 #define CONFIG_SYS_IBAT6L       (0)
 612 #define CONFIG_SYS_IBAT6U       (0)
 613 #define CONFIG_SYS_IBAT7L       (0)
 614 #define CONFIG_SYS_IBAT7U       (0)
 615 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 616 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 617 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 618 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 619 #endif
 620
 621 /*
 622  * Internal Definitions
 623  *
 624  * Boot Flags
 625  */
 626 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 627 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 628
 629 #if defined(CONFIG_CMD_KGDB)
 630 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 631 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 632 #endif
 633
 634 /*
 635  * Environment Configuration
 636  */
 637
 638 #define CONFIG_ENV_OVERWRITE
 639
 640 #if defined(CONFIG_TSEC_ENET)
 641 #define CONFIG_HAS_ETH0
 642 #define CONFIG_ETHADDR          00:E0:0C:00:83:79
 643 #define CONFIG_HAS_ETH1
 644 #define CONFIG_ETH1ADDR         00:E0:0C:00:83:78
 645 #endif
 646
 647 #define CONFIG_BAUDRATE 115200
 648
 649 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 650
 651 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 652 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 653
 654 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 655    "netdev=eth0\0"                                                      \
 656    "consoledev=ttyS0\0"                                                 \
 657    "ramdiskaddr=1000000\0"                                              \
 658    "ramdiskfile=ramfs.83xx\0"                                           \
 659    "fdtaddr=780000\0"                                                   \
 660    "fdtfile=mpc8379_mds.dtb\0"                                          \
 661    ""
 662
 663 #define CONFIG_NFSBOOTCOMMAND                                           \
 664    "setenv bootargs root=/dev/nfs rw "                                  \
 665       "nfsroot=$serverip:$rootpath "                                    \
 666       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 667       "console=$consoledev,$baudrate $othbootargs;"                     \
 668    "tftp $loadaddr $bootfile;"                                          \
 669    "tftp $fdtaddr $fdtfile;"                                            \
 670    "bootm $loadaddr - $fdtaddr"
 671
 672 #define CONFIG_RAMBOOTCOMMAND                                           \
 673    "setenv bootargs root=/dev/ram rw "                                  \
 674       "console=$consoledev,$baudrate $othbootargs;"                     \
 675    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 676    "tftp $loadaddr $bootfile;"                                          \
 677    "tftp $fdtaddr $fdtfile;"                                            \
 678    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 679
 680
 681 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 682
 683 #endif  /* __CONFIG_H */