1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
11 * High Level Configuration Options
13 #define CONFIG_E300 1 /* E300 family */
14 #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
19 #ifdef CONFIG_PCISLAVE
20 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
22 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
25 #ifndef CONFIG_SYS_CLK_FREQ
26 #define CONFIG_SYS_CLK_FREQ 66000000
30 * Hardware Reset Configuration Word
31 * if CLKIN is 66MHz, then
32 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
34 #define CONFIG_SYS_HRCW_LOW (\
35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
36 HRCWL_DDR_TO_SCB_CLK_1X1 |\
38 HRCWL_CSB_TO_CLKIN_6X1 |\
39 HRCWL_CORE_TO_CSB_1_5X1)
41 #ifdef CONFIG_PCISLAVE
42 #define CONFIG_SYS_HRCW_HIGH (\
44 HRCWH_PCI1_ARBITER_DISABLE |\
46 HRCWH_FROM_0XFFF00100 |\
47 HRCWH_BOOTSEQ_DISABLE |\
48 HRCWH_SW_WATCHDOG_DISABLE |\
49 HRCWH_ROM_LOC_LOCAL_16BIT |\
50 HRCWH_RL_EXT_LEGACY |\
51 HRCWH_TSEC1M_IN_RGMII |\
52 HRCWH_TSEC2M_IN_RGMII |\
56 #define CONFIG_SYS_HRCW_HIGH (\
58 HRCWH_PCI1_ARBITER_ENABLE |\
60 HRCWH_FROM_0X00000100 |\
61 HRCWH_BOOTSEQ_DISABLE |\
62 HRCWH_SW_WATCHDOG_DISABLE |\
63 HRCWH_ROM_LOC_LOCAL_16BIT |\
64 HRCWH_RL_EXT_LEGACY |\
65 HRCWH_TSEC1M_IN_RGMII |\
66 HRCWH_TSEC2M_IN_RGMII |\
71 /* Arbiter Configuration Register */
72 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
73 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
75 /* System Priority Control Register */
76 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
79 * IP blocks clock configuration
81 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
82 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
83 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
88 #define CONFIG_SYS_SICRH 0x00000000
89 #define CONFIG_SYS_SICRL 0x00000000
92 * Output Buffer Impedance
94 #define CONFIG_SYS_OBIR 0x31100000
96 #define CONFIG_HWCONFIG
101 #define CONFIG_SYS_IMMR 0xE0000000
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
110 #define CONFIG_SYS_83XX_DDR_USES_CS0
111 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
114 /* 0x80080001 */ /* ODT 150ohm on SoC */
116 #undef CONFIG_DDR_ECC /* support DDR ECC function */
117 #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
119 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
120 #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
122 #if defined(CONFIG_SPD_EEPROM)
123 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
126 * Manually set up DDR parameters
127 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
128 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
130 #define CONFIG_SYS_DDR_SIZE 512 /* MB */
131 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
132 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
133 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
134 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
135 | CSCONFIG_ROW_BIT_14 \
136 | CSCONFIG_COL_BIT_10)
138 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
139 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
140 | (0 << TIMING_CFG0_WRT_SHIFT) \
141 | (0 << TIMING_CFG0_RRT_SHIFT) \
142 | (0 << TIMING_CFG0_WWT_SHIFT) \
143 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
144 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
145 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
146 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
148 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
149 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
150 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
151 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
152 | (13 << TIMING_CFG1_REFREC_SHIFT) \
153 | (3 << TIMING_CFG1_WRREC_SHIFT) \
154 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
155 | (2 << TIMING_CFG1_WRTORD_SHIFT))
157 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
158 | (6 << TIMING_CFG2_CPO_SHIFT) \
159 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
160 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
161 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
162 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
163 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
165 #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
166 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
168 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
169 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
170 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
171 | (0x1432 << SDRAM_MODE_SD_SHIFT))
172 /* ODT 150ohm CL=3, AL=1 on SDRAM */
173 #define CONFIG_SYS_DDR_MODE2 0x00000000
179 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
180 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
181 #define CONFIG_SYS_MEMTEST_END 0x00140000
184 * The reserved memory
186 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
188 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
189 #define CONFIG_SYS_RAMBOOT
191 #undef CONFIG_SYS_RAMBOOT
194 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
195 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
196 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
199 * Initial RAM Base Address Setup
201 #define CONFIG_SYS_INIT_RAM_LOCK 1
202 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
203 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
204 #define CONFIG_SYS_GBL_DATA_OFFSET \
205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
208 * Local Bus Configuration & Clock Setup
210 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
211 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
212 #define CONFIG_SYS_LBC_LBCR 0x00000000
213 #define CONFIG_FSL_ELBC 1
216 * FLASH on the Local Bus
218 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
219 #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
221 /* Window base at flash base */
222 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
223 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
225 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
226 | BR_PS_16 /* 16 bit port */ \
227 | BR_MS_GPCM /* MSEL = GPCM */ \
229 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
240 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
241 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
243 #undef CONFIG_SYS_FLASH_CHECKSUM
244 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
248 * BCSR on the Local Bus
250 #define CONFIG_SYS_BCSR 0xF8000000
251 /* Access window base at BCSR base */
252 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
253 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
255 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
260 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
271 * NAND Flash on the Local Bus
273 #define CONFIG_SYS_MAX_NAND_DEVICE 1
274 #define CONFIG_NAND_FSL_ELBC 1
276 #define CONFIG_SYS_NAND_BASE 0xE0600000
277 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
278 | BR_DECC_CHK_GEN /* Use HW ECC */ \
279 | BR_PS_8 /* 8 bit port */ \
280 | BR_MS_FCM /* MSEL = FCM */ \
282 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
292 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
293 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
298 #define CONFIG_SYS_NS16550_SERIAL
299 #define CONFIG_SYS_NS16550_REG_SIZE 1
300 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
302 #define CONFIG_SYS_BAUDRATE_TABLE \
303 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
305 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
306 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
309 #define CONFIG_SYS_I2C
310 #define CONFIG_SYS_I2C_FSL
311 #define CONFIG_SYS_FSL_I2C_SPEED 400000
312 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
313 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
314 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
317 * Config on-board RTC
319 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
320 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
324 * Addresses are mapped 1-1.
326 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
327 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
328 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
329 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
330 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
331 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
332 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
333 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
334 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
336 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
337 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
338 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
340 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
341 #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
342 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
343 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
344 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
345 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
346 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
347 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
348 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
350 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
351 #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
352 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
353 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
354 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
355 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
356 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
357 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
358 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
361 #define CONFIG_PCI_INDIRECT_BRIDGE
363 extern int board_pci_host_broken(void);
366 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
368 #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
369 #define CONFIG_USB_EHCI_FSL
370 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
372 #undef CONFIG_EEPRO100
373 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
374 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
375 #endif /* CONFIG_PCI */
380 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
381 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
382 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
383 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
386 * TSEC ethernet configuration
388 #define CONFIG_TSEC1 1
389 #define CONFIG_TSEC1_NAME "eTSEC0"
390 #define CONFIG_TSEC2 1
391 #define CONFIG_TSEC2_NAME "eTSEC1"
392 #define TSEC1_PHY_ADDR 2
393 #define TSEC2_PHY_ADDR 3
394 #define TSEC1_PHY_ADDR_SGMII 8
395 #define TSEC2_PHY_ADDR_SGMII 4
396 #define TSEC1_PHYIDX 0
397 #define TSEC2_PHYIDX 0
398 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
399 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
401 /* Options are: TSEC[0-1] */
402 #define CONFIG_ETHPRIME "eTSEC1"
405 #define CONFIG_FSL_SERDES
406 #define CONFIG_FSL_SERDES1 0xe3000
407 #define CONFIG_FSL_SERDES2 0xe3100
412 #define CONFIG_SYS_SATA_MAX_DEVICE 2
414 #define CONFIG_SYS_SATA1_OFFSET 0x18000
415 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
416 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
418 #define CONFIG_SYS_SATA2_OFFSET 0x19000
419 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
420 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
422 #ifdef CONFIG_FSL_SATA
429 #ifndef CONFIG_SYS_RAMBOOT
430 #define CONFIG_ENV_ADDR \
431 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
432 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
433 #define CONFIG_ENV_SIZE 0x2000
435 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
436 #define CONFIG_ENV_SIZE 0x2000
439 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
440 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
445 #define CONFIG_BOOTP_BOOTFILESIZE
448 * Command line configuration.
451 #undef CONFIG_WATCHDOG /* watchdog disabled */
454 #define CONFIG_FSL_ESDHC_PIN_MUX
455 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
459 * Miscellaneous configurable options
461 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
464 * For booting Linux, the board info and command line data
465 * have to be in the first 256 MB of memory, since this is
466 * the maximum mapped by the Linux kernel during initialization.
468 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
469 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
474 #define CONFIG_SYS_HID0_INIT 0x000000000
475 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
476 HID0_ENABLE_INSTRUCTION_CACHE)
477 #define CONFIG_SYS_HID2 HID2_HBE
482 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
484 /* DDR: cache cacheable */
485 #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
486 #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
488 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
491 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
495 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
496 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
498 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
501 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
505 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
506 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
508 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
509 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
511 | BATL_CACHEINHIBIT \
512 | BATL_GUARDEDSTORAGE)
513 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
517 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
518 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
520 /* BCSR: cache-inhibit and guarded */
521 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
523 | BATL_CACHEINHIBIT \
524 | BATL_GUARDEDSTORAGE)
525 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
529 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
530 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
532 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
533 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
536 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
540 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
542 | BATL_CACHEINHIBIT \
543 | BATL_GUARDEDSTORAGE)
544 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
546 /* Stack in dcache: cacheable, no memory coherence */
547 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
548 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
552 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
553 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
556 /* PCI MEM space: cacheable */
557 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
560 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
564 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
565 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
566 /* PCI MMIO space: cache-inhibit and guarded */
567 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
569 | BATL_CACHEINHIBIT \
570 | BATL_GUARDEDSTORAGE)
571 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
575 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
576 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
578 #define CONFIG_SYS_IBAT6L (0)
579 #define CONFIG_SYS_IBAT6U (0)
580 #define CONFIG_SYS_IBAT7L (0)
581 #define CONFIG_SYS_IBAT7U (0)
582 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
583 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
584 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
585 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
588 #if defined(CONFIG_CMD_KGDB)
589 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
593 * Environment Configuration
596 #define CONFIG_ENV_OVERWRITE
598 #if defined(CONFIG_TSEC_ENET)
599 #define CONFIG_HAS_ETH0
600 #define CONFIG_HAS_ETH1
603 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
605 #define CONFIG_EXTRA_ENV_SETTINGS \
607 "consoledev=ttyS0\0" \
608 "ramdiskaddr=1000000\0" \
609 "ramdiskfile=ramfs.83xx\0" \
611 "fdtfile=mpc8379_mds.dtb\0" \
614 #define CONFIG_NFSBOOTCOMMAND \
615 "setenv bootargs root=/dev/nfs rw " \
616 "nfsroot=$serverip:$rootpath " \
617 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $loadaddr $bootfile;" \
621 "tftp $fdtaddr $fdtfile;" \
622 "bootm $loadaddr - $fdtaddr"
624 #define CONFIG_RAMBOOTCOMMAND \
625 "setenv bootargs root=/dev/ram rw " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $ramdiskaddr $ramdiskfile;" \
628 "tftp $loadaddr $bootfile;" \
629 "tftp $fdtaddr $fdtfile;" \
630 "bootm $loadaddr $ramdiskaddr $fdtaddr"
632 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
634 #endif /* __CONFIG_H */