include/configs/MPC8360EMDS.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Configuration Options
  27  */
  28 #define CONFIG_E300             1 /* E300 family */
  29 #define CONFIG_QE               1 /* Has QE */
  30 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  31 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  32 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
  33
  34 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  35
  36 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
  37 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
  38
  39 /*
  40  * System Clock Setup
  41  */
  42 #ifdef CONFIG_PCISLAVE
  43 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
  44 #else
  45 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
  46 #endif
  47
  48 #ifndef CONFIG_SYS_CLK_FREQ
  49 #define CONFIG_SYS_CLK_FREQ     66000000
  50 #endif
  51
  52 /*
  53  * Hardware Reset Configuration Word
  54  */
  55 #define CONFIG_SYS_HRCW_LOW (\
  56         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  57         HRCWL_DDR_TO_SCB_CLK_1X1 |\
  58         HRCWL_CSB_TO_CLKIN_4X1 |\
  59         HRCWL_VCO_1X2 |\
  60         HRCWL_CE_PLL_VCO_DIV_4 |\
  61         HRCWL_CE_PLL_DIV_1X1 |\
  62         HRCWL_CE_TO_PLL_1X6 |\
  63         HRCWL_CORE_TO_CSB_2X1)
  64
  65 #ifdef CONFIG_PCISLAVE
  66 #define CONFIG_SYS_HRCW_HIGH (\
  67         HRCWH_PCI_AGENT |\
  68         HRCWH_PCI1_ARBITER_DISABLE |\
  69         HRCWH_PCICKDRV_DISABLE |\
  70         HRCWH_CORE_ENABLE |\
  71         HRCWH_FROM_0XFFF00100 |\
  72         HRCWH_BOOTSEQ_DISABLE |\
  73         HRCWH_SW_WATCHDOG_DISABLE |\
  74         HRCWH_ROM_LOC_LOCAL_16BIT)
  75 #else
  76 #define CONFIG_SYS_HRCW_HIGH (\
  77         HRCWH_PCI_HOST |\
  78         HRCWH_PCI1_ARBITER_ENABLE |\
  79         HRCWH_PCICKDRV_ENABLE |\
  80         HRCWH_CORE_ENABLE |\
  81         HRCWH_FROM_0X00000100 |\
  82         HRCWH_BOOTSEQ_DISABLE |\
  83         HRCWH_SW_WATCHDOG_DISABLE |\
  84         HRCWH_ROM_LOC_LOCAL_16BIT)
  85 #endif
  86
  87 /*
  88  * System IO Config
  89  */
  90 #define CONFIG_SYS_SICRH                0x00000000
  91 #define CONFIG_SYS_SICRL                0x40000000
  92
  93 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  94 #define CONFIG_BOARD_EARLY_INIT_R
  95
  96 /*
  97  * IMMR new address
  98  */
  99 #define CONFIG_SYS_IMMR         0xE0000000
 100
 101 /*
 102  * DDR Setup
 103  */
 104 #define CONFIG_SYS_DDR_BASE     0x00000000 /* DDR is system memory */
 105 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
 106                                 /* + 256M */
 107 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 108 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 110                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 111
 112 #define CONFIG_SYS_83XX_DDR_USES_CS0
 113
 114 #define CONFIG_DDR_ECC          /* support DDR ECC function */
 115 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
 116
 117 /*
 118  * DDRCDR - DDR Control Driver Register
 119  */
 120 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 121
 122 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
 123 #if defined(CONFIG_SPD_EEPROM)
 124 /*
 125  * Determine DDR configuration from I2C interface.
 126  */
 127 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
 128 #else
 129 /*
 130  * Manually set up DDR parameters
 131  */
 132 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
 133 #if defined(CONFIG_DDR_II)
 134 #define CONFIG_SYS_DDRCDR               0x80080001
 135 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
 136 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
 137 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 138 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 139 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 140 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 141 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 142 #define CONFIG_SYS_DDR_MODE             0x47d00432
 143 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 144 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 145 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 146 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 147 #else
 148 #define CONFIG_SYS_DDR_CONFIG   (CSCONFIG_EN \
 149                                 | CSCONFIG_ROW_BIT_13 \
 150                                 | CSCONFIG_COL_BIT_9)
 151 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 152 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
 153 #define CONFIG_SYS_DDR_CONTROL  0x42008000 /* Self refresh,2T timing */
 154 #define CONFIG_SYS_DDR_MODE     0x20000162 /* DLL,normal,seq,4/2.5 */
 155 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
 156 #endif
 157 #endif
 158
 159 /*
 160  * Memory test
 161  */
 162 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 163 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
 164 #define CONFIG_SYS_MEMTEST_END          0x00100000
 165
 166 /*
 167  * The reserved memory
 168  */
 169
 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 171
 172 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 173 #define CONFIG_SYS_RAMBOOT
 174 #else
 175 #undef  CONFIG_SYS_RAMBOOT
 176 #endif
 177
 178 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 179 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 180 #define CONFIG_SYS_MALLOC_LEN   (128 * 1024) /* Reserved for malloc */
 181
 182 /*
 183  * Initial RAM Base Address Setup
 184  */
 185 #define CONFIG_SYS_INIT_RAM_LOCK        1
 186 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 187 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 188 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 189                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 190
 191 /*
 192  * Local Bus Configuration & Clock Setup
 193  */
 194 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 195 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 196 #define CONFIG_SYS_LBC_LBCR     0x00000000
 197
 198 /*
 199  * FLASH on the Local Bus
 200  */
 201 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 202 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 203 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 204 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
 205 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
 206 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 207
 208                                         /* Window base at flash base */
 209 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 210 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000018 /* 32MB window size */
 211
 212 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 213                                 | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
 214                                 | BR_V)                 /* valid */
 215 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
 216                                 | OR_UPM_XAM \
 217                                 | OR_GPCM_CSNT \
 218                                 | OR_GPCM_ACS_DIV2 \
 219                                 | OR_GPCM_XACS \
 220                                 | OR_GPCM_SCY_15 \
 221                                 | OR_GPCM_TRLX \
 222                                 | OR_GPCM_EHTR \
 223                                 | OR_GPCM_EAD)
 224
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
 227
 228 #undef  CONFIG_SYS_FLASH_CHECKSUM
 229
 230 /*
 231  * BCSR on the Local Bus
 232  */
 233 #define CONFIG_SYS_BCSR                 0xF8000000
 234                                         /* Access window base at BCSR base */
 235 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 236 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000000F /* Access window size 64K */
 237
 238                                         /* Port size=8bit, MSEL=GPCM */
 239 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR|0x00000801)
 240 #define CONFIG_SYS_OR1_PRELIM           0xFFFFE9f7 /* length 32K */
 241
 242 /*
 243  * SDRAM on the Local Bus
 244  */
 245 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
 246 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 247
 248 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
 249
 250 #ifdef CONFIG_SYS_LB_SDRAM
 251 #define CONFIG_SYS_LBLAWBAR2            0
 252 #define CONFIG_SYS_LBLAWAR2             0x80000019 /* 64MB */
 253
 254 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
 255 /*
 256  * Base Register 2 and Option Register 2 configure SDRAM.
 257  *
 258  * For BR2, need:
 259  *    Base address = BR[0:16] = dynamic
 260  *    port size = 32-bits = BR2[19:20] = 11
 261  *    no parity checking = BR2[21:22] = 00
 262  *    SDRAM for MSEL = BR2[24:26] = 011
 263  *    Valid = BR[31] = 1
 264  *
 265  * 0    4    8    12   16   20   24   28
 266  * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
 267  */
 268
 269 #define CONFIG_SYS_BR2          0x00001861 /*Port size=32bit, MSEL=SDRAM */
 270
 271 /*
 272  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 273  *
 274  * For OR2, need:
 275  *    64MB mask for AM, OR2[0:7] = 1111 1100
 276  *                 XAM, OR2[17:18] = 11
 277  *    9 columns OR2[19-21] = 010
 278  *    13 rows   OR2[23-25] = 100
 279  *    EAD set for extra time OR[31] = 1
 280  *
 281  * 0    4    8    12   16   20   24   28
 282  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 283  */
 284
 285 #define CONFIG_SYS_OR2          0xfc006901
 286
 287                                 /* LB sdram refresh timer, about 6us */
 288 #define CONFIG_SYS_LBC_LSRT     0x32000000
 289                                 /* LB refresh timer prescal, 266MHz/32 */
 290 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 291
 292 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
 293
 294 /*
 295  * SDRAM Controller configuration sequence.
 296  */
 297 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 298 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 299 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 300 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 301 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 302
 303 #endif
 304
 305 /*
 306  * Windows to access PIB via local bus
 307  */
 308 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0xf8010000 /* windows base 0xf8010000 */
 309 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000000e /* windows size 32KB */
 310
 311 /*
 312  * CS4 on Local Bus, to PIB
 313  */
 314 #define CONFIG_SYS_BR4_PRELIM   0xf8008801 /* CS4 base address at 0xf8008000 */
 315 #define CONFIG_SYS_OR4_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 316
 317 /*
 318  * CS5 on Local Bus, to PIB
 319  */
 320 #define CONFIG_SYS_BR5_PRELIM   0xf8010801 /* CS5 base address at 0xf8010000 */
 321 #define CONFIG_SYS_OR5_PRELIM   0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 322
 323 /*
 324  * Serial Port
 325  */
 326 #define CONFIG_CONS_INDEX       1
 327 #define CONFIG_SYS_NS16550
 328 #define CONFIG_SYS_NS16550_SERIAL
 329 #define CONFIG_SYS_NS16550_REG_SIZE     1
 330 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 331
 332 #define CONFIG_SYS_BAUDRATE_TABLE  \
 333                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 334
 335 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 336 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 337
 338 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 339 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 340 /* Use the HUSH parser */
 341 #define CONFIG_SYS_HUSH_PARSER
 342 #ifdef  CONFIG_SYS_HUSH_PARSER
 343 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 344 #endif
 345
 346 /* pass open firmware flat tree */
 347 #define CONFIG_OF_LIBFDT        1
 348 #define CONFIG_OF_BOARD_SETUP   1
 349 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 350
 351 /* I2C */
 352 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 353 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 354 #define CONFIG_FSL_I2C
 355 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 356 #define CONFIG_SYS_I2C_SLAVE    0x7F
 357 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
 358 #define CONFIG_SYS_I2C_OFFSET   0x3000
 359 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 360
 361 /*
 362  * Config on-board RTC
 363  */
 364 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 365 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 366
 367 /*
 368  * General PCI
 369  * Addresses are mapped 1-1.
 370  */
 371 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 372 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 373 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
 374 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 375 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 376 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
 377 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 378 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
 379 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
 380
 381 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 382 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 383 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 384
 385
 386 #ifdef CONFIG_PCI
 387
 388 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 389 #define CONFIG_83XX_PCI_STREAMING
 390
 391 #undef CONFIG_EEPRO100
 392 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 393 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 394
 395 #endif  /* CONFIG_PCI */
 396
 397
 398 #define CONFIG_HWCONFIG         1
 399
 400 /*
 401  * QE UEC ethernet configuration
 402  */
 403 #define CONFIG_UEC_ETH
 404 #define CONFIG_ETHPRIME         "UEC0"
 405 #define CONFIG_PHY_MODE_NEED_CHANGE
 406
 407 #define CONFIG_UEC_ETH1         /* GETH1 */
 408
 409 #ifdef CONFIG_UEC_ETH1
 410 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 411 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
 412 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
 413 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
 414 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 415 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 416 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
 417 #endif
 418
 419 #define CONFIG_UEC_ETH2         /* GETH2 */
 420
 421 #ifdef CONFIG_UEC_ETH2
 422 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 423 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
 424 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
 425 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
 426 #define CONFIG_SYS_UEC2_PHY_ADDR        1
 427 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
 428 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
 429 #endif
 430
 431 /*
 432  * Environment
 433  */
 434
 435 #ifndef CONFIG_SYS_RAMBOOT
 436         #define CONFIG_ENV_IS_IN_FLASH  1
 437         #define CONFIG_ENV_ADDR         \
 438                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 439         #define CONFIG_ENV_SECT_SIZE    0x20000
 440         #define CONFIG_ENV_SIZE         0x2000
 441 #else
 442         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 443         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 444         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 445         #define CONFIG_ENV_SIZE         0x2000
 446 #endif
 447
 448 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 449 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 450
 451 /*
 452  * BOOTP options
 453  */
 454 #define CONFIG_BOOTP_BOOTFILESIZE
 455 #define CONFIG_BOOTP_BOOTPATH
 456 #define CONFIG_BOOTP_GATEWAY
 457 #define CONFIG_BOOTP_HOSTNAME
 458
 459
 460 /*
 461  * Command line configuration.
 462  */
 463 #include <config_cmd_default.h>
 464
 465 #define CONFIG_CMD_PING
 466 #define CONFIG_CMD_I2C
 467 #define CONFIG_CMD_ASKENV
 468 #define CONFIG_CMD_SDRAM
 469
 470 #if defined(CONFIG_PCI)
 471     #define CONFIG_CMD_PCI
 472 #endif
 473
 474 #if defined(CONFIG_SYS_RAMBOOT)
 475     #undef CONFIG_CMD_SAVEENV
 476     #undef CONFIG_CMD_LOADS
 477 #endif
 478
 479
 480 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 481
 482 /*
 483  * Miscellaneous configurable options
 484  */
 485 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 486 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 487 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
 488
 489 #if defined(CONFIG_CMD_KGDB)
 490         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 491 #else
 492         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 493 #endif
 494
 495                                 /* Print Buffer Size */
 496 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 497 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 498                                 /* Boot Argument Buffer Size */
 499 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 500 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 501
 502 /*
 503  * For booting Linux, the board info and command line data
 504  * have to be in the first 256 MB of memory, since this is
 505  * the maximum mapped by the Linux kernel during initialization.
 506  */
 507 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 508
 509 /*
 510  * Core HID Setup
 511  */
 512 #define CONFIG_SYS_HID0_INIT    0x000000000
 513 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 514                                  HID0_ENABLE_INSTRUCTION_CACHE)
 515 #define CONFIG_SYS_HID2         HID2_HBE
 516
 517 /*
 518  * MMU Setup
 519  */
 520
 521 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 522
 523 /* DDR/LBC SDRAM: cacheable */
 524 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 525                                 | BATL_PP_RW \
 526                                 | BATL_MEMCOHERENCE)
 527 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 528                                 | BATU_BL_256M \
 529                                 | BATU_VS \
 530                                 | BATU_VP)
 531 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 532 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 533
 534 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 535 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 536                                 | BATL_PP_RW \
 537                                 | BATL_CACHEINHIBIT \
 538                                 | BATL_GUARDEDSTORAGE)
 539 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 540                                 | BATU_BL_4M \
 541                                 | BATU_VS \
 542                                 | BATU_VP)
 543 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 544 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 545
 546 /* BCSR: cache-inhibit and guarded */
 547 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
 548                                 | BATL_PP_RW \
 549                                 | BATL_CACHEINHIBIT \
 550                                 | BATL_GUARDEDSTORAGE)
 551 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
 552                                 | BATU_BL_128K \
 553                                 | BATU_VS \
 554                                 | BATU_VP)
 555 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 556 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 557
 558 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 559 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
 560                                 | BATL_PP_RW \
 561                                 | BATL_MEMCOHERENCE)
 562 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
 563                                 | BATU_BL_32M \
 564                                 | BATU_VS \
 565                                 | BATU_VP)
 566 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
 567                                 | BATL_PP_RW \
 568                                 | BATL_CACHEINHIBIT \
 569                                 | BATL_GUARDEDSTORAGE)
 570 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 571
 572 /* DDR/LBC SDRAM next 256M: cacheable */
 573 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_SDRAM_BASE2 \
 574                                 | BATL_PP_RW \
 575                                 | BATL_MEMCOHERENCE)
 576 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_SDRAM_BASE2 \
 577                                 | BATU_BL_256M \
 578                                 | BATU_VS \
 579                                 | BATU_VP)
 580 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 581 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 582
 583 /* Stack in dcache: cacheable, no memory coherence */
 584 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 585 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
 586                                 | BATU_BL_128K \
 587                                 | BATU_VS \
 588                                 | BATU_VP)
 589 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 590 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 591
 592 #ifdef CONFIG_PCI
 593 /* PCI MEM space: cacheable */
 594 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
 595                                 | BATL_PP_RW \
 596                                 | BATL_MEMCOHERENCE)
 597 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
 598                                 | BATU_BL_256M \
 599                                 | BATU_VS \
 600                                 | BATU_VP)
 601 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 602 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 603 /* PCI MMIO space: cache-inhibit and guarded */
 604 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 605                                 | BATL_PP_RW \
 606                                 | BATL_CACHEINHIBIT \
 607                                 | BATL_GUARDEDSTORAGE)
 608 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 609                                 | BATU_BL_256M \
 610                                 | BATU_VS \
 611                                 | BATU_VP)
 612 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 613 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 614 #else
 615 #define CONFIG_SYS_IBAT6L       (0)
 616 #define CONFIG_SYS_IBAT6U       (0)
 617 #define CONFIG_SYS_IBAT7L       (0)
 618 #define CONFIG_SYS_IBAT7U       (0)
 619 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 620 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 621 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 622 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 623 #endif
 624
 625 #if defined(CONFIG_CMD_KGDB)
 626 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 627 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 628 #endif
 629
 630 /*
 631  * Environment Configuration
 632  */
 633
 634 #define CONFIG_ENV_OVERWRITE
 635
 636 #if defined(CONFIG_UEC_ETH)
 637 #define CONFIG_HAS_ETH0
 638 #define CONFIG_HAS_ETH1
 639 #endif
 640
 641 #define CONFIG_BAUDRATE 115200
 642
 643 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 644
 645 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 646 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 647
 648 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 649         "netdev=eth0\0"                                                 \
 650         "consoledev=ttyS0\0"                                            \
 651         "ramdiskaddr=1000000\0"                                         \
 652         "ramdiskfile=ramfs.83xx\0"                                      \
 653         "fdtaddr=780000\0"                                              \
 654         "fdtfile=mpc836x_mds.dtb\0"                                     \
 655         ""
 656
 657 #define CONFIG_NFSBOOTCOMMAND                                           \
 658         "setenv bootargs root=/dev/nfs rw "                             \
 659                 "nfsroot=$serverip:$rootpath "                          \
 660                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 661                                                         "$netdev:off "  \
 662                 "console=$consoledev,$baudrate $othbootargs;"           \
 663         "tftp $loadaddr $bootfile;"                                     \
 664         "tftp $fdtaddr $fdtfile;"                                       \
 665         "bootm $loadaddr - $fdtaddr"
 666
 667 #define CONFIG_RAMBOOTCOMMAND                                           \
 668         "setenv bootargs root=/dev/ram rw "                             \
 669                 "console=$consoledev,$baudrate $othbootargs;"           \
 670         "tftp $ramdiskaddr $ramdiskfile;"                               \
 671         "tftp $loadaddr $bootfile;"                                     \
 672         "tftp $fdtaddr $fdtfile;"                                       \
 673         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 674
 675
 676 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 677
 678 #endif  /* __CONFIG_H */