Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
[platform/kernel/u-boot.git] / include / configs / MPC8360EMDS.h
1 /*
2  * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
3  *
4  * Dave Liu <daveliu@freescale.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21
22 #ifndef __CONFIG_H
23 #define __CONFIG_H
24
25 /*
26  * High Level Configuration Options
27  */
28 #define CONFIG_E300             1 /* E300 family */
29 #define CONFIG_QE               1 /* Has QE */
30 #define CONFIG_MPC83xx          1 /* MPC83xx family */
31 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
32 #define CONFIG_MPC8360EMDS      1 /* MPC8360EMDS board specific */
33
34 #define CONFIG_SYS_TEXT_BASE    0xFE000000
35
36 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
37 #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
38
39 /*
40  * System Clock Setup
41  */
42 #ifdef CONFIG_CLKIN_33MHZ
43 #ifdef CONFIG_PCISLAVE
44 #define CONFIG_83XX_PCICLK      33330000 /* in HZ */
45 #else
46 #define CONFIG_83XX_CLKIN       33330000 /* in Hz */
47 #endif
48
49 #ifndef CONFIG_SYS_CLK_FREQ
50 #define CONFIG_SYS_CLK_FREQ     33330000
51 #endif
52
53 #elif defined(CONFIG_CLKIN_66MHZ)
54 #ifdef CONFIG_PCISLAVE
55 #define CONFIG_83XX_PCICLK      66000000 /* in HZ */
56 #else
57 #define CONFIG_83XX_CLKIN       66000000 /* in Hz */
58 #endif
59
60 #ifndef CONFIG_SYS_CLK_FREQ
61 #define CONFIG_SYS_CLK_FREQ     66000000
62 #endif
63 #else
64 #error Unknown oscillator frequency.
65 #endif
66
67 /*
68  * Hardware Reset Configuration Word
69  */
70 #ifdef CONFIG_CLKIN_33MHZ
71 #define CONFIG_SYS_HRCW_LOW (\
72         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
73         HRCWL_DDR_TO_SCB_CLK_1X1 |\
74         HRCWL_CSB_TO_CLKIN_8X1 |\
75         HRCWL_VCO_1X2 |\
76         HRCWL_CE_PLL_VCO_DIV_4 |\
77         HRCWL_CE_PLL_DIV_1X1 |\
78         HRCWL_CE_TO_PLL_1X15 |\
79         HRCWL_CORE_TO_CSB_2X1)
80 #elif defined(CONFIG_CLKIN_66MHZ)
81 #define CONFIG_SYS_HRCW_LOW (\
82         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
83         HRCWL_DDR_TO_SCB_CLK_1X1 |\
84         HRCWL_CSB_TO_CLKIN_4X1 |\
85         HRCWL_VCO_1X2 |\
86         HRCWL_CE_PLL_VCO_DIV_4 |\
87         HRCWL_CE_PLL_DIV_1X1 |\
88         HRCWL_CE_TO_PLL_1X6 |\
89         HRCWL_CORE_TO_CSB_2X1)
90 #endif
91
92 #ifdef CONFIG_PCISLAVE
93 #define CONFIG_SYS_HRCW_HIGH (\
94         HRCWH_PCI_AGENT |\
95         HRCWH_PCI1_ARBITER_DISABLE |\
96         HRCWH_PCICKDRV_DISABLE |\
97         HRCWH_CORE_ENABLE |\
98         HRCWH_FROM_0XFFF00100 |\
99         HRCWH_BOOTSEQ_DISABLE |\
100         HRCWH_SW_WATCHDOG_DISABLE |\
101         HRCWH_ROM_LOC_LOCAL_16BIT)
102 #else
103 #define CONFIG_SYS_HRCW_HIGH (\
104         HRCWH_PCI_HOST |\
105         HRCWH_PCI1_ARBITER_ENABLE |\
106         HRCWH_PCICKDRV_ENABLE |\
107         HRCWH_CORE_ENABLE |\
108         HRCWH_FROM_0X00000100 |\
109         HRCWH_BOOTSEQ_DISABLE |\
110         HRCWH_SW_WATCHDOG_DISABLE |\
111         HRCWH_ROM_LOC_LOCAL_16BIT)
112 #endif
113
114 /*
115  * System IO Config
116  */
117 #define CONFIG_SYS_SICRH                0x00000000
118 #define CONFIG_SYS_SICRL                0x40000000
119
120 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
121 #define CONFIG_BOARD_EARLY_INIT_R
122
123 /*
124  * IMMR new address
125  */
126 #define CONFIG_SYS_IMMR         0xE0000000
127
128 /*
129  * DDR Setup
130  */
131 #define CONFIG_SYS_DDR_BASE     0x00000000 /* DDR is system memory */
132 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
133                                 /* + 256M */
134 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000)
135 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
136 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
137                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
138
139 #define CONFIG_SYS_83XX_DDR_USES_CS0
140
141 #define CONFIG_DDR_ECC          /* support DDR ECC function */
142 #define CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
143
144 /*
145  * DDRCDR - DDR Control Driver Register
146  */
147 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
148
149 #define CONFIG_SPD_EEPROM       /* Use SPD EEPROM for DDR setup */
150 #if defined(CONFIG_SPD_EEPROM)
151 /*
152  * Determine DDR configuration from I2C interface.
153  */
154 #define SPD_EEPROM_ADDRESS      0x52 /* DDR SODIMM */
155 #else
156 /*
157  * Manually set up DDR parameters
158  */
159 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
160 #if defined(CONFIG_DDR_II)
161 #define CONFIG_SYS_DDRCDR               0x80080001
162 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
163 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80330102
164 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
165 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
166 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
167 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
168 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
169 #define CONFIG_SYS_DDR_MODE             0x47d00432
170 #define CONFIG_SYS_DDR_MODE2            0x8000c000
171 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
172 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
173 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
174 #else
175 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
176                                         | CSCONFIG_ROW_BIT_13 \
177                                         | CSCONFIG_COL_BIT_9)
178 #define CONFIG_SYS_DDR_CS1_CONFIG       CONFIG_SYS_DDR_CS0_CONFIG
179 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
180 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
181 #define CONFIG_SYS_DDR_CONTROL  0x42008000 /* Self refresh,2T timing */
182 #define CONFIG_SYS_DDR_MODE     0x20000162 /* DLL,normal,seq,4/2.5 */
183 #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
184 #endif
185 #endif
186
187 /*
188  * Memory test
189  */
190 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
191 #define CONFIG_SYS_MEMTEST_START        0x00000000 /* memtest region */
192 #define CONFIG_SYS_MEMTEST_END          0x00100000
193
194 /*
195  * The reserved memory
196  */
197
198 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
199
200 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_RAMBOOT
202 #else
203 #undef  CONFIG_SYS_RAMBOOT
204 #endif
205
206 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
207 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
208 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
209
210 /*
211  * Initial RAM Base Address Setup
212  */
213 #define CONFIG_SYS_INIT_RAM_LOCK        1
214 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
215 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
216 #define CONFIG_SYS_GBL_DATA_OFFSET      \
217                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218
219 /*
220  * Local Bus Configuration & Clock Setup
221  */
222 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
223 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
224 #define CONFIG_SYS_LBC_LBCR     0x00000000
225
226 /*
227  * FLASH on the Local Bus
228  */
229 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
230 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
231 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
232 #define CONFIG_SYS_FLASH_SIZE           32 /* max FLASH size is 32M */
233 #define CONFIG_SYS_FLASH_PROTECTION     1 /* Use h/w Flash protection. */
234 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
235
236                                         /* Window base at flash base */
237 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
238 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
239
240 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
241                                 | BR_PS_16      /* 16 bit port */ \
242                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
243                                 | BR_V)         /* valid */
244 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
245                                 | OR_GPCM_XAM \
246                                 | OR_GPCM_CSNT \
247                                 | OR_GPCM_ACS_DIV2 \
248                                 | OR_GPCM_XACS \
249                                 | OR_GPCM_SCY_15 \
250                                 | OR_GPCM_TRLX_SET \
251                                 | OR_GPCM_EHTR_SET \
252                                 | OR_GPCM_EAD)
253
254 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
255 #define CONFIG_SYS_MAX_FLASH_SECT       256 /* max sectors per device */
256
257 #undef  CONFIG_SYS_FLASH_CHECKSUM
258
259 /*
260  * BCSR on the Local Bus
261  */
262 #define CONFIG_SYS_BCSR                 0xF8000000
263                                         /* Access window base at BCSR base */
264 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
265 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
266
267 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_BCSR \
268                                 | BR_PS_8 \
269                                 | BR_MS_GPCM \
270                                 | BR_V)
271 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_32KB \
272                                 | OR_GPCM_XAM \
273                                 | OR_GPCM_CSNT \
274                                 | OR_GPCM_XACS \
275                                 | OR_GPCM_SCY_15 \
276                                 | OR_GPCM_TRLX_SET \
277                                 | OR_GPCM_EHTR_SET \
278                                 | OR_GPCM_EAD)
279                                 /* 0xFFFFE9F7 */
280
281 /*
282  * SDRAM on the Local Bus
283  */
284 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* SDRAM base address */
285 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
286
287 #define CONFIG_SYS_LB_SDRAM             /* if board has SRDAM on local bus */
288
289 #ifdef CONFIG_SYS_LB_SDRAM
290 #define CONFIG_SYS_LBLAWBAR2            0
291 #define CONFIG_SYS_LBLAWAR2             (LBLAWAR_EN | LBLAWAR_64MB)
292
293 /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
294 /*
295  * Base Register 2 and Option Register 2 configure SDRAM.
296  *
297  * For BR2, need:
298  *    Base address = BR[0:16] = dynamic
299  *    port size = 32-bits = BR2[19:20] = 11
300  *    no parity checking = BR2[21:22] = 00
301  *    SDRAM for MSEL = BR2[24:26] = 011
302  *    Valid = BR[31] = 1
303  *
304  * 0    4    8    12   16   20   24   28
305  * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
306  */
307
308 /* Port size=32bit, MSEL=DRAM */
309 #define CONFIG_SYS_BR2  (BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
310
311 /*
312  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
313  *
314  * For OR2, need:
315  *    64MB mask for AM, OR2[0:7] = 1111 1100
316  *                 XAM, OR2[17:18] = 11
317  *    9 columns OR2[19-21] = 010
318  *    13 rows   OR2[23-25] = 100
319  *    EAD set for extra time OR[31] = 1
320  *
321  * 0    4    8    12   16   20   24   28
322  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
323  */
324
325 #define CONFIG_SYS_OR2  (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
326                         | OR_SDRAM_XAM \
327                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
328                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
329                         | OR_SDRAM_EAD)
330                         /* 0xFC006901 */
331
332                                 /* LB sdram refresh timer, about 6us */
333 #define CONFIG_SYS_LBC_LSRT     0x32000000
334                                 /* LB refresh timer prescal, 266MHz/32 */
335 #define CONFIG_SYS_LBC_MRTPR    0x20000000
336
337 #define CONFIG_SYS_LBC_LSDMR_COMMON     0x0063b723
338
339 /*
340  * SDRAM Controller configuration sequence.
341  */
342 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
343 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
344 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
345 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
346 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
347
348 #endif
349
350 /*
351  * Windows to access Platform I/O Boards (PIB) via local bus
352  */
353 #define CONFIG_SYS_PIB_BASE             0xF8008000
354 #define CONFIG_SYS_PIB_WINDOW_SIZE      (32 * 1024)
355
356 /* [RFC] This LBLAW only covers the 2nd window (CS5) */
357 #define CONFIG_SYS_LBLAWBAR3_PRELIM     \
358                         CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
359 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
360
361 /*
362  * CS4 on Local Bus, to PIB
363  */
364                                 /* CS4 base address at 0xf8008000 */
365 #define CONFIG_SYS_BR4_PRELIM   (CONFIG_SYS_PIB_BASE \
366                                 | BR_PS_8 \
367                                 | BR_MS_GPCM \
368                                 | BR_V)
369                                 /* 0xF8008801 */
370 #define CONFIG_SYS_OR4_PRELIM   (OR_AM_32KB \
371                                 | OR_GPCM_XAM \
372                                 | OR_GPCM_CSNT \
373                                 | OR_GPCM_XACS \
374                                 | OR_GPCM_SCY_15 \
375                                 | OR_GPCM_TRLX_SET \
376                                 | OR_GPCM_EHTR_SET \
377                                 | OR_GPCM_EAD)
378                                 /* 0xffffe9f7 */
379
380 /*
381  * CS5 on Local Bus, to PIB
382  */
383                                 /* CS5 base address at 0xf8010000 */
384 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_PIB_BASE + \
385                                                 CONFIG_SYS_PIB_WINDOW_SIZE) \
386                                 | BR_PS_8 \
387                                 | BR_MS_GPCM \
388                                 | BR_V)
389                                 /* 0xF8010801 */
390 #define CONFIG_SYS_OR5_PRELIM   (CONFIG_SYS_PIB_BASE \
391                                 | OR_GPCM_XAM \
392                                 | OR_GPCM_CSNT \
393                                 | OR_GPCM_XACS \
394                                 | OR_GPCM_SCY_15 \
395                                 | OR_GPCM_TRLX_SET \
396                                 | OR_GPCM_EHTR_SET \
397                                 | OR_GPCM_EAD)
398                                 /* 0xffffe9f7 */
399
400 /*
401  * Serial Port
402  */
403 #define CONFIG_CONS_INDEX       1
404 #define CONFIG_SYS_NS16550
405 #define CONFIG_SYS_NS16550_SERIAL
406 #define CONFIG_SYS_NS16550_REG_SIZE     1
407 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
408
409 #define CONFIG_SYS_BAUDRATE_TABLE  \
410                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
411
412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
414
415 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
416 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
417 /* Use the HUSH parser */
418 #define CONFIG_SYS_HUSH_PARSER
419
420 /* pass open firmware flat tree */
421 #define CONFIG_OF_LIBFDT        1
422 #define CONFIG_OF_BOARD_SETUP   1
423 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
424
425 /* I2C */
426 #define CONFIG_HARD_I2C         /* I2C with hardware support */
427 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
428 #define CONFIG_FSL_I2C
429 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
430 #define CONFIG_SYS_I2C_SLAVE    0x7F
431 #define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
432 #define CONFIG_SYS_I2C_OFFSET   0x3000
433 #define CONFIG_SYS_I2C2_OFFSET 0x3100
434
435 /*
436  * Config on-board RTC
437  */
438 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
439 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
440
441 /*
442  * General PCI
443  * Addresses are mapped 1-1.
444  */
445 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
446 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
447 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000 /* 256M */
448 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
449 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
450 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000 /* 256M */
451 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
452 #define CONFIG_SYS_PCI1_IO_PHYS         0xE0300000
453 #define CONFIG_SYS_PCI1_IO_SIZE         0x100000 /* 1M */
454
455 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
456 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
457 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
458
459
460 #ifdef CONFIG_PCI
461
462 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
463 #define CONFIG_83XX_PCI_STREAMING
464
465 #undef CONFIG_EEPRO100
466 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
467 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
468
469 #endif  /* CONFIG_PCI */
470
471
472 #define CONFIG_HWCONFIG         1
473
474 /*
475  * QE UEC ethernet configuration
476  */
477 #define CONFIG_UEC_ETH
478 #define CONFIG_ETHPRIME         "UEC0"
479 #define CONFIG_PHY_MODE_NEED_CHANGE
480
481 #define CONFIG_UEC_ETH1         /* GETH1 */
482
483 #ifdef CONFIG_UEC_ETH1
484 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
485 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE
486 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK9
487 #define CONFIG_SYS_UEC1_ETH_TYPE        GIGA_ETH
488 #define CONFIG_SYS_UEC1_PHY_ADDR        0
489 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
490 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
491 #endif
492
493 #define CONFIG_UEC_ETH2         /* GETH2 */
494
495 #ifdef CONFIG_UEC_ETH2
496 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
497 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK_NONE
498 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK4
499 #define CONFIG_SYS_UEC2_ETH_TYPE        GIGA_ETH
500 #define CONFIG_SYS_UEC2_PHY_ADDR        1
501 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
502 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
503 #endif
504
505 /*
506  * Environment
507  */
508
509 #ifndef CONFIG_SYS_RAMBOOT
510         #define CONFIG_ENV_IS_IN_FLASH  1
511         #define CONFIG_ENV_ADDR         \
512                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
513         #define CONFIG_ENV_SECT_SIZE    0x20000
514         #define CONFIG_ENV_SIZE         0x2000
515 #else
516         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
517         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
518         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
519         #define CONFIG_ENV_SIZE         0x2000
520 #endif
521
522 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
523 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
524
525 /*
526  * BOOTP options
527  */
528 #define CONFIG_BOOTP_BOOTFILESIZE
529 #define CONFIG_BOOTP_BOOTPATH
530 #define CONFIG_BOOTP_GATEWAY
531 #define CONFIG_BOOTP_HOSTNAME
532
533
534 /*
535  * Command line configuration.
536  */
537 #include <config_cmd_default.h>
538
539 #define CONFIG_CMD_PING
540 #define CONFIG_CMD_I2C
541 #define CONFIG_CMD_ASKENV
542 #define CONFIG_CMD_SDRAM
543
544 #if defined(CONFIG_PCI)
545     #define CONFIG_CMD_PCI
546 #endif
547
548 #if defined(CONFIG_SYS_RAMBOOT)
549     #undef CONFIG_CMD_SAVEENV
550     #undef CONFIG_CMD_LOADS
551 #endif
552
553
554 #undef CONFIG_WATCHDOG          /* watchdog disabled */
555
556 /*
557  * Miscellaneous configurable options
558  */
559 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
560 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
561 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt */
562
563 #if defined(CONFIG_CMD_KGDB)
564         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
565 #else
566         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
567 #endif
568
569                                 /* Print Buffer Size */
570 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
571 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
572                                 /* Boot Argument Buffer Size */
573 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
574 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
575
576 /*
577  * For booting Linux, the board info and command line data
578  * have to be in the first 256 MB of memory, since this is
579  * the maximum mapped by the Linux kernel during initialization.
580  */
581 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
582
583 /*
584  * Core HID Setup
585  */
586 #define CONFIG_SYS_HID0_INIT    0x000000000
587 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
588                                  HID0_ENABLE_INSTRUCTION_CACHE)
589 #define CONFIG_SYS_HID2         HID2_HBE
590
591 /*
592  * MMU Setup
593  */
594
595 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
596 #define CONFIG_BAT_RW
597
598 /* DDR/LBC SDRAM: cacheable */
599 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
600                                 | BATL_PP_RW \
601                                 | BATL_MEMCOHERENCE)
602 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
603                                 | BATU_BL_256M \
604                                 | BATU_VS \
605                                 | BATU_VP)
606 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
607 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
608
609 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
610 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
611                                 | BATL_PP_RW \
612                                 | BATL_CACHEINHIBIT \
613                                 | BATL_GUARDEDSTORAGE)
614 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
615                                 | BATU_BL_4M \
616                                 | BATU_VS \
617                                 | BATU_VP)
618 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
619 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
620
621 /* BCSR: cache-inhibit and guarded */
622 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_BCSR \
623                                 | BATL_PP_RW \
624                                 | BATL_CACHEINHIBIT \
625                                 | BATL_GUARDEDSTORAGE)
626 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_BCSR \
627                                 | BATU_BL_128K \
628                                 | BATU_VS \
629                                 | BATU_VP)
630 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
631 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
632
633 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
634 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE \
635                                 | BATL_PP_RW \
636                                 | BATL_MEMCOHERENCE)
637 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE \
638                                 | BATU_BL_32M \
639                                 | BATU_VS \
640                                 | BATU_VP)
641 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE \
642                                 | BATL_PP_RW \
643                                 | BATL_CACHEINHIBIT \
644                                 | BATL_GUARDEDSTORAGE)
645 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
646
647 /* DDR/LBC SDRAM next 256M: cacheable */
648 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_SDRAM_BASE2 \
649                                 | BATL_PP_RW \
650                                 | BATL_MEMCOHERENCE)
651 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_SDRAM_BASE2 \
652                                 | BATU_BL_256M \
653                                 | BATU_VS \
654                                 | BATU_VP)
655 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
656 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
657
658 /* Stack in dcache: cacheable, no memory coherence */
659 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
660 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_INIT_RAM_ADDR \
661                                 | BATU_BL_128K \
662                                 | BATU_VS \
663                                 | BATU_VP)
664 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
665 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
666
667 #ifdef CONFIG_PCI
668 /* PCI MEM space: cacheable */
669 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MEM_PHYS \
670                                 | BATL_PP_RW \
671                                 | BATL_MEMCOHERENCE)
672 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MEM_PHYS \
673                                 | BATU_BL_256M \
674                                 | BATU_VS \
675                                 | BATU_VP)
676 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
677 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
678 /* PCI MMIO space: cache-inhibit and guarded */
679 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_PCI1_MMIO_PHYS \
680                                 | BATL_PP_RW \
681                                 | BATL_CACHEINHIBIT \
682                                 | BATL_GUARDEDSTORAGE)
683 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_PCI1_MMIO_PHYS \
684                                 | BATU_BL_256M \
685                                 | BATU_VS \
686                                 | BATU_VP)
687 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
688 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
689 #else
690 #define CONFIG_SYS_IBAT6L       (0)
691 #define CONFIG_SYS_IBAT6U       (0)
692 #define CONFIG_SYS_IBAT7L       (0)
693 #define CONFIG_SYS_IBAT7U       (0)
694 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
695 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
696 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
697 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
698 #endif
699
700 #if defined(CONFIG_CMD_KGDB)
701 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
702 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
703 #endif
704
705 /*
706  * Environment Configuration
707  */
708
709 #define CONFIG_ENV_OVERWRITE
710
711 #if defined(CONFIG_UEC_ETH)
712 #define CONFIG_HAS_ETH0
713 #define CONFIG_HAS_ETH1
714 #endif
715
716 #define CONFIG_BAUDRATE 115200
717
718 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
719
720 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
721 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
722
723 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
724         "netdev=eth0\0"                                                 \
725         "consoledev=ttyS0\0"                                            \
726         "ramdiskaddr=1000000\0"                                         \
727         "ramdiskfile=ramfs.83xx\0"                                      \
728         "fdtaddr=780000\0"                                              \
729         "fdtfile=mpc836x_mds.dtb\0"                                     \
730         ""
731
732 #define CONFIG_NFSBOOTCOMMAND                                           \
733         "setenv bootargs root=/dev/nfs rw "                             \
734                 "nfsroot=$serverip:$rootpath "                          \
735                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
736                                                         "$netdev:off "  \
737                 "console=$consoledev,$baudrate $othbootargs;"           \
738         "tftp $loadaddr $bootfile;"                                     \
739         "tftp $fdtaddr $fdtfile;"                                       \
740         "bootm $loadaddr - $fdtaddr"
741
742 #define CONFIG_RAMBOOTCOMMAND                                           \
743         "setenv bootargs root=/dev/ram rw "                             \
744                 "console=$consoledev,$baudrate $othbootargs;"           \
745         "tftp $ramdiskaddr $ramdiskfile;"                               \
746         "tftp $loadaddr $bootfile;"                                     \
747         "tftp $fdtaddr $fdtfile;"                                       \
748         "bootm $loadaddr $ramdiskaddr $fdtaddr"
749
750
751 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
752
753 #endif  /* __CONFIG_H */