include/configs/MPC8349ITX.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   9
  10  Memory map:
  11
  12  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  13  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  14  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  15  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  16  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  17  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  18  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  19  0xF001_0000-0xF001_FFFF Local bus expansion slot
  20  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  21  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  22  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  23
  24  I2C address list:
  25                                                 Align.  Board
  26  Bus    Addr    Part No.        Description     Length  Location
  27  ----------------------------------------------------------------
  28  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  29
  30  I2C1   0x20    PCF8574         I2C Expander    0       U8
  31  I2C1   0x21    PCF8574         I2C Expander    0       U10
  32  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  33  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  34  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  35  I2C1   0x68    DS1339          RTC             1       U68
  36
  37  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  38 */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  44 #define CONFIG_SYS_LOWBOOT
  45 #endif
  46
  47 /*
  48  * High Level Configuration Options
  49  */
  50 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  51 #define CONFIG_MPC8349          /* MPC8349 specific */
  52
  53 #ifndef CONFIG_SYS_TEXT_BASE
  54 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
  55 #endif
  56
  57 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  58
  59 #define CONFIG_MISC_INIT_F
  60 #define CONFIG_MISC_INIT_R
  61
  62 /*
  63  * On-board devices
  64  */
  65
  66 #ifdef CONFIG_MPC8349ITX
  67 /* The CF card interface on the back of the board */
  68 #define CONFIG_COMPACT_FLASH
  69 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  70 #define CONFIG_SATA_SIL3114     /* SIL3114 SATA controller */
  71 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  72 #endif
  73
  74 #define CONFIG_PCI
  75 #define CONFIG_RTC_DS1337
  76 #define CONFIG_SYS_I2C
  77 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  78
  79 /*
  80  * Device configurations
  81  */
  82
  83 /* I2C */
  84 #ifdef CONFIG_SYS_I2C
  85 #define CONFIG_SYS_I2C_FSL
  86 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  87 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  88 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  89 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  90 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  91 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  92
  93 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  94 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  95
  96 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  97 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  98 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  99 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
 100 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
 101 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
 102 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
 103
 104 /* Don't probe these addresses: */
 105 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
 106                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 107                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 108                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 109 /* Bit definitions for the 8574[A] I2C expander */
 110                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 111 #define I2C_8574_REVISION       0x03
 112 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 113 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 114 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 115 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 116
 117 #endif
 118
 119 /* Compact Flash */
 120 #ifdef CONFIG_COMPACT_FLASH
 121
 122 #define CONFIG_SYS_IDE_MAXBUS           1
 123 #define CONFIG_SYS_IDE_MAXDEVICE        1
 124
 125 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 126 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 127 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 128 #define CONFIG_SYS_ATA_REG_OFFSET       0
 129 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 130 #define CONFIG_SYS_ATA_STRIDE           2
 131
 132 /* If a CF card is not inserted, time out quickly */
 133 #define ATA_RESET_TIME  1
 134
 135 #endif
 136
 137 /*
 138  * SATA
 139  */
 140 #ifdef CONFIG_SATA_SIL3114
 141
 142 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 143 #define CONFIG_LIBATA
 144 #define CONFIG_LBA48
 145
 146 #endif
 147
 148 #ifdef CONFIG_SYS_USB_HOST
 149 /*
 150  * Support USB
 151  */
 152 #define CONFIG_USB_EHCI
 153 #define CONFIG_USB_EHCI_FSL
 154
 155 /* Current USB implementation supports the only USB controller,
 156  * so we have to choose between the MPH or the DR ones */
 157 #if 1
 158 #define CONFIG_HAS_FSL_MPH_USB
 159 #else
 160 #define CONFIG_HAS_FSL_DR_USB
 161 #endif
 162
 163 #endif
 164
 165 /*
 166  * DDR Setup
 167  */
 168 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 169 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 170 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 171 #define CONFIG_SYS_83XX_DDR_USES_CS0
 172 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 173 #define CONFIG_SYS_MEMTEST_END          0x2000
 174
 175 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 176                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 177
 178 #define CONFIG_VERY_BIG_RAM
 179 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 180
 181 #ifdef CONFIG_SYS_I2C
 182 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 183 #endif
 184
 185 /* No SPD? Then manually set up DDR parameters */
 186 #ifndef CONFIG_SPD_EEPROM
 187     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 188     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 189                                         | CSCONFIG_ROW_BIT_13 \
 190                                         | CSCONFIG_COL_BIT_10)
 191
 192     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 193     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 194 #endif
 195
 196 /*
 197  *Flash on the Local Bus
 198  */
 199
 200 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 201 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 202 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 203 #define CONFIG_SYS_FLASH_EMPTY_INFO
 204 /* 127 64KB sectors + 8 8KB sectors per device */
 205 #define CONFIG_SYS_MAX_FLASH_SECT       135
 206 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 207 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 208 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 209
 210 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 211 boards, we say we have two, but don't display a message if we find only one. */
 212 #define CONFIG_SYS_FLASH_QUIET_TEST
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 214 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 215                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 216 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 217 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 218
 219 /* Vitesse 7385 */
 220
 221 #ifdef CONFIG_VSC7385_ENET
 222
 223 #define CONFIG_TSEC2
 224
 225 /* The flash address and size of the VSC7385 firmware image */
 226 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 227 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 228
 229 #endif
 230
 231 /*
 232  * BRx, ORx, LBLAWBARx, and LBLAWARx
 233  */
 234
 235 /* Flash */
 236
 237 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 238                                 | BR_PS_16 \
 239                                 | BR_MS_GPCM \
 240                                 | BR_V)
 241 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 242                                 | OR_UPM_XAM \
 243                                 | OR_GPCM_CSNT \
 244                                 | OR_GPCM_ACS_DIV2 \
 245                                 | OR_GPCM_XACS \
 246                                 | OR_GPCM_SCY_15 \
 247                                 | OR_GPCM_TRLX_SET \
 248                                 | OR_GPCM_EHTR_SET \
 249                                 | OR_GPCM_EAD)
 250 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 251 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 252
 253 /* Vitesse 7385 */
 254
 255 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 256
 257 #ifdef CONFIG_VSC7385_ENET
 258
 259 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 260                                 | BR_PS_8 \
 261                                 | BR_MS_GPCM \
 262                                 | BR_V)
 263 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 264                                 | OR_GPCM_CSNT \
 265                                 | OR_GPCM_XACS \
 266                                 | OR_GPCM_SCY_15 \
 267                                 | OR_GPCM_SETA \
 268                                 | OR_GPCM_TRLX_SET \
 269                                 | OR_GPCM_EHTR_SET \
 270                                 | OR_GPCM_EAD)
 271
 272 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 273 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 274
 275 #endif
 276
 277 /* LED */
 278
 279 #define CONFIG_SYS_LED_BASE     0xF9000000
 280 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 281                                 | BR_PS_8 \
 282                                 | BR_MS_GPCM \
 283                                 | BR_V)
 284 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 285                                 | OR_GPCM_CSNT \
 286                                 | OR_GPCM_ACS_DIV2 \
 287                                 | OR_GPCM_XACS \
 288                                 | OR_GPCM_SCY_9 \
 289                                 | OR_GPCM_TRLX_SET \
 290                                 | OR_GPCM_EHTR_SET \
 291                                 | OR_GPCM_EAD)
 292
 293 /* Compact Flash */
 294
 295 #ifdef CONFIG_COMPACT_FLASH
 296
 297 #define CONFIG_SYS_CF_BASE      0xF0000000
 298
 299 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 300                                 | BR_PS_16 \
 301                                 | BR_MS_UPMA \
 302                                 | BR_V)
 303 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 304
 305 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 306 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 307
 308 #endif
 309
 310 /*
 311  * U-Boot memory configuration
 312  */
 313 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 314
 315 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 316 #define CONFIG_SYS_RAMBOOT
 317 #else
 318 #undef  CONFIG_SYS_RAMBOOT
 319 #endif
 320
 321 #define CONFIG_SYS_INIT_RAM_LOCK
 322 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 323 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 324
 325 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 326                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 327 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 328
 329 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 330 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 331 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 332
 333 /*
 334  * Local Bus LCRR and LBCR regs
 335  *    LCRR:  DLL bypass, Clock divider is 4
 336  * External Local Bus rate is
 337  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 338  */
 339 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 340 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 341 #define CONFIG_SYS_LBC_LBCR     0x00000000
 342
 343                                 /* LB sdram refresh timer, about 6us */
 344 #define CONFIG_SYS_LBC_LSRT     0x32000000
 345                                 /* LB refresh timer prescal, 266MHz/32*/
 346 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 347
 348 /*
 349  * Serial Port
 350  */
 351 #define CONFIG_CONS_INDEX       1
 352 #define CONFIG_SYS_NS16550_SERIAL
 353 #define CONFIG_SYS_NS16550_REG_SIZE     1
 354 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 355
 356 #define CONFIG_SYS_BAUDRATE_TABLE  \
 357                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 358
 359 #define CONFIG_CONSOLE          ttyS0
 360 #define CONFIG_BAUDRATE         115200
 361
 362 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 363 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 364
 365 /*
 366  * PCI
 367  */
 368 #ifdef CONFIG_PCI
 369 #define CONFIG_PCI_INDIRECT_BRIDGE
 370
 371 #define CONFIG_MPC83XX_PCI2
 372
 373 /*
 374  * General PCI
 375  * Addresses are mapped 1-1.
 376  */
 377 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 378 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 379 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 380 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 381                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 382 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 383 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 384 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 385 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 386 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 387
 388 #ifdef CONFIG_MPC83XX_PCI2
 389 #define CONFIG_SYS_PCI2_MEM_BASE        \
 390                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 391 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 392 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 393 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 394                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 395 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 396 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 397 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 398 #define CONFIG_SYS_PCI2_IO_PHYS         \
 399                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 400 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 401 #endif
 402
 403 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 404
 405 #ifndef CONFIG_PCI_PNP
 406     #define PCI_ENET0_IOADDR    0x00000000
 407     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 408     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 409 #endif
 410
 411 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 412
 413 #endif
 414
 415 #define CONFIG_PCI_66M
 416 #ifdef CONFIG_PCI_66M
 417 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 418 #else
 419 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 420 #endif
 421
 422 /* TSEC */
 423
 424 #ifdef CONFIG_TSEC_ENET
 425
 426 #define CONFIG_MII
 427 #define CONFIG_PHY_GIGE         /* In case CONFIG_CMD_MII is specified */
 428
 429 #define CONFIG_TSEC1
 430
 431 #ifdef CONFIG_TSEC1
 432 #define CONFIG_HAS_ETH0
 433 #define CONFIG_TSEC1_NAME  "TSEC0"
 434 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 435 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 436 #define TSEC1_PHYIDX            0
 437 #define TSEC1_FLAGS             TSEC_GIGABIT
 438 #endif
 439
 440 #ifdef CONFIG_TSEC2
 441 #define CONFIG_HAS_ETH1
 442 #define CONFIG_TSEC2_NAME  "TSEC1"
 443 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 444
 445 #define TSEC2_PHY_ADDR          4
 446 #define TSEC2_PHYIDX            0
 447 #define TSEC2_FLAGS             TSEC_GIGABIT
 448 #endif
 449
 450 #define CONFIG_ETHPRIME         "Freescale TSEC"
 451
 452 #endif
 453
 454 /*
 455  * Environment
 456  */
 457 #define CONFIG_ENV_OVERWRITE
 458
 459 #ifndef CONFIG_SYS_RAMBOOT
 460   #define CONFIG_ENV_IS_IN_FLASH
 461   #define CONFIG_ENV_ADDR       \
 462                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 463   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 464   #define CONFIG_ENV_SIZE       0x2000
 465 #else
 466   #define CONFIG_SYS_NO_FLASH   /* Flash is not usable now */
 467   #undef  CONFIG_FLASH_CFI_DRIVER
 468   #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
 469   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 470   #define CONFIG_ENV_SIZE       0x2000
 471 #endif
 472
 473 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 474 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 475
 476 /*
 477  * BOOTP options
 478  */
 479 #define CONFIG_BOOTP_BOOTFILESIZE
 480 #define CONFIG_BOOTP_BOOTPATH
 481 #define CONFIG_BOOTP_GATEWAY
 482 #define CONFIG_BOOTP_HOSTNAME
 483
 484 /*
 485  * Command line configuration.
 486  */
 487 #define CONFIG_CMD_DATE
 488 #define CONFIG_CMD_IRQ
 489 #define CONFIG_CMD_SDRAM
 490
 491 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 492                                 || defined(CONFIG_USB_STORAGE)
 493         #define CONFIG_DOS_PARTITION
 494         #define CONFIG_SUPPORT_VFAT
 495 #endif
 496
 497 #ifdef CONFIG_COMPACT_FLASH
 498         #define CONFIG_CMD_IDE
 499 #endif
 500
 501 #ifdef CONFIG_SATA_SIL3114
 502         #define CONFIG_CMD_SATA
 503 #endif
 504
 505 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
 506 #endif
 507
 508 #ifdef CONFIG_PCI
 509         #define CONFIG_CMD_PCI
 510 #endif
 511
 512 /* Watchdog */
 513 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 514
 515 /*
 516  * Miscellaneous configurable options
 517  */
 518 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 519 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 520 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 521
 522 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 523 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 524
 525 #if defined(CONFIG_CMD_KGDB)
 526         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 527 #else
 528         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 529 #endif
 530
 531                                 /* Print Buffer Size */
 532 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 533 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 534                                 /* Boot Argument Buffer Size */
 535 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 536
 537 /*
 538  * For booting Linux, the board info and command line data
 539  * have to be in the first 256 MB of memory, since this is
 540  * the maximum mapped by the Linux kernel during initialization.
 541  */
 542                                 /* Initial Memory map for Linux*/
 543 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 544 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 545
 546 #define CONFIG_SYS_HRCW_LOW (\
 547         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 548         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 549         HRCWL_CSB_TO_CLKIN_4X1 |\
 550         HRCWL_VCO_1X2 |\
 551         HRCWL_CORE_TO_CSB_2X1)
 552
 553 #ifdef CONFIG_SYS_LOWBOOT
 554 #define CONFIG_SYS_HRCW_HIGH (\
 555         HRCWH_PCI_HOST |\
 556         HRCWH_32_BIT_PCI |\
 557         HRCWH_PCI1_ARBITER_ENABLE |\
 558         HRCWH_PCI2_ARBITER_ENABLE |\
 559         HRCWH_CORE_ENABLE |\
 560         HRCWH_FROM_0X00000100 |\
 561         HRCWH_BOOTSEQ_DISABLE |\
 562         HRCWH_SW_WATCHDOG_DISABLE |\
 563         HRCWH_ROM_LOC_LOCAL_16BIT |\
 564         HRCWH_TSEC1M_IN_GMII |\
 565         HRCWH_TSEC2M_IN_GMII)
 566 #else
 567 #define CONFIG_SYS_HRCW_HIGH (\
 568         HRCWH_PCI_HOST |\
 569         HRCWH_32_BIT_PCI |\
 570         HRCWH_PCI1_ARBITER_ENABLE |\
 571         HRCWH_PCI2_ARBITER_ENABLE |\
 572         HRCWH_CORE_ENABLE |\
 573         HRCWH_FROM_0XFFF00100 |\
 574         HRCWH_BOOTSEQ_DISABLE |\
 575         HRCWH_SW_WATCHDOG_DISABLE |\
 576         HRCWH_ROM_LOC_LOCAL_16BIT |\
 577         HRCWH_TSEC1M_IN_GMII |\
 578         HRCWH_TSEC2M_IN_GMII)
 579 #endif
 580
 581 /*
 582  * System performance
 583  */
 584 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 585 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 586 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 587 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 588 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 589 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 590 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 591 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 592
 593 /*
 594  * System IO Config
 595  */
 596 /* Needed for gigabit to work on TSEC 1 */
 597 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 598                                 /* USB DR as device + USB MPH as host */
 599 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 600
 601 #define CONFIG_SYS_HID0_INIT    0x00000000
 602 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 603
 604 #define CONFIG_SYS_HID2 HID2_HBE
 605 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 606
 607 /* DDR  */
 608 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 609                                 | BATL_PP_RW \
 610                                 | BATL_MEMCOHERENCE)
 611 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 612                                 | BATU_BL_256M \
 613                                 | BATU_VS \
 614                                 | BATU_VP)
 615
 616 /* PCI  */
 617 #ifdef CONFIG_PCI
 618 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 619                                 | BATL_PP_RW \
 620                                 | BATL_MEMCOHERENCE)
 621 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 622                                 | BATU_BL_256M \
 623                                 | BATU_VS \
 624                                 | BATU_VP)
 625 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 626                                 | BATL_PP_RW \
 627                                 | BATL_CACHEINHIBIT \
 628                                 | BATL_GUARDEDSTORAGE)
 629 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 630                                 | BATU_BL_256M \
 631                                 | BATU_VS \
 632                                 | BATU_VP)
 633 #else
 634 #define CONFIG_SYS_IBAT1L       0
 635 #define CONFIG_SYS_IBAT1U       0
 636 #define CONFIG_SYS_IBAT2L       0
 637 #define CONFIG_SYS_IBAT2U       0
 638 #endif
 639
 640 #ifdef CONFIG_MPC83XX_PCI2
 641 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 642                                 | BATL_PP_RW \
 643                                 | BATL_MEMCOHERENCE)
 644 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 645                                 | BATU_BL_256M \
 646                                 | BATU_VS \
 647                                 | BATU_VP)
 648 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 649                                 | BATL_PP_RW \
 650                                 | BATL_CACHEINHIBIT \
 651                                 | BATL_GUARDEDSTORAGE)
 652 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 653                                 | BATU_BL_256M \
 654                                 | BATU_VS \
 655                                 | BATU_VP)
 656 #else
 657 #define CONFIG_SYS_IBAT3L       0
 658 #define CONFIG_SYS_IBAT3U       0
 659 #define CONFIG_SYS_IBAT4L       0
 660 #define CONFIG_SYS_IBAT4U       0
 661 #endif
 662
 663 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 664 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 665                                 | BATL_PP_RW \
 666                                 | BATL_CACHEINHIBIT \
 667                                 | BATL_GUARDEDSTORAGE)
 668 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 669                                 | BATU_BL_256M \
 670                                 | BATU_VS \
 671                                 | BATU_VP)
 672
 673 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 674 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 675                                 | BATL_PP_RW \
 676                                 | BATL_MEMCOHERENCE \
 677                                 | BATL_GUARDEDSTORAGE)
 678 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 679                                 | BATU_BL_256M \
 680                                 | BATU_VS \
 681                                 | BATU_VP)
 682
 683 #define CONFIG_SYS_IBAT7L       0
 684 #define CONFIG_SYS_IBAT7U       0
 685
 686 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 687 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 688 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 689 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 690 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 691 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 692 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 693 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 694 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 695 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 696 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 697 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 698 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 699 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 700 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 701 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 702
 703 #if defined(CONFIG_CMD_KGDB)
 704 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 705 #endif
 706
 707 /*
 708  * Environment Configuration
 709  */
 710 #define CONFIG_ENV_OVERWRITE
 711
 712 #define CONFIG_NETDEV           "eth0"
 713
 714 #ifdef CONFIG_MPC8349ITX
 715 #define CONFIG_HOSTNAME         "mpc8349emitx"
 716 #else
 717 #define CONFIG_HOSTNAME         "mpc8349emitxgp"
 718 #endif
 719
 720 /* Default path and filenames */
 721 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 722 #define CONFIG_BOOTFILE         "uImage"
 723                                 /* U-Boot image on TFTP server */
 724 #define CONFIG_UBOOTPATH        "u-boot.bin"
 725
 726 #ifdef CONFIG_MPC8349ITX
 727 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 728 #else
 729 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 730 #endif
 731
 732
 733 #define CONFIG_BOOTARGS \
 734         "root=/dev/nfs rw" \
 735         " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH    \
 736         " ip=" __stringify(CONFIG_IPADDR) ":"           \
 737                 __stringify(CONFIG_SERVERIP) ":"        \
 738                 __stringify(CONFIG_GATEWAYIP) ":"       \
 739                 __stringify(CONFIG_NETMASK) ":"         \
 740                 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"                \
 741         " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
 742
 743 #define CONFIG_EXTRA_ENV_SETTINGS \
 744         "console=" __stringify(CONFIG_CONSOLE) "\0"                     \
 745         "netdev=" CONFIG_NETDEV "\0"                                    \
 746         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 747         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 748                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 749                         " +$filesize; " \
 750                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 751                         " +$filesize; " \
 752                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 753                         " $filesize; "  \
 754                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 755                         " +$filesize; " \
 756                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 757                         " $filesize\0"  \
 758         "fdtaddr=780000\0"                                              \
 759         "fdtfile=" CONFIG_FDTFILE "\0"
 760
 761 #define CONFIG_NFSBOOTCOMMAND                                           \
 762         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 763         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 764         " console=$console,$baudrate $othbootargs; "                    \
 765         "tftp $loadaddr $bootfile;"                                     \
 766         "tftp $fdtaddr $fdtfile;"                                       \
 767         "bootm $loadaddr - $fdtaddr"
 768
 769 #define CONFIG_RAMBOOTCOMMAND                                           \
 770         "setenv bootargs root=/dev/ram rw"                              \
 771         " console=$console,$baudrate $othbootargs; "                    \
 772         "tftp $ramdiskaddr $ramdiskfile;"                               \
 773         "tftp $loadaddr $bootfile;"                                     \
 774         "tftp $fdtaddr $fdtfile;"                                       \
 775         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 776
 777 #endif