1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
7 MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
18 0xF001_0000-0xF001_FFFF Local bus expansion slot
19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
25 Bus Addr Part No. Description Length Location
26 ----------------------------------------------------------------
27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
29 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
36 Note that a given board has *either* a pair of 8574s or a pair of 8574As.
43 * High Level Configuration Options
45 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
47 #define CONFIG_MISC_INIT_F
53 #ifdef CONFIG_TARGET_MPC8349ITX
54 /* The CF card interface on the back of the board */
55 #define CONFIG_COMPACT_FLASH
56 #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
57 #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
60 #define CONFIG_RTC_DS1337
61 #define CONFIG_SYS_I2C
64 * Device configurations
69 #define CONFIG_SYS_I2C_FSL
70 #define CONFIG_SYS_FSL_I2C_SPEED 400000
71 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
72 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
73 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
74 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
75 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
77 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */
78 #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
80 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
81 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
82 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
83 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
84 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
85 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
86 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
88 /* Don't probe these addresses: */
89 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
90 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
91 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
92 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
93 /* Bit definitions for the 8574[A] I2C expander */
94 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
95 #define I2C_8574_REVISION 0x03
96 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
97 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
98 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
99 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
104 #ifdef CONFIG_COMPACT_FLASH
106 #define CONFIG_SYS_IDE_MAXBUS 1
107 #define CONFIG_SYS_IDE_MAXDEVICE 1
109 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
110 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE
111 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
112 #define CONFIG_SYS_ATA_REG_OFFSET 0
113 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
114 #define CONFIG_SYS_ATA_STRIDE 2
116 /* If a CF card is not inserted, time out quickly */
117 #define ATA_RESET_TIME 1
124 #ifdef CONFIG_SATA_SIL3114
126 #define CONFIG_SYS_SATA_MAX_DEVICE 4
131 #ifdef CONFIG_SYS_USB_HOST
135 #define CONFIG_USB_EHCI_FSL
137 /* Current USB implementation supports the only USB controller,
138 * so we have to choose between the MPH or the DR ones */
140 #define CONFIG_HAS_FSL_MPH_USB
142 #define CONFIG_HAS_FSL_DR_USB
150 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
151 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
152 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
153 #define CONFIG_SYS_83XX_DDR_USES_CS0
154 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
155 #define CONFIG_SYS_MEMTEST_END 0x2000
157 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
158 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
160 #define CONFIG_VERY_BIG_RAM
161 #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
163 #ifdef CONFIG_SYS_I2C
164 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
167 /* No SPD? Then manually set up DDR parameters */
168 #ifndef CONFIG_SPD_EEPROM
169 #define CONFIG_SYS_DDR_SIZE 256 /* Mb */
170 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
171 | CSCONFIG_ROW_BIT_13 \
172 | CSCONFIG_COL_BIT_10)
174 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
175 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
179 *Flash on the Local Bus
182 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
183 #define CONFIG_SYS_FLASH_EMPTY_INFO
184 /* 127 64KB sectors + 8 8KB sectors per device */
185 #define CONFIG_SYS_MAX_FLASH_SECT 135
186 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
187 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
188 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
190 /* The ITX has two flash chips, but the ITX-GP has only one. To support both
191 boards, we say we have two, but don't display a message if we find only one. */
192 #define CONFIG_SYS_FLASH_QUIET_TEST
193 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
194 #define CONFIG_SYS_FLASH_BANKS_LIST \
195 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
196 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
200 #ifdef CONFIG_VSC7385_ENET
204 /* The flash address and size of the VSC7385 firmware image */
205 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
206 #define CONFIG_VSC7385_IMAGE_SIZE 8192
211 * BRx, ORx, LBLAWBARx, and LBLAWARx
217 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
219 #ifdef CONFIG_VSC7385_ENET
225 #define CONFIG_SYS_LED_BASE 0xF9000000
230 #ifdef CONFIG_COMPACT_FLASH
232 #define CONFIG_SYS_CF_BASE 0xF0000000
238 * U-Boot memory configuration
240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
242 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
243 #define CONFIG_SYS_RAMBOOT
245 #undef CONFIG_SYS_RAMBOOT
248 #define CONFIG_SYS_INIT_RAM_LOCK
249 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
250 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
252 #define CONFIG_SYS_GBL_DATA_OFFSET \
253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
254 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
256 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
257 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
258 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
261 * Local Bus LCRR and LBCR regs
262 * LCRR: DLL bypass, Clock divider is 4
263 * External Local Bus rate is
264 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
266 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
267 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
268 #define CONFIG_SYS_LBC_LBCR 0x00000000
270 /* LB sdram refresh timer, about 6us */
271 #define CONFIG_SYS_LBC_LSRT 0x32000000
272 /* LB refresh timer prescal, 266MHz/32*/
273 #define CONFIG_SYS_LBC_MRTPR 0x20000000
278 #define CONFIG_SYS_NS16550_SERIAL
279 #define CONFIG_SYS_NS16550_REG_SIZE 1
280 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
282 #define CONFIG_SYS_BAUDRATE_TABLE \
283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
285 #define CONSOLE ttyS0
287 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
288 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
294 #define CONFIG_PCI_INDIRECT_BRIDGE
296 #define CONFIG_MPC83XX_PCI2
300 * Addresses are mapped 1-1.
302 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
303 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
304 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
305 #define CONFIG_SYS_PCI1_MMIO_BASE \
306 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
307 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
308 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
309 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
310 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
311 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
313 #ifdef CONFIG_MPC83XX_PCI2
314 #define CONFIG_SYS_PCI2_MEM_BASE \
315 (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
316 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
317 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
318 #define CONFIG_SYS_PCI2_MMIO_BASE \
319 (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
320 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
321 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
322 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
323 #define CONFIG_SYS_PCI2_IO_PHYS \
324 (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
325 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
328 #ifndef CONFIG_PCI_PNP
329 #define PCI_ENET0_IOADDR 0x00000000
330 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE
331 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
334 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
340 #ifdef CONFIG_TSEC_ENET
344 #define CONFIG_HAS_ETH0
345 #define CONFIG_TSEC1_NAME "TSEC0"
346 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
347 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
348 #define TSEC1_PHYIDX 0
349 #define TSEC1_FLAGS TSEC_GIGABIT
353 #define CONFIG_HAS_ETH1
354 #define CONFIG_TSEC2_NAME "TSEC1"
355 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
357 #define TSEC2_PHY_ADDR 4
358 #define TSEC2_PHYIDX 0
359 #define TSEC2_FLAGS TSEC_GIGABIT
362 #define CONFIG_ETHPRIME "Freescale TSEC"
369 #define CONFIG_ENV_OVERWRITE
371 #ifndef CONFIG_SYS_RAMBOOT
372 #define CONFIG_ENV_ADDR \
373 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
374 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
375 #define CONFIG_ENV_SIZE 0x2000
377 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
378 #define CONFIG_ENV_SIZE 0x2000
381 #define CONFIG_LOADS_ECHO /* echo on for serial download */
382 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
387 #define CONFIG_BOOTP_BOOTFILESIZE
390 #undef CONFIG_WATCHDOG /* watchdog disabled */
393 * Miscellaneous configurable options
396 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
397 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
400 * For booting Linux, the board info and command line data
401 * have to be in the first 256 MB of memory, since this is
402 * the maximum mapped by the Linux kernel during initialization.
404 /* Initial Memory map for Linux*/
405 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
406 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
411 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
412 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
413 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
414 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
415 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
416 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
417 #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */
418 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
423 /* Needed for gigabit to work on TSEC 1 */
424 #define CONFIG_SYS_SICRH SICRH_TSOBI1
425 /* USB DR as device + USB MPH as host */
426 #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
428 #define CONFIG_SYS_HID0_INIT 0x00000000
429 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
431 #define CONFIG_SYS_HID2 HID2_HBE
433 #if defined(CONFIG_CMD_KGDB)
434 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
438 * Environment Configuration
440 #define CONFIG_ENV_OVERWRITE
442 #define CONFIG_NETDEV "eth0"
444 /* Default path and filenames */
445 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
446 #define CONFIG_BOOTFILE "uImage"
447 /* U-Boot image on TFTP server */
448 #define CONFIG_UBOOTPATH "u-boot.bin"
450 #ifdef CONFIG_TARGET_MPC8349ITX
451 #define CONFIG_FDTFILE "mpc8349emitx.dtb"
453 #define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
457 #define CONFIG_EXTRA_ENV_SETTINGS \
458 "console=" __stringify(CONSOLE) "\0" \
459 "netdev=" CONFIG_NETDEV "\0" \
460 "uboot=" CONFIG_UBOOTPATH "\0" \
461 "tftpflash=tftpboot $loadaddr $uboot; " \
462 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
464 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
466 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
468 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
470 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
473 "fdtfile=" CONFIG_FDTFILE "\0"
475 #define CONFIG_NFSBOOTCOMMAND \
476 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
477 " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
478 " console=$console,$baudrate $othbootargs; " \
479 "tftp $loadaddr $bootfile;" \
480 "tftp $fdtaddr $fdtfile;" \
481 "bootm $loadaddr - $fdtaddr"
483 #define CONFIG_RAMBOOTCOMMAND \
484 "setenv bootargs root=/dev/ram rw" \
485 " console=$console,$baudrate $othbootargs; " \
486 "tftp $ramdiskaddr $ramdiskfile;" \
487 "tftp $loadaddr $bootfile;" \
488 "tftp $fdtaddr $fdtfile;" \
489 "bootm $loadaddr $ramdiskaddr $fdtaddr"