include/configs/MPC8349ITX.h

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
   9
  10  Memory map:
  11
  12  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
  13  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
  14  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
  15  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
  16  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
  17  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
  18  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
  19  0xF001_0000-0xF001_FFFF Local bus expansion slot
  20  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
  21  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
  22  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
  23
  24  I2C address list:
  25                                                 Align.  Board
  26  Bus    Addr    Part No.        Description     Length  Location
  27  ----------------------------------------------------------------
  28  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
  29
  30  I2C1   0x20    PCF8574         I2C Expander    0       U8
  31  I2C1   0x21    PCF8574         I2C Expander    0       U10
  32  I2C1   0x38    PCF8574A        I2C Expander    0       U8
  33  I2C1   0x39    PCF8574A        I2C Expander    0       U10
  34  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
  35  I2C1   0x68    DS1339          RTC             1       U68
  36
  37  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
  38 */
  39
  40 #ifndef __CONFIG_H
  41 #define __CONFIG_H
  42
  43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
  44 #define CONFIG_SYS_LOWBOOT
  45 #endif
  46
  47 /*
  48  * High Level Configuration Options
  49  */
  50 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
  51 #define CONFIG_MPC8349          /* MPC8349 specific */
  52
  53 #ifndef CONFIG_SYS_TEXT_BASE
  54 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
  55 #endif
  56
  57 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
  58
  59 #define CONFIG_MISC_INIT_F
  60 #define CONFIG_MISC_INIT_R
  61
  62 /*
  63  * On-board devices
  64  */
  65
  66 #ifdef CONFIG_MPC8349ITX
  67 /* The CF card interface on the back of the board */
  68 #define CONFIG_COMPACT_FLASH
  69 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
  70 #define CONFIG_SATA_SIL3114     /* SIL3114 SATA controller */
  71 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
  72 #endif
  73
  74 #define CONFIG_RTC_DS1337
  75 #define CONFIG_SYS_I2C
  76 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
  77
  78 /*
  79  * Device configurations
  80  */
  81
  82 /* I2C */
  83 #ifdef CONFIG_SYS_I2C
  84 #define CONFIG_SYS_I2C_FSL
  85 #define CONFIG_SYS_FSL_I2C_SPEED        400000
  86 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  87 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
  88 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
  89 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
  90 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
  91
  92 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
  93 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
  94
  95 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
  96 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
  97 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
  98 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
 100 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
 101 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
 102
 103 /* Don't probe these addresses: */
 104 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
 105                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
 106                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
 107                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
 108 /* Bit definitions for the 8574[A] I2C expander */
 109                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
 110 #define I2C_8574_REVISION       0x03
 111 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
 112 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
 113 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
 114 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
 115
 116 #endif
 117
 118 /* Compact Flash */
 119 #ifdef CONFIG_COMPACT_FLASH
 120
 121 #define CONFIG_SYS_IDE_MAXBUS           1
 122 #define CONFIG_SYS_IDE_MAXDEVICE        1
 123
 124 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 125 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
 126 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
 127 #define CONFIG_SYS_ATA_REG_OFFSET       0
 128 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
 129 #define CONFIG_SYS_ATA_STRIDE           2
 130
 131 /* If a CF card is not inserted, time out quickly */
 132 #define ATA_RESET_TIME  1
 133
 134 #endif
 135
 136 /*
 137  * SATA
 138  */
 139 #ifdef CONFIG_SATA_SIL3114
 140
 141 #define CONFIG_SYS_SATA_MAX_DEVICE      4
 142 #define CONFIG_LIBATA
 143 #define CONFIG_LBA48
 144
 145 #endif
 146
 147 #ifdef CONFIG_SYS_USB_HOST
 148 /*
 149  * Support USB
 150  */
 151 #define CONFIG_USB_EHCI
 152 #define CONFIG_USB_EHCI_FSL
 153
 154 /* Current USB implementation supports the only USB controller,
 155  * so we have to choose between the MPH or the DR ones */
 156 #if 1
 157 #define CONFIG_HAS_FSL_MPH_USB
 158 #else
 159 #define CONFIG_HAS_FSL_DR_USB
 160 #endif
 161
 162 #endif
 163
 164 /*
 165  * DDR Setup
 166  */
 167 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
 168 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 169 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 170 #define CONFIG_SYS_83XX_DDR_USES_CS0
 171 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
 172 #define CONFIG_SYS_MEMTEST_END          0x2000
 173
 174 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 175                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 176
 177 #define CONFIG_VERY_BIG_RAM
 178 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
 179
 180 #ifdef CONFIG_SYS_I2C
 181 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
 182 #endif
 183
 184 /* No SPD? Then manually set up DDR parameters */
 185 #ifndef CONFIG_SPD_EEPROM
 186     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
 187     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
 188                                         | CSCONFIG_ROW_BIT_13 \
 189                                         | CSCONFIG_COL_BIT_10)
 190
 191     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
 192     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
 193 #endif
 194
 195 /*
 196  *Flash on the Local Bus
 197  */
 198
 199 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 200 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 201 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 202 #define CONFIG_SYS_FLASH_EMPTY_INFO
 203 /* 127 64KB sectors + 8 8KB sectors per device */
 204 #define CONFIG_SYS_MAX_FLASH_SECT       135
 205 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 206 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 207 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 208
 209 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
 210 boards, we say we have two, but don't display a message if we find only one. */
 211 #define CONFIG_SYS_FLASH_QUIET_TEST
 212 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 213 #define CONFIG_SYS_FLASH_BANKS_LIST     \
 214                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
 215 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
 216 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 217
 218 /* Vitesse 7385 */
 219
 220 #ifdef CONFIG_VSC7385_ENET
 221
 222 #define CONFIG_TSEC2
 223
 224 /* The flash address and size of the VSC7385 firmware image */
 225 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
 226 #define CONFIG_VSC7385_IMAGE_SIZE       8192
 227
 228 #endif
 229
 230 /*
 231  * BRx, ORx, LBLAWBARx, and LBLAWARx
 232  */
 233
 234 /* Flash */
 235
 236 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 237                                 | BR_PS_16 \
 238                                 | BR_MS_GPCM \
 239                                 | BR_V)
 240 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 241                                 | OR_UPM_XAM \
 242                                 | OR_GPCM_CSNT \
 243                                 | OR_GPCM_ACS_DIV2 \
 244                                 | OR_GPCM_XACS \
 245                                 | OR_GPCM_SCY_15 \
 246                                 | OR_GPCM_TRLX_SET \
 247                                 | OR_GPCM_EHTR_SET \
 248                                 | OR_GPCM_EAD)
 249 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 250 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
 251
 252 /* Vitesse 7385 */
 253
 254 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
 255
 256 #ifdef CONFIG_VSC7385_ENET
 257
 258 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
 259                                 | BR_PS_8 \
 260                                 | BR_MS_GPCM \
 261                                 | BR_V)
 262 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
 263                                 | OR_GPCM_CSNT \
 264                                 | OR_GPCM_XACS \
 265                                 | OR_GPCM_SCY_15 \
 266                                 | OR_GPCM_SETA \
 267                                 | OR_GPCM_TRLX_SET \
 268                                 | OR_GPCM_EHTR_SET \
 269                                 | OR_GPCM_EAD)
 270
 271 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
 272 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
 273
 274 #endif
 275
 276 /* LED */
 277
 278 #define CONFIG_SYS_LED_BASE     0xF9000000
 279 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
 280                                 | BR_PS_8 \
 281                                 | BR_MS_GPCM \
 282                                 | BR_V)
 283 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
 284                                 | OR_GPCM_CSNT \
 285                                 | OR_GPCM_ACS_DIV2 \
 286                                 | OR_GPCM_XACS \
 287                                 | OR_GPCM_SCY_9 \
 288                                 | OR_GPCM_TRLX_SET \
 289                                 | OR_GPCM_EHTR_SET \
 290                                 | OR_GPCM_EAD)
 291
 292 /* Compact Flash */
 293
 294 #ifdef CONFIG_COMPACT_FLASH
 295
 296 #define CONFIG_SYS_CF_BASE      0xF0000000
 297
 298 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
 299                                 | BR_PS_16 \
 300                                 | BR_MS_UPMA \
 301                                 | BR_V)
 302 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
 303
 304 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
 305 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
 306
 307 #endif
 308
 309 /*
 310  * U-Boot memory configuration
 311  */
 312 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 313
 314 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 315 #define CONFIG_SYS_RAMBOOT
 316 #else
 317 #undef  CONFIG_SYS_RAMBOOT
 318 #endif
 319
 320 #define CONFIG_SYS_INIT_RAM_LOCK
 321 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 322 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 323
 324 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 325                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 326 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 327
 328 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 329 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 330 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
 331
 332 /*
 333  * Local Bus LCRR and LBCR regs
 334  *    LCRR:  DLL bypass, Clock divider is 4
 335  * External Local Bus rate is
 336  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 337  */
 338 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 339 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 340 #define CONFIG_SYS_LBC_LBCR     0x00000000
 341
 342                                 /* LB sdram refresh timer, about 6us */
 343 #define CONFIG_SYS_LBC_LSRT     0x32000000
 344                                 /* LB refresh timer prescal, 266MHz/32*/
 345 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 346
 347 /*
 348  * Serial Port
 349  */
 350 #define CONFIG_CONS_INDEX       1
 351 #define CONFIG_SYS_NS16550_SERIAL
 352 #define CONFIG_SYS_NS16550_REG_SIZE     1
 353 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 354
 355 #define CONFIG_SYS_BAUDRATE_TABLE  \
 356                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 357
 358 #define CONSOLE                 ttyS0
 359 #define CONFIG_BAUDRATE         115200
 360
 361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 363
 364 /*
 365  * PCI
 366  */
 367 #ifdef CONFIG_PCI
 368 #define CONFIG_PCI_INDIRECT_BRIDGE
 369
 370 #define CONFIG_MPC83XX_PCI2
 371
 372 /*
 373  * General PCI
 374  * Addresses are mapped 1-1.
 375  */
 376 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 377 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 378 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 379 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 380                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 381 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 382 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 383 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 384 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 385 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
 386
 387 #ifdef CONFIG_MPC83XX_PCI2
 388 #define CONFIG_SYS_PCI2_MEM_BASE        \
 389                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
 390 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 391 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 392 #define CONFIG_SYS_PCI2_MMIO_BASE       \
 393                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
 394 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 395 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 396 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 397 #define CONFIG_SYS_PCI2_IO_PHYS         \
 398                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
 399 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
 400 #endif
 401
 402 #ifndef CONFIG_PCI_PNP
 403     #define PCI_ENET0_IOADDR    0x00000000
 404     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
 405     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
 406 #endif
 407
 408 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 409
 410 #endif
 411
 412 #define CONFIG_PCI_66M
 413 #ifdef CONFIG_PCI_66M
 414 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
 415 #else
 416 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
 417 #endif
 418
 419 /* TSEC */
 420
 421 #ifdef CONFIG_TSEC_ENET
 422
 423 #define CONFIG_MII
 424 #define CONFIG_PHY_GIGE         /* In case CONFIG_CMD_MII is specified */
 425
 426 #define CONFIG_TSEC1
 427
 428 #ifdef CONFIG_TSEC1
 429 #define CONFIG_HAS_ETH0
 430 #define CONFIG_TSEC1_NAME  "TSEC0"
 431 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 432 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
 433 #define TSEC1_PHYIDX            0
 434 #define TSEC1_FLAGS             TSEC_GIGABIT
 435 #endif
 436
 437 #ifdef CONFIG_TSEC2
 438 #define CONFIG_HAS_ETH1
 439 #define CONFIG_TSEC2_NAME  "TSEC1"
 440 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 441
 442 #define TSEC2_PHY_ADDR          4
 443 #define TSEC2_PHYIDX            0
 444 #define TSEC2_FLAGS             TSEC_GIGABIT
 445 #endif
 446
 447 #define CONFIG_ETHPRIME         "Freescale TSEC"
 448
 449 #endif
 450
 451 /*
 452  * Environment
 453  */
 454 #define CONFIG_ENV_OVERWRITE
 455
 456 #ifndef CONFIG_SYS_RAMBOOT
 457   #define CONFIG_ENV_IS_IN_FLASH
 458   #define CONFIG_ENV_ADDR       \
 459                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 460   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
 461   #define CONFIG_ENV_SIZE       0x2000
 462 #else
 463   #undef  CONFIG_FLASH_CFI_DRIVER
 464   #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
 465   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
 466   #define CONFIG_ENV_SIZE       0x2000
 467 #endif
 468
 469 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 470 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 471
 472 /*
 473  * BOOTP options
 474  */
 475 #define CONFIG_BOOTP_BOOTFILESIZE
 476 #define CONFIG_BOOTP_BOOTPATH
 477 #define CONFIG_BOOTP_GATEWAY
 478 #define CONFIG_BOOTP_HOSTNAME
 479
 480 /*
 481  * Command line configuration.
 482  */
 483 #define CONFIG_CMD_DATE
 484 #define CONFIG_CMD_IRQ
 485 #define CONFIG_CMD_SDRAM
 486
 487 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
 488                                 || defined(CONFIG_USB_STORAGE)
 489         #define CONFIG_SUPPORT_VFAT
 490 #endif
 491
 492 #ifdef CONFIG_COMPACT_FLASH
 493         #define CONFIG_CMD_IDE
 494 #endif
 495
 496 #ifdef CONFIG_SATA_SIL3114
 497         #define CONFIG_CMD_SATA
 498 #endif
 499
 500 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
 501 #endif
 502
 503 #ifdef CONFIG_PCI
 504         #define CONFIG_CMD_PCI
 505 #endif
 506
 507 /* Watchdog */
 508 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 509
 510 /*
 511  * Miscellaneous configurable options
 512  */
 513 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 514 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 515 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 516
 517 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 518 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 519
 520 #if defined(CONFIG_CMD_KGDB)
 521         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 522 #else
 523         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 524 #endif
 525
 526                                 /* Print Buffer Size */
 527 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 528 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 529                                 /* Boot Argument Buffer Size */
 530 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 531
 532 /*
 533  * For booting Linux, the board info and command line data
 534  * have to be in the first 256 MB of memory, since this is
 535  * the maximum mapped by the Linux kernel during initialization.
 536  */
 537                                 /* Initial Memory map for Linux*/
 538 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 539 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 540
 541 #define CONFIG_SYS_HRCW_LOW (\
 542         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 543         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 544         HRCWL_CSB_TO_CLKIN_4X1 |\
 545         HRCWL_VCO_1X2 |\
 546         HRCWL_CORE_TO_CSB_2X1)
 547
 548 #ifdef CONFIG_SYS_LOWBOOT
 549 #define CONFIG_SYS_HRCW_HIGH (\
 550         HRCWH_PCI_HOST |\
 551         HRCWH_32_BIT_PCI |\
 552         HRCWH_PCI1_ARBITER_ENABLE |\
 553         HRCWH_PCI2_ARBITER_ENABLE |\
 554         HRCWH_CORE_ENABLE |\
 555         HRCWH_FROM_0X00000100 |\
 556         HRCWH_BOOTSEQ_DISABLE |\
 557         HRCWH_SW_WATCHDOG_DISABLE |\
 558         HRCWH_ROM_LOC_LOCAL_16BIT |\
 559         HRCWH_TSEC1M_IN_GMII |\
 560         HRCWH_TSEC2M_IN_GMII)
 561 #else
 562 #define CONFIG_SYS_HRCW_HIGH (\
 563         HRCWH_PCI_HOST |\
 564         HRCWH_32_BIT_PCI |\
 565         HRCWH_PCI1_ARBITER_ENABLE |\
 566         HRCWH_PCI2_ARBITER_ENABLE |\
 567         HRCWH_CORE_ENABLE |\
 568         HRCWH_FROM_0XFFF00100 |\
 569         HRCWH_BOOTSEQ_DISABLE |\
 570         HRCWH_SW_WATCHDOG_DISABLE |\
 571         HRCWH_ROM_LOC_LOCAL_16BIT |\
 572         HRCWH_TSEC1M_IN_GMII |\
 573         HRCWH_TSEC2M_IN_GMII)
 574 #endif
 575
 576 /*
 577  * System performance
 578  */
 579 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 580 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 581 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 582 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 583 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 584 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 585 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
 586 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
 587
 588 /*
 589  * System IO Config
 590  */
 591 /* Needed for gigabit to work on TSEC 1 */
 592 #define CONFIG_SYS_SICRH SICRH_TSOBI1
 593                                 /* USB DR as device + USB MPH as host */
 594 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
 595
 596 #define CONFIG_SYS_HID0_INIT    0x00000000
 597 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
 598
 599 #define CONFIG_SYS_HID2 HID2_HBE
 600 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 601
 602 /* DDR  */
 603 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 604                                 | BATL_PP_RW \
 605                                 | BATL_MEMCOHERENCE)
 606 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 607                                 | BATU_BL_256M \
 608                                 | BATU_VS \
 609                                 | BATU_VP)
 610
 611 /* PCI  */
 612 #ifdef CONFIG_PCI
 613 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 614                                 | BATL_PP_RW \
 615                                 | BATL_MEMCOHERENCE)
 616 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 617                                 | BATU_BL_256M \
 618                                 | BATU_VS \
 619                                 | BATU_VP)
 620 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 621                                 | BATL_PP_RW \
 622                                 | BATL_CACHEINHIBIT \
 623                                 | BATL_GUARDEDSTORAGE)
 624 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 625                                 | BATU_BL_256M \
 626                                 | BATU_VS \
 627                                 | BATU_VP)
 628 #else
 629 #define CONFIG_SYS_IBAT1L       0
 630 #define CONFIG_SYS_IBAT1U       0
 631 #define CONFIG_SYS_IBAT2L       0
 632 #define CONFIG_SYS_IBAT2U       0
 633 #endif
 634
 635 #ifdef CONFIG_MPC83XX_PCI2
 636 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 637                                 | BATL_PP_RW \
 638                                 | BATL_MEMCOHERENCE)
 639 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 640                                 | BATU_BL_256M \
 641                                 | BATU_VS \
 642                                 | BATU_VP)
 643 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 644                                 | BATL_PP_RW \
 645                                 | BATL_CACHEINHIBIT \
 646                                 | BATL_GUARDEDSTORAGE)
 647 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 648                                 | BATU_BL_256M \
 649                                 | BATU_VS \
 650                                 | BATU_VP)
 651 #else
 652 #define CONFIG_SYS_IBAT3L       0
 653 #define CONFIG_SYS_IBAT3U       0
 654 #define CONFIG_SYS_IBAT4L       0
 655 #define CONFIG_SYS_IBAT4U       0
 656 #endif
 657
 658 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 659 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 660                                 | BATL_PP_RW \
 661                                 | BATL_CACHEINHIBIT \
 662                                 | BATL_GUARDEDSTORAGE)
 663 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 664                                 | BATU_BL_256M \
 665                                 | BATU_VS \
 666                                 | BATU_VP)
 667
 668 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 669 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 670                                 | BATL_PP_RW \
 671                                 | BATL_MEMCOHERENCE \
 672                                 | BATL_GUARDEDSTORAGE)
 673 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 674                                 | BATU_BL_256M \
 675                                 | BATU_VS \
 676                                 | BATU_VP)
 677
 678 #define CONFIG_SYS_IBAT7L       0
 679 #define CONFIG_SYS_IBAT7U       0
 680
 681 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 682 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 683 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 684 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 685 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 686 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 687 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 688 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 689 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 690 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 691 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 692 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 693 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 694 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 695 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 696 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 697
 698 #if defined(CONFIG_CMD_KGDB)
 699 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 700 #endif
 701
 702 /*
 703  * Environment Configuration
 704  */
 705 #define CONFIG_ENV_OVERWRITE
 706
 707 #define CONFIG_NETDEV           "eth0"
 708
 709 #ifdef CONFIG_MPC8349ITX
 710 #define CONFIG_HOSTNAME         "mpc8349emitx"
 711 #else
 712 #define CONFIG_HOSTNAME         "mpc8349emitxgp"
 713 #endif
 714
 715 /* Default path and filenames */
 716 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 717 #define CONFIG_BOOTFILE         "uImage"
 718                                 /* U-Boot image on TFTP server */
 719 #define CONFIG_UBOOTPATH        "u-boot.bin"
 720
 721 #ifdef CONFIG_MPC8349ITX
 722 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
 723 #else
 724 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
 725 #endif
 726
 727
 728 #define CONFIG_BOOTARGS \
 729         "root=/dev/nfs rw" \
 730         " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH    \
 731         " ip=" __stringify(CONFIG_IPADDR) ":"           \
 732                 __stringify(CONFIG_SERVERIP) ":"        \
 733                 __stringify(CONFIG_GATEWAYIP) ":"       \
 734                 __stringify(CONFIG_NETMASK) ":"         \
 735                 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"                \
 736         " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
 737
 738 #define CONFIG_EXTRA_ENV_SETTINGS \
 739         "console=" __stringify(CONSOLE) "\0"                    \
 740         "netdev=" CONFIG_NETDEV "\0"                                    \
 741         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 742         "tftpflash=tftpboot $loadaddr $uboot; "                         \
 743                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 744                         " +$filesize; " \
 745                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 746                         " +$filesize; " \
 747                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 748                         " $filesize; "  \
 749                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 750                         " +$filesize; " \
 751                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 752                         " $filesize\0"  \
 753         "fdtaddr=780000\0"                                              \
 754         "fdtfile=" CONFIG_FDTFILE "\0"
 755
 756 #define CONFIG_NFSBOOTCOMMAND                                           \
 757         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
 758         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
 759         " console=$console,$baudrate $othbootargs; "                    \
 760         "tftp $loadaddr $bootfile;"                                     \
 761         "tftp $fdtaddr $fdtfile;"                                       \
 762         "bootm $loadaddr - $fdtaddr"
 763
 764 #define CONFIG_RAMBOOTCOMMAND                                           \
 765         "setenv bootargs root=/dev/ram rw"                              \
 766         " console=$console,$baudrate $othbootargs; "                    \
 767         "tftp $ramdiskaddr $ramdiskfile;"                               \
 768         "tftp $loadaddr $bootfile;"                                     \
 769         "tftp $fdtaddr $fdtfile;"                                       \
 770         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 771
 772 #endif