Merge git://git.denx.de/u-boot-dm
[platform/kernel/u-boot.git] / include / configs / MPC8349ITX.h
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 /*
8  MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
9
10  Memory map:
11
12  0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
13  0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
14  0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
15  0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
16  0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
17  0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
18  0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
19  0xF001_0000-0xF001_FFFF Local bus expansion slot
20  0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
21  0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
22  0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
23
24  I2C address list:
25                                                 Align.  Board
26  Bus    Addr    Part No.        Description     Length  Location
27  ----------------------------------------------------------------
28  I2C0   0x50    M24256-BWMN6P   Board EEPROM    2       U64
29
30  I2C1   0x20    PCF8574         I2C Expander    0       U8
31  I2C1   0x21    PCF8574         I2C Expander    0       U10
32  I2C1   0x38    PCF8574A        I2C Expander    0       U8
33  I2C1   0x39    PCF8574A        I2C Expander    0       U10
34  I2C1   0x51    (DDR)           DDR EEPROM      1       U1
35  I2C1   0x68    DS1339          RTC             1       U68
36
37  Note that a given board has *either* a pair of 8574s or a pair of 8574As.
38 */
39
40 #ifndef __CONFIG_H
41 #define __CONFIG_H
42
43 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
44 #define CONFIG_SYS_LOWBOOT
45 #endif
46
47 /*
48  * High Level Configuration Options
49  */
50 #define CONFIG_MPC834x          /* MPC834x family (8343, 8347, 8349) */
51 #define CONFIG_MPC8349          /* MPC8349 specific */
52
53 #ifndef CONFIG_SYS_TEXT_BASE
54 #define CONFIG_SYS_TEXT_BASE    0xFEF00000
55 #endif
56
57 #define CONFIG_SYS_IMMR 0xE0000000      /* The IMMR is relocated to here */
58
59 #define CONFIG_MISC_INIT_F
60 #define CONFIG_MISC_INIT_R
61
62 /*
63  * On-board devices
64  */
65
66 #ifdef CONFIG_MPC8349ITX
67 /* The CF card interface on the back of the board */
68 #define CONFIG_COMPACT_FLASH
69 #define CONFIG_VSC7385_ENET     /* VSC7385 ethernet support */
70 #define CONFIG_SATA_SIL3114     /* SIL3114 SATA controller */
71 #define CONFIG_SYS_USB_HOST     /* use the EHCI USB controller */
72 #endif
73
74 #define CONFIG_RTC_DS1337
75 #define CONFIG_SYS_I2C
76 #define CONFIG_TSEC_ENET                /* TSEC Ethernet support */
77
78 /*
79  * Device configurations
80  */
81
82 /* I2C */
83 #ifdef CONFIG_SYS_I2C
84 #define CONFIG_SYS_I2C_FSL
85 #define CONFIG_SYS_FSL_I2C_SPEED        400000
86 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
87 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
88 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
89 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
90 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
91
92 #define CONFIG_SYS_SPD_BUS_NUM          1       /* The I2C bus for SPD */
93 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC */
94
95 #define CONFIG_SYS_I2C_8574_ADDR1       0x20    /* I2C1, PCF8574 */
96 #define CONFIG_SYS_I2C_8574_ADDR2       0x21    /* I2C1, PCF8574 */
97 #define CONFIG_SYS_I2C_8574A_ADDR1      0x38    /* I2C1, PCF8574A */
98 #define CONFIG_SYS_I2C_8574A_ADDR2      0x39    /* I2C1, PCF8574A */
99 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* I2C0, Board EEPROM */
100 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* I2C1, DS1339 RTC*/
101 #define SPD_EEPROM_ADDRESS              0x51    /* I2C1, DDR */
102
103 /* Don't probe these addresses: */
104 #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \
105                                  {1, CONFIG_SYS_I2C_8574_ADDR2}, \
106                                  {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
107                                  {1, CONFIG_SYS_I2C_8574A_ADDR2} }
108 /* Bit definitions for the 8574[A] I2C expander */
109                                 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */
110 #define I2C_8574_REVISION       0x03
111 #define I2C_8574_CF             0x08    /* 1=Compact flash absent, 0=present */
112 #define I2C_8574_MPCICLKRN      0x10    /* MiniPCI Clk Run */
113 #define I2C_8574_PCI66          0x20    /* 0=33MHz PCI, 1=66MHz PCI */
114 #define I2C_8574_FLASHSIDE      0x40    /* 0=Reset vector from U4, 1=from U7*/
115
116 #endif
117
118 /* Compact Flash */
119 #ifdef CONFIG_COMPACT_FLASH
120
121 #define CONFIG_SYS_IDE_MAXBUS           1
122 #define CONFIG_SYS_IDE_MAXDEVICE        1
123
124 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
125 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_CF_BASE
126 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000
127 #define CONFIG_SYS_ATA_REG_OFFSET       0
128 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0200
129 #define CONFIG_SYS_ATA_STRIDE           2
130
131 /* If a CF card is not inserted, time out quickly */
132 #define ATA_RESET_TIME  1
133
134 #endif
135
136 /*
137  * SATA
138  */
139 #ifdef CONFIG_SATA_SIL3114
140
141 #define CONFIG_SYS_SATA_MAX_DEVICE      4
142 #define CONFIG_LIBATA
143 #define CONFIG_LBA48
144
145 #endif
146
147 #ifdef CONFIG_SYS_USB_HOST
148 /*
149  * Support USB
150  */
151 #define CONFIG_USB_EHCI_FSL
152
153 /* Current USB implementation supports the only USB controller,
154  * so we have to choose between the MPH or the DR ones */
155 #if 1
156 #define CONFIG_HAS_FSL_MPH_USB
157 #else
158 #define CONFIG_HAS_FSL_DR_USB
159 #endif
160
161 #endif
162
163 /*
164  * DDR Setup
165  */
166 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
167 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
168 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
169 #define CONFIG_SYS_83XX_DDR_USES_CS0
170 #define CONFIG_SYS_MEMTEST_START        0x1000  /* memtest region */
171 #define CONFIG_SYS_MEMTEST_END          0x2000
172
173 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
174                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
175
176 #define CONFIG_VERY_BIG_RAM
177 #define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
178
179 #ifdef CONFIG_SYS_I2C
180 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
181 #endif
182
183 /* No SPD? Then manually set up DDR parameters */
184 #ifndef CONFIG_SPD_EEPROM
185     #define CONFIG_SYS_DDR_SIZE         256     /* Mb */
186     #define CONFIG_SYS_DDR_CS0_CONFIG   (CSCONFIG_EN \
187                                         | CSCONFIG_ROW_BIT_13 \
188                                         | CSCONFIG_COL_BIT_10)
189
190     #define CONFIG_SYS_DDR_TIMING_1     0x26242321
191     #define CONFIG_SYS_DDR_TIMING_2     0x00000800  /* P9-45, may need tuning */
192 #endif
193
194 /*
195  *Flash on the Local Bus
196  */
197
198 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
199 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
200 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
201 #define CONFIG_SYS_FLASH_EMPTY_INFO
202 /* 127 64KB sectors + 8 8KB sectors per device */
203 #define CONFIG_SYS_MAX_FLASH_SECT       135
204 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
206 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
207
208 /* The ITX has two flash chips, but the ITX-GP has only one.  To support both
209 boards, we say we have two, but don't display a message if we find only one. */
210 #define CONFIG_SYS_FLASH_QUIET_TEST
211 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
212 #define CONFIG_SYS_FLASH_BANKS_LIST     \
213                 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
214 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size in MB */
215 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
216
217 /* Vitesse 7385 */
218
219 #ifdef CONFIG_VSC7385_ENET
220
221 #define CONFIG_TSEC2
222
223 /* The flash address and size of the VSC7385 firmware image */
224 #define CONFIG_VSC7385_IMAGE            0xFEFFE000
225 #define CONFIG_VSC7385_IMAGE_SIZE       8192
226
227 #endif
228
229 /*
230  * BRx, ORx, LBLAWBARx, and LBLAWARx
231  */
232
233 /* Flash */
234
235 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
236                                 | BR_PS_16 \
237                                 | BR_MS_GPCM \
238                                 | BR_V)
239 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
240                                 | OR_UPM_XAM \
241                                 | OR_GPCM_CSNT \
242                                 | OR_GPCM_ACS_DIV2 \
243                                 | OR_GPCM_XACS \
244                                 | OR_GPCM_SCY_15 \
245                                 | OR_GPCM_TRLX_SET \
246                                 | OR_GPCM_EHTR_SET \
247                                 | OR_GPCM_EAD)
248 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
249 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_16MB)
250
251 /* Vitesse 7385 */
252
253 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
254
255 #ifdef CONFIG_VSC7385_ENET
256
257 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_VSC7385_BASE \
258                                 | BR_PS_8 \
259                                 | BR_MS_GPCM \
260                                 | BR_V)
261 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128KB \
262                                 | OR_GPCM_CSNT \
263                                 | OR_GPCM_XACS \
264                                 | OR_GPCM_SCY_15 \
265                                 | OR_GPCM_SETA \
266                                 | OR_GPCM_TRLX_SET \
267                                 | OR_GPCM_EHTR_SET \
268                                 | OR_GPCM_EAD)
269
270 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_VSC7385_BASE
271 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128KB)
272
273 #endif
274
275 /* LED */
276
277 #define CONFIG_SYS_LED_BASE     0xF9000000
278 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_LED_BASE \
279                                 | BR_PS_8 \
280                                 | BR_MS_GPCM \
281                                 | BR_V)
282 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_2MB \
283                                 | OR_GPCM_CSNT \
284                                 | OR_GPCM_ACS_DIV2 \
285                                 | OR_GPCM_XACS \
286                                 | OR_GPCM_SCY_9 \
287                                 | OR_GPCM_TRLX_SET \
288                                 | OR_GPCM_EHTR_SET \
289                                 | OR_GPCM_EAD)
290
291 /* Compact Flash */
292
293 #ifdef CONFIG_COMPACT_FLASH
294
295 #define CONFIG_SYS_CF_BASE      0xF0000000
296
297 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_CF_BASE \
298                                 | BR_PS_16 \
299                                 | BR_MS_UPMA \
300                                 | BR_V)
301 #define CONFIG_SYS_OR3_PRELIM   (OR_UPM_AM | OR_UPM_BI)
302
303 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_CF_BASE
304 #define CONFIG_SYS_LBLAWAR3_PRELIM      (LBLAWAR_EN | LBLAWAR_64KB)
305
306 #endif
307
308 /*
309  * U-Boot memory configuration
310  */
311 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
312
313 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
314 #define CONFIG_SYS_RAMBOOT
315 #else
316 #undef  CONFIG_SYS_RAMBOOT
317 #endif
318
319 #define CONFIG_SYS_INIT_RAM_LOCK
320 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
321 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
322
323 #define CONFIG_SYS_GBL_DATA_OFFSET      \
324                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
325 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
326
327 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
328 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
329 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024) /* Reserved for malloc */
330
331 /*
332  * Local Bus LCRR and LBCR regs
333  *    LCRR:  DLL bypass, Clock divider is 4
334  * External Local Bus rate is
335  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
336  */
337 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
338 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
339 #define CONFIG_SYS_LBC_LBCR     0x00000000
340
341                                 /* LB sdram refresh timer, about 6us */
342 #define CONFIG_SYS_LBC_LSRT     0x32000000
343                                 /* LB refresh timer prescal, 266MHz/32*/
344 #define CONFIG_SYS_LBC_MRTPR    0x20000000
345
346 /*
347  * Serial Port
348  */
349 #define CONFIG_CONS_INDEX       1
350 #define CONFIG_SYS_NS16550_SERIAL
351 #define CONFIG_SYS_NS16550_REG_SIZE     1
352 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
353
354 #define CONFIG_SYS_BAUDRATE_TABLE  \
355                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
356
357 #define CONSOLE                 ttyS0
358
359 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
360 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
361
362 /*
363  * PCI
364  */
365 #ifdef CONFIG_PCI
366 #define CONFIG_PCI_INDIRECT_BRIDGE
367
368 #define CONFIG_MPC83XX_PCI2
369
370 /*
371  * General PCI
372  * Addresses are mapped 1-1.
373  */
374 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
375 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
376 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
377 #define CONFIG_SYS_PCI1_MMIO_BASE       \
378                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
379 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
380 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
381 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
382 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
383 #define CONFIG_SYS_PCI1_IO_SIZE         0x01000000      /* 16M */
384
385 #ifdef CONFIG_MPC83XX_PCI2
386 #define CONFIG_SYS_PCI2_MEM_BASE        \
387                         (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
388 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
389 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
390 #define CONFIG_SYS_PCI2_MMIO_BASE       \
391                         (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
392 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
393 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
394 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
395 #define CONFIG_SYS_PCI2_IO_PHYS         \
396                         (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
397 #define CONFIG_SYS_PCI2_IO_SIZE         0x01000000      /* 16M */
398 #endif
399
400 #ifndef CONFIG_PCI_PNP
401     #define PCI_ENET0_IOADDR    0x00000000
402     #define PCI_ENET0_MEMADDR   CONFIG_SYS_PCI2_MEM_BASE
403     #define PCI_IDSEL_NUMBER    0x0f    /* IDSEL = AD15 */
404 #endif
405
406 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
407
408 #endif
409
410 #define CONFIG_PCI_66M
411 #ifdef CONFIG_PCI_66M
412 #define CONFIG_83XX_CLKIN       66666666        /* in Hz */
413 #else
414 #define CONFIG_83XX_CLKIN       33333333        /* in Hz */
415 #endif
416
417 /* TSEC */
418
419 #ifdef CONFIG_TSEC_ENET
420
421 #define CONFIG_MII
422 #define CONFIG_PHY_GIGE         /* In case CONFIG_CMD_MII is specified */
423
424 #define CONFIG_TSEC1
425
426 #ifdef CONFIG_TSEC1
427 #define CONFIG_HAS_ETH0
428 #define CONFIG_TSEC1_NAME  "TSEC0"
429 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
430 #define TSEC1_PHY_ADDR          0x1c    /* VSC8201 uses address 0x1c */
431 #define TSEC1_PHYIDX            0
432 #define TSEC1_FLAGS             TSEC_GIGABIT
433 #endif
434
435 #ifdef CONFIG_TSEC2
436 #define CONFIG_HAS_ETH1
437 #define CONFIG_TSEC2_NAME  "TSEC1"
438 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
439
440 #define TSEC2_PHY_ADDR          4
441 #define TSEC2_PHYIDX            0
442 #define TSEC2_FLAGS             TSEC_GIGABIT
443 #endif
444
445 #define CONFIG_ETHPRIME         "Freescale TSEC"
446
447 #endif
448
449 /*
450  * Environment
451  */
452 #define CONFIG_ENV_OVERWRITE
453
454 #ifndef CONFIG_SYS_RAMBOOT
455   #define CONFIG_ENV_IS_IN_FLASH
456   #define CONFIG_ENV_ADDR       \
457                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
458   #define CONFIG_ENV_SECT_SIZE  0x10000 /* 64K (one sector) for environment */
459   #define CONFIG_ENV_SIZE       0x2000
460 #else
461   #undef  CONFIG_FLASH_CFI_DRIVER
462   #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
463   #define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE - 0x1000)
464   #define CONFIG_ENV_SIZE       0x2000
465 #endif
466
467 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
468 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
469
470 /*
471  * BOOTP options
472  */
473 #define CONFIG_BOOTP_BOOTFILESIZE
474 #define CONFIG_BOOTP_BOOTPATH
475 #define CONFIG_BOOTP_GATEWAY
476 #define CONFIG_BOOTP_HOSTNAME
477
478 /*
479  * Command line configuration.
480  */
481 #define CONFIG_CMD_SDRAM
482
483 #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
484                                 || defined(CONFIG_USB_STORAGE)
485         #define CONFIG_SUPPORT_VFAT
486 #endif
487
488 #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
489 #endif
490
491 #ifdef CONFIG_PCI
492         #define CONFIG_CMD_PCI
493 #endif
494
495 /* Watchdog */
496 #undef CONFIG_WATCHDOG          /* watchdog disabled */
497
498 /*
499  * Miscellaneous configurable options
500  */
501 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
502 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
503 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
504
505 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
506 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
507
508 #if defined(CONFIG_CMD_KGDB)
509         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
510 #else
511         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
512 #endif
513
514                                 /* Print Buffer Size */
515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
516 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
517                                 /* Boot Argument Buffer Size */
518 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
519
520 /*
521  * For booting Linux, the board info and command line data
522  * have to be in the first 256 MB of memory, since this is
523  * the maximum mapped by the Linux kernel during initialization.
524  */
525                                 /* Initial Memory map for Linux*/
526 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
527 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
528
529 #define CONFIG_SYS_HRCW_LOW (\
530         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
531         HRCWL_DDR_TO_SCB_CLK_1X1 |\
532         HRCWL_CSB_TO_CLKIN_4X1 |\
533         HRCWL_VCO_1X2 |\
534         HRCWL_CORE_TO_CSB_2X1)
535
536 #ifdef CONFIG_SYS_LOWBOOT
537 #define CONFIG_SYS_HRCW_HIGH (\
538         HRCWH_PCI_HOST |\
539         HRCWH_32_BIT_PCI |\
540         HRCWH_PCI1_ARBITER_ENABLE |\
541         HRCWH_PCI2_ARBITER_ENABLE |\
542         HRCWH_CORE_ENABLE |\
543         HRCWH_FROM_0X00000100 |\
544         HRCWH_BOOTSEQ_DISABLE |\
545         HRCWH_SW_WATCHDOG_DISABLE |\
546         HRCWH_ROM_LOC_LOCAL_16BIT |\
547         HRCWH_TSEC1M_IN_GMII |\
548         HRCWH_TSEC2M_IN_GMII)
549 #else
550 #define CONFIG_SYS_HRCW_HIGH (\
551         HRCWH_PCI_HOST |\
552         HRCWH_32_BIT_PCI |\
553         HRCWH_PCI1_ARBITER_ENABLE |\
554         HRCWH_PCI2_ARBITER_ENABLE |\
555         HRCWH_CORE_ENABLE |\
556         HRCWH_FROM_0XFFF00100 |\
557         HRCWH_BOOTSEQ_DISABLE |\
558         HRCWH_SW_WATCHDOG_DISABLE |\
559         HRCWH_ROM_LOC_LOCAL_16BIT |\
560         HRCWH_TSEC1M_IN_GMII |\
561         HRCWH_TSEC2M_IN_GMII)
562 #endif
563
564 /*
565  * System performance
566  */
567 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
568 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
569 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
570 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
571 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
572 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
573 #define CONFIG_SYS_SCCR_USBMPHCM 3      /* USB MPH controller's clock */
574 #define CONFIG_SYS_SCCR_USBDRCM 0       /* USB DR controller's clock */
575
576 /*
577  * System IO Config
578  */
579 /* Needed for gigabit to work on TSEC 1 */
580 #define CONFIG_SYS_SICRH SICRH_TSOBI1
581                                 /* USB DR as device + USB MPH as host */
582 #define CONFIG_SYS_SICRL        (SICRL_LDP_A | SICRL_USB1)
583
584 #define CONFIG_SYS_HID0_INIT    0x00000000
585 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_INSTRUCTION_CACHE
586
587 #define CONFIG_SYS_HID2 HID2_HBE
588 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
589
590 /* DDR  */
591 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
592                                 | BATL_PP_RW \
593                                 | BATL_MEMCOHERENCE)
594 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
595                                 | BATU_BL_256M \
596                                 | BATU_VS \
597                                 | BATU_VP)
598
599 /* PCI  */
600 #ifdef CONFIG_PCI
601 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
602                                 | BATL_PP_RW \
603                                 | BATL_MEMCOHERENCE)
604 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
605                                 | BATU_BL_256M \
606                                 | BATU_VS \
607                                 | BATU_VP)
608 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
609                                 | BATL_PP_RW \
610                                 | BATL_CACHEINHIBIT \
611                                 | BATL_GUARDEDSTORAGE)
612 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
613                                 | BATU_BL_256M \
614                                 | BATU_VS \
615                                 | BATU_VP)
616 #else
617 #define CONFIG_SYS_IBAT1L       0
618 #define CONFIG_SYS_IBAT1U       0
619 #define CONFIG_SYS_IBAT2L       0
620 #define CONFIG_SYS_IBAT2U       0
621 #endif
622
623 #ifdef CONFIG_MPC83XX_PCI2
624 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
625                                 | BATL_PP_RW \
626                                 | BATL_MEMCOHERENCE)
627 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
628                                 | BATU_BL_256M \
629                                 | BATU_VS \
630                                 | BATU_VP)
631 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
632                                 | BATL_PP_RW \
633                                 | BATL_CACHEINHIBIT \
634                                 | BATL_GUARDEDSTORAGE)
635 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
636                                 | BATU_BL_256M \
637                                 | BATU_VS \
638                                 | BATU_VP)
639 #else
640 #define CONFIG_SYS_IBAT3L       0
641 #define CONFIG_SYS_IBAT3U       0
642 #define CONFIG_SYS_IBAT4L       0
643 #define CONFIG_SYS_IBAT4U       0
644 #endif
645
646 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
647 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
648                                 | BATL_PP_RW \
649                                 | BATL_CACHEINHIBIT \
650                                 | BATL_GUARDEDSTORAGE)
651 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
652                                 | BATU_BL_256M \
653                                 | BATU_VS \
654                                 | BATU_VP)
655
656 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
657 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
658                                 | BATL_PP_RW \
659                                 | BATL_MEMCOHERENCE \
660                                 | BATL_GUARDEDSTORAGE)
661 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
662                                 | BATU_BL_256M \
663                                 | BATU_VS \
664                                 | BATU_VP)
665
666 #define CONFIG_SYS_IBAT7L       0
667 #define CONFIG_SYS_IBAT7U       0
668
669 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
670 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
671 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
672 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
673 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
674 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
675 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
676 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
677 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
678 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
679 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
680 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
681 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
682 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
683 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
684 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
685
686 #if defined(CONFIG_CMD_KGDB)
687 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
688 #endif
689
690 /*
691  * Environment Configuration
692  */
693 #define CONFIG_ENV_OVERWRITE
694
695 #define CONFIG_NETDEV           "eth0"
696
697 #ifdef CONFIG_MPC8349ITX
698 #define CONFIG_HOSTNAME         "mpc8349emitx"
699 #else
700 #define CONFIG_HOSTNAME         "mpc8349emitxgp"
701 #endif
702
703 /* Default path and filenames */
704 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
705 #define CONFIG_BOOTFILE         "uImage"
706                                 /* U-Boot image on TFTP server */
707 #define CONFIG_UBOOTPATH        "u-boot.bin"
708
709 #ifdef CONFIG_MPC8349ITX
710 #define CONFIG_FDTFILE          "mpc8349emitx.dtb"
711 #else
712 #define CONFIG_FDTFILE          "mpc8349emitxgp.dtb"
713 #endif
714
715
716 #define CONFIG_BOOTARGS \
717         "root=/dev/nfs rw" \
718         " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH    \
719         " ip=" __stringify(CONFIG_IPADDR) ":"           \
720                 __stringify(CONFIG_SERVERIP) ":"        \
721                 __stringify(CONFIG_GATEWAYIP) ":"       \
722                 __stringify(CONFIG_NETMASK) ":"         \
723                 CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"                \
724         " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
725
726 #define CONFIG_EXTRA_ENV_SETTINGS \
727         "console=" __stringify(CONSOLE) "\0"                    \
728         "netdev=" CONFIG_NETDEV "\0"                                    \
729         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
730         "tftpflash=tftpboot $loadaddr $uboot; "                         \
731                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
732                         " +$filesize; " \
733                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
734                         " +$filesize; " \
735                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
736                         " $filesize; "  \
737                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
738                         " +$filesize; " \
739                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
740                         " $filesize\0"  \
741         "fdtaddr=780000\0"                                              \
742         "fdtfile=" CONFIG_FDTFILE "\0"
743
744 #define CONFIG_NFSBOOTCOMMAND                                           \
745         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"  \
746         " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
747         " console=$console,$baudrate $othbootargs; "                    \
748         "tftp $loadaddr $bootfile;"                                     \
749         "tftp $fdtaddr $fdtfile;"                                       \
750         "bootm $loadaddr - $fdtaddr"
751
752 #define CONFIG_RAMBOOTCOMMAND                                           \
753         "setenv bootargs root=/dev/ram rw"                              \
754         " console=$console,$baudrate $othbootargs; "                    \
755         "tftp $ramdiskaddr $ramdiskfile;"                               \
756         "tftp $loadaddr $bootfile;"                                     \
757         "tftp $fdtaddr $fdtfile;"                                       \
758         "bootm $loadaddr $ramdiskaddr $fdtaddr"
759
760 #endif