1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
21 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
22 #elif CONFIG_SYS_CLK_FREQ == 33000000
23 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
26 #define CONFIG_SYS_IMMR 0xE0000000
28 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
29 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
30 #define CONFIG_SYS_MEMTEST_END 0x00100000
35 #define CONFIG_DDR_ECC /* support DDR ECC function */
36 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
37 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
40 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
41 * unselect it to use old spd_sdram.c
43 #define CONFIG_SYS_SPD_BUS_NUM 0
44 #define SPD_EEPROM_ADDRESS1 0x52
45 #define SPD_EEPROM_ADDRESS2 0x51
46 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
47 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
49 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
52 * 32-bit data path mode.
54 * Please note that using this mode for devices with the real density of 64-bit
55 * effectively reduces the amount of available memory due to the effect of
56 * wrapping around while translating address to row/columns, for example in the
57 * 256MB module the upper 128MB get aliased with contents of the lower
58 * 128MB); normally this define should be used for devices with real 32-bit
61 #undef CONFIG_DDR_32BIT
63 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
64 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
65 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
67 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
68 #undef CONFIG_DDR_2T_TIMING
71 * DDRCDR - DDR Control Driver Register
73 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
75 #if defined(CONFIG_SPD_EEPROM)
77 * Determine DDR configuration from I2C interface.
79 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
82 * Manually set up DDR parameters
84 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
85 #if defined(CONFIG_DDR_II)
86 #define CONFIG_SYS_DDRCDR 0x80080001
87 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
88 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
89 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
90 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
91 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
92 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
93 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
94 #define CONFIG_SYS_DDR_MODE 0x47d00432
95 #define CONFIG_SYS_DDR_MODE2 0x8000c000
96 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
97 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
98 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
100 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
101 | CSCONFIG_ROW_BIT_13 \
102 | CSCONFIG_COL_BIT_10)
103 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
104 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
105 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
106 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
108 #if defined(CONFIG_DDR_32BIT)
109 /* set burst length to 8 for 32-bit data path */
110 /* DLL,normal,seq,4/2.5, 8 burst len */
111 #define CONFIG_SYS_DDR_MODE 0x00000023
113 /* the default burst length is 4 - for 64-bit data path */
114 /* DLL,normal,seq,4/2.5, 4 burst len */
115 #define CONFIG_SYS_DDR_MODE 0x00000022
121 * SDRAM on the Local Bus
123 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
124 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
127 * FLASH on the Local Bus
129 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
130 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
132 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
133 | BR_PS_16 /* 16 bit port */ \
134 | BR_MS_GPCM /* MSEL = GPCM */ \
136 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
146 /* window base at flash base */
147 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
148 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
150 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
151 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
153 #undef CONFIG_SYS_FLASH_CHECKSUM
154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
160 #define CONFIG_SYS_RAMBOOT
162 #undef CONFIG_SYS_RAMBOOT
166 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
168 #define CONFIG_SYS_BCSR 0xE2400000
169 /* Access window base at BCSR base */
170 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
171 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
172 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
177 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
181 | OR_GPCM_TRLX_CLEAR \
182 | OR_GPCM_EHTR_CLEAR)
185 #define CONFIG_SYS_INIT_RAM_LOCK 1
186 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
187 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
189 #define CONFIG_SYS_GBL_DATA_OFFSET \
190 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
193 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
194 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
197 * Local Bus LCRR and LBCR regs
198 * LCRR: DLL bypass, Clock divider is 4
199 * External Local Bus rate is
200 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
202 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
203 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
204 #define CONFIG_SYS_LBC_LBCR 0x00000000
207 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
210 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
212 * Base Register 2 and Option Register 2 configure SDRAM.
213 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
216 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
217 * port-size = 32-bits = BR2[19:20] = 11
218 * no parity checking = BR2[21:22] = 00
219 * SDRAM for MSEL = BR2[24:26] = 011
222 * 0 4 8 12 16 20 24 28
223 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
226 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
227 | BR_PS_32 /* 32-bit port */ \
228 | BR_MS_SDRAM /* MSEL = SDRAM */ \
231 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
232 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
235 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
238 * 64MB mask for AM, OR2[0:7] = 1111 1100
239 * XAM, OR2[17:18] = 11
240 * 9 columns OR2[19-21] = 010
241 * 13 rows OR2[23-25] = 100
242 * EAD set for extra time OR[31] = 1
244 * 0 4 8 12 16 20 24 28
245 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
248 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
250 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
251 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
255 /* LB sdram refresh timer, about 6us */
256 #define CONFIG_SYS_LBC_LSRT 0x32000000
257 /* LB refresh timer prescal, 266MHz/32 */
258 #define CONFIG_SYS_LBC_MRTPR 0x20000000
260 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
270 * SDRAM Controller configuration sequence.
272 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
273 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
274 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
275 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
276 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
281 #define CONFIG_SYS_NS16550_SERIAL
282 #define CONFIG_SYS_NS16550_REG_SIZE 1
283 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
285 #define CONFIG_SYS_BAUDRATE_TABLE \
286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
292 #define CONFIG_SYS_I2C
293 #define CONFIG_SYS_I2C_FSL
294 #define CONFIG_SYS_FSL_I2C_SPEED 400000
295 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
296 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
297 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
298 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
299 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
300 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
303 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
305 /* GPIOs. Used as SPI chip selects */
306 #define CONFIG_SYS_GPIO1_PRELIM
307 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
308 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
311 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
312 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
313 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
314 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
317 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
321 * Addresses are mapped 1-1.
323 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
324 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
325 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
326 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
327 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
328 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
329 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
330 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
331 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
333 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
334 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
335 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
336 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
337 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
338 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
339 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
340 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
341 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
343 #if defined(CONFIG_PCI)
345 #define CONFIG_83XX_PCI_STREAMING
347 #undef CONFIG_EEPRO100
350 #if !defined(CONFIG_PCI_PNP)
351 #define PCI_ENET0_IOADDR 0xFIXME
352 #define PCI_ENET0_MEMADDR 0xFIXME
353 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
356 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
357 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
359 #endif /* CONFIG_PCI */
365 #if defined(CONFIG_TSEC_ENET)
367 #define CONFIG_GMII 1 /* MII PHY management */
368 #define CONFIG_TSEC1 1
369 #define CONFIG_TSEC1_NAME "TSEC0"
370 #define CONFIG_TSEC2 1
371 #define CONFIG_TSEC2_NAME "TSEC1"
372 #define TSEC1_PHY_ADDR 0
373 #define TSEC2_PHY_ADDR 1
374 #define TSEC1_PHYIDX 0
375 #define TSEC2_PHYIDX 0
376 #define TSEC1_FLAGS TSEC_GIGABIT
377 #define TSEC2_FLAGS TSEC_GIGABIT
379 /* Options are: TSEC[0-1] */
380 #define CONFIG_ETHPRIME "TSEC0"
382 #endif /* CONFIG_TSEC_ENET */
385 * Configure on-board RTC
387 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
388 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
393 #ifndef CONFIG_SYS_RAMBOOT
394 #define CONFIG_ENV_ADDR \
395 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
396 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
397 #define CONFIG_ENV_SIZE 0x2000
399 /* Address and size of Redundant Environment Sector */
400 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
401 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
404 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
405 #define CONFIG_ENV_SIZE 0x2000
408 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
409 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
414 #define CONFIG_BOOTP_BOOTFILESIZE
417 * Command line configuration.
420 #undef CONFIG_WATCHDOG /* watchdog disabled */
423 * Miscellaneous configurable options
425 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
428 * For booting Linux, the board info and command line data
429 * have to be in the first 256 MB of memory, since this is
430 * the maximum mapped by the Linux kernel during initialization.
432 /* Initial Memory map for Linux*/
433 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
434 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
436 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
439 #define CONFIG_SYS_HRCW_LOW (\
440 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
441 HRCWL_DDR_TO_SCB_CLK_1X1 |\
442 HRCWL_CSB_TO_CLKIN |\
444 HRCWL_CORE_TO_CSB_2X1)
446 #define CONFIG_SYS_HRCW_LOW (\
447 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
448 HRCWL_DDR_TO_SCB_CLK_1X1 |\
449 HRCWL_CSB_TO_CLKIN |\
451 HRCWL_CORE_TO_CSB_3X1)
453 #define CONFIG_SYS_HRCW_LOW (\
454 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
455 HRCWL_DDR_TO_SCB_CLK_1X1 |\
456 HRCWL_CSB_TO_CLKIN |\
458 HRCWL_CORE_TO_CSB_2X1)
460 #define CONFIG_SYS_HRCW_LOW (\
461 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
462 HRCWL_DDR_TO_SCB_CLK_1X1 |\
463 HRCWL_CSB_TO_CLKIN |\
465 HRCWL_CORE_TO_CSB_1X1)
467 #define CONFIG_SYS_HRCW_LOW (\
468 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
469 HRCWL_DDR_TO_SCB_CLK_1X1 |\
470 HRCWL_CSB_TO_CLKIN |\
472 HRCWL_CORE_TO_CSB_1X1)
475 #ifdef CONFIG_PCISLAVE
476 #define CONFIG_SYS_HRCW_HIGH (\
479 HRCWH_PCI1_ARBITER_DISABLE |\
480 HRCWH_PCI2_ARBITER_DISABLE |\
482 HRCWH_FROM_0X00000100 |\
483 HRCWH_BOOTSEQ_DISABLE |\
484 HRCWH_SW_WATCHDOG_DISABLE |\
485 HRCWH_ROM_LOC_LOCAL_16BIT |\
486 HRCWH_TSEC1M_IN_GMII |\
487 HRCWH_TSEC2M_IN_GMII)
489 #if defined(CONFIG_PCI_64BIT)
490 #define CONFIG_SYS_HRCW_HIGH (\
493 HRCWH_PCI1_ARBITER_ENABLE |\
494 HRCWH_PCI2_ARBITER_DISABLE |\
496 HRCWH_FROM_0X00000100 |\
497 HRCWH_BOOTSEQ_DISABLE |\
498 HRCWH_SW_WATCHDOG_DISABLE |\
499 HRCWH_ROM_LOC_LOCAL_16BIT |\
500 HRCWH_TSEC1M_IN_GMII |\
501 HRCWH_TSEC2M_IN_GMII)
503 #define CONFIG_SYS_HRCW_HIGH (\
506 HRCWH_PCI1_ARBITER_ENABLE |\
507 HRCWH_PCI2_ARBITER_ENABLE |\
509 HRCWH_FROM_0X00000100 |\
510 HRCWH_BOOTSEQ_DISABLE |\
511 HRCWH_SW_WATCHDOG_DISABLE |\
512 HRCWH_ROM_LOC_LOCAL_16BIT |\
513 HRCWH_TSEC1M_IN_GMII |\
514 HRCWH_TSEC2M_IN_GMII)
515 #endif /* CONFIG_PCI_64BIT */
516 #endif /* CONFIG_PCISLAVE */
521 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
522 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
523 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
524 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
525 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
526 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
528 /* System IO Config */
529 #define CONFIG_SYS_SICRH 0
530 #define CONFIG_SYS_SICRL SICRL_LDP_A
532 #define CONFIG_SYS_HID0_INIT 0x000000000
533 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
534 | HID0_ENABLE_INSTRUCTION_CACHE)
536 /* #define CONFIG_SYS_HID0_FINAL (\
537 HID0_ENABLE_INSTRUCTION_CACHE |\
539 HID0_ENABLE_ADDRESS_BROADCAST) */
541 #define CONFIG_SYS_HID2 HID2_HBE
542 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
544 /* DDR @ 0x00000000 */
545 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
548 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
553 /* PCI @ 0x80000000 */
555 #define CONFIG_PCI_INDIRECT_BRIDGE
556 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
559 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
563 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
565 | BATL_CACHEINHIBIT \
566 | BATL_GUARDEDSTORAGE)
567 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
572 #define CONFIG_SYS_IBAT1L (0)
573 #define CONFIG_SYS_IBAT1U (0)
574 #define CONFIG_SYS_IBAT2L (0)
575 #define CONFIG_SYS_IBAT2U (0)
578 #ifdef CONFIG_MPC83XX_PCI2
579 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
582 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
586 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
588 | BATL_CACHEINHIBIT \
589 | BATL_GUARDEDSTORAGE)
590 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
595 #define CONFIG_SYS_IBAT3L (0)
596 #define CONFIG_SYS_IBAT3U (0)
597 #define CONFIG_SYS_IBAT4L (0)
598 #define CONFIG_SYS_IBAT4U (0)
601 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
602 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
604 | BATL_CACHEINHIBIT \
605 | BATL_GUARDEDSTORAGE)
606 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
611 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
612 #define CONFIG_SYS_IBAT6L (0xF0000000 \
614 | BATL_MEMCOHERENCE \
615 | BATL_GUARDEDSTORAGE)
616 #define CONFIG_SYS_IBAT6U (0xF0000000 \
621 #define CONFIG_SYS_IBAT7L (0)
622 #define CONFIG_SYS_IBAT7U (0)
624 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
625 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
626 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
627 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
628 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
629 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
630 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
631 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
632 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
633 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
634 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
635 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
636 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
637 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
638 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
639 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
641 #if defined(CONFIG_CMD_KGDB)
642 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
646 * Environment Configuration
648 #define CONFIG_ENV_OVERWRITE
650 #if defined(CONFIG_TSEC_ENET)
651 #define CONFIG_HAS_ETH1
652 #define CONFIG_HAS_ETH0
655 #define CONFIG_HOSTNAME "mpc8349emds"
656 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
657 #define CONFIG_BOOTFILE "uImage"
659 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
661 #define CONFIG_PREBOOT "echo;" \
662 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
665 #define CONFIG_EXTRA_ENV_SETTINGS \
667 "hostname=mpc8349emds\0" \
668 "nfsargs=setenv bootargs root=/dev/nfs rw " \
669 "nfsroot=${serverip}:${rootpath}\0" \
670 "ramargs=setenv bootargs root=/dev/ram rw\0" \
671 "addip=setenv bootargs ${bootargs} " \
672 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
673 ":${hostname}:${netdev}:off panic=1\0" \
674 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
675 "flash_nfs=run nfsargs addip addtty;" \
676 "bootm ${kernel_addr}\0" \
677 "flash_self=run ramargs addip addtty;" \
678 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
679 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
681 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
682 "update=protect off fe000000 fe03ffff; " \
683 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
684 "upd=run load update\0" \
686 "fdtfile=mpc834x_mds.dtb\0" \
689 #define CONFIG_NFSBOOTCOMMAND \
690 "setenv bootargs root=/dev/nfs rw " \
691 "nfsroot=$serverip:$rootpath " \
692 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
699 #define CONFIG_RAMBOOTCOMMAND \
700 "setenv bootargs root=/dev/ram rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $ramdiskaddr $ramdiskfile;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"
707 #define CONFIG_BOOTCOMMAND "run flash_self"
709 #endif /* __CONFIG_H */