1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
25 #define CONFIG_DDR_ECC /* support DDR ECC function */
26 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
27 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
30 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
31 * unselect it to use old spd_sdram.c
33 #define CONFIG_SYS_SPD_BUS_NUM 0
34 #define SPD_EEPROM_ADDRESS1 0x52
35 #define SPD_EEPROM_ADDRESS2 0x51
36 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
37 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
39 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
42 * 32-bit data path mode.
44 * Please note that using this mode for devices with the real density of 64-bit
45 * effectively reduces the amount of available memory due to the effect of
46 * wrapping around while translating address to row/columns, for example in the
47 * 256MB module the upper 128MB get aliased with contents of the lower
48 * 128MB); normally this define should be used for devices with real 32-bit
51 #undef CONFIG_DDR_32BIT
53 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
55 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
56 #undef CONFIG_DDR_2T_TIMING
59 * DDRCDR - DDR Control Driver Register
61 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
63 #if defined(CONFIG_SPD_EEPROM)
65 * Determine DDR configuration from I2C interface.
67 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
70 * Manually set up DDR parameters
72 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
73 #if defined(CONFIG_DDR_II)
74 #define CONFIG_SYS_DDRCDR 0x80080001
75 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
76 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
77 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
78 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
79 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
80 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
81 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
82 #define CONFIG_SYS_DDR_MODE 0x47d00432
83 #define CONFIG_SYS_DDR_MODE2 0x8000c000
84 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
85 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
86 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
88 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
89 | CSCONFIG_ROW_BIT_13 \
90 | CSCONFIG_COL_BIT_10)
91 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
92 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
93 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
94 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
96 #if defined(CONFIG_DDR_32BIT)
97 /* set burst length to 8 for 32-bit data path */
98 /* DLL,normal,seq,4/2.5, 8 burst len */
99 #define CONFIG_SYS_DDR_MODE 0x00000023
101 /* the default burst length is 4 - for 64-bit data path */
102 /* DLL,normal,seq,4/2.5, 4 burst len */
103 #define CONFIG_SYS_DDR_MODE 0x00000022
109 * SDRAM on the Local Bus
111 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
112 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
115 * FLASH on the Local Bus
117 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
118 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
120 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
121 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
123 #undef CONFIG_SYS_FLASH_CHECKSUM
124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
129 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
130 #define CONFIG_SYS_RAMBOOT
132 #undef CONFIG_SYS_RAMBOOT
136 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
138 #define CONFIG_SYS_BCSR 0xE2400000
139 /* Access window base at BCSR base */
140 #define CONFIG_SYS_INIT_RAM_LOCK 1
141 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
142 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
144 #define CONFIG_SYS_GBL_DATA_OFFSET \
145 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
146 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
148 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
149 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
152 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
155 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
157 * Base Register 2 and Option Register 2 configure SDRAM.
158 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
161 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
162 * port-size = 32-bits = BR2[19:20] = 11
163 * no parity checking = BR2[21:22] = 00
164 * SDRAM for MSEL = BR2[24:26] = 011
167 * 0 4 8 12 16 20 24 28
168 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
172 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
175 * 64MB mask for AM, OR2[0:7] = 1111 1100
176 * XAM, OR2[17:18] = 11
177 * 9 columns OR2[19-21] = 010
178 * 13 rows OR2[23-25] = 100
179 * EAD set for extra time OR[31] = 1
181 * 0 4 8 12 16 20 24 28
182 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
186 /* LB sdram refresh timer, about 6us */
187 #define CONFIG_SYS_LBC_LSRT 0x32000000
188 /* LB refresh timer prescal, 266MHz/32 */
189 #define CONFIG_SYS_LBC_MRTPR 0x20000000
191 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
201 * SDRAM Controller configuration sequence.
203 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
204 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
205 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
206 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
207 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
212 #define CONFIG_SYS_NS16550_SERIAL
213 #define CONFIG_SYS_NS16550_REG_SIZE 1
214 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
216 #define CONFIG_SYS_BAUDRATE_TABLE \
217 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
223 #define CONFIG_SYS_I2C_LEGACY
224 #define CONFIG_SYS_I2C_FSL
225 #define CONFIG_SYS_FSL_I2C_SPEED 400000
226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
228 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
229 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
230 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
231 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
234 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
236 /* GPIOs. Used as SPI chip selects */
237 #define CONFIG_SYS_GPIO1_PRELIM
238 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
239 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
242 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
243 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
244 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
245 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
248 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
252 * Addresses are mapped 1-1.
254 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
255 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
256 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
257 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
258 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
259 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
260 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
261 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
262 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
264 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
265 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
266 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
267 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
268 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
269 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
270 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
271 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
272 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
274 #if defined(CONFIG_PCI)
276 #define CONFIG_83XX_PCI_STREAMING
279 #if !defined(CONFIG_PCI_PNP)
280 #define PCI_ENET0_IOADDR 0xFIXME
281 #define PCI_ENET0_MEMADDR 0xFIXME
282 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
285 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
287 #endif /* CONFIG_PCI */
293 #if defined(CONFIG_TSEC_ENET)
295 #define CONFIG_GMII 1 /* MII PHY management */
296 #define CONFIG_TSEC1 1
297 #define CONFIG_TSEC1_NAME "TSEC0"
298 #define CONFIG_TSEC2 1
299 #define CONFIG_TSEC2_NAME "TSEC1"
300 #define TSEC1_PHY_ADDR 0
301 #define TSEC2_PHY_ADDR 1
302 #define TSEC1_PHYIDX 0
303 #define TSEC2_PHYIDX 0
304 #define TSEC1_FLAGS TSEC_GIGABIT
305 #define TSEC2_FLAGS TSEC_GIGABIT
307 /* Options are: TSEC[0-1] */
308 #define CONFIG_ETHPRIME "TSEC0"
310 #endif /* CONFIG_TSEC_ENET */
313 * Configure on-board RTC
315 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
316 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
321 #ifndef CONFIG_SYS_RAMBOOT
322 /* Address and size of Redundant Environment Sector */
325 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
326 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
331 #define CONFIG_BOOTP_BOOTFILESIZE
333 #undef CONFIG_WATCHDOG /* watchdog disabled */
336 * Miscellaneous configurable options
338 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
341 * For booting Linux, the board info and command line data
342 * have to be in the first 256 MB of memory, since this is
343 * the maximum mapped by the Linux kernel during initialization.
345 /* Initial Memory map for Linux*/
346 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
347 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
349 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
354 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
355 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
356 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
357 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
359 /* System IO Config */
360 #define CONFIG_SYS_SICRH 0
361 #define CONFIG_SYS_SICRL SICRL_LDP_A
363 #if defined(CONFIG_CMD_KGDB)
364 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
368 * Environment Configuration
371 #if defined(CONFIG_TSEC_ENET)
372 #define CONFIG_HAS_ETH1
373 #define CONFIG_HAS_ETH0
376 #define CONFIG_HOSTNAME "mpc8349emds"
377 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
378 #define CONFIG_BOOTFILE "uImage"
380 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
382 #define CONFIG_EXTRA_ENV_SETTINGS \
384 "hostname=mpc8349emds\0" \
385 "nfsargs=setenv bootargs root=/dev/nfs rw " \
386 "nfsroot=${serverip}:${rootpath}\0" \
387 "ramargs=setenv bootargs root=/dev/ram rw\0" \
388 "addip=setenv bootargs ${bootargs} " \
389 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
390 ":${hostname}:${netdev}:off panic=1\0" \
391 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
392 "flash_nfs=run nfsargs addip addtty;" \
393 "bootm ${kernel_addr}\0" \
394 "flash_self=run ramargs addip addtty;" \
395 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
396 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
398 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
399 "update=protect off fe000000 fe03ffff; " \
400 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
401 "upd=run load update\0" \
403 "fdtfile=mpc834x_mds.dtb\0" \
406 #define CONFIG_NFSBOOTCOMMAND \
407 "setenv bootargs root=/dev/nfs rw " \
408 "nfsroot=$serverip:$rootpath " \
409 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
411 "console=$consoledev,$baudrate $othbootargs;" \
412 "tftp $loadaddr $bootfile;" \
413 "tftp $fdtaddr $fdtfile;" \
414 "bootm $loadaddr - $fdtaddr"
416 #define CONFIG_RAMBOOTCOMMAND \
417 "setenv bootargs root=/dev/ram rw " \
418 "console=$consoledev,$baudrate $othbootargs;" \
419 "tftp $ramdiskaddr $ramdiskfile;" \
420 "tftp $loadaddr $bootfile;" \
421 "tftp $fdtaddr $fdtfile;" \
422 "bootm $loadaddr $ramdiskaddr $fdtaddr"
424 #define CONFIG_BOOTCOMMAND "run flash_self"
426 #endif /* __CONFIG_H */