include/configs/MPC8349EMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2010
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * mpc8349emds board configuration file
   9  *
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19
  20 #if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666
  21 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  22 #elif CONFIG_SYS_CLK_FREQ == 33000000
  23 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  24 #endif
  25
  26 #define CONFIG_SYS_IMMR         0xE0000000
  27
  28 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  29 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  30 #define CONFIG_SYS_MEMTEST_END          0x00100000
  31
  32 /*
  33  * DDR Setup
  34  */
  35 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  36 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  37 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  38
  39 /*
  40  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  41  * unselect it to use old spd_sdram.c
  42  */
  43 #define CONFIG_SYS_SPD_BUS_NUM  0
  44 #define SPD_EEPROM_ADDRESS1     0x52
  45 #define SPD_EEPROM_ADDRESS2     0x51
  46 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  47 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  49 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  50
  51 /*
  52  * 32-bit data path mode.
  53  *
  54  * Please note that using this mode for devices with the real density of 64-bit
  55  * effectively reduces the amount of available memory due to the effect of
  56  * wrapping around while translating address to row/columns, for example in the
  57  * 256MB module the upper 128MB get aliased with contents of the lower
  58  * 128MB); normally this define should be used for devices with real 32-bit
  59  * data path.
  60  */
  61 #undef CONFIG_DDR_32BIT
  62
  63 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  64 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  67                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  68 #undef  CONFIG_DDR_2T_TIMING
  69
  70 /*
  71  * DDRCDR - DDR Control Driver Register
  72  */
  73 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  74
  75 #if defined(CONFIG_SPD_EEPROM)
  76 /*
  77  * Determine DDR configuration from I2C interface.
  78  */
  79 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  80 #else
  81 /*
  82  * Manually set up DDR parameters
  83  */
  84 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  85 #if defined(CONFIG_DDR_II)
  86 #define CONFIG_SYS_DDRCDR               0x80080001
  87 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  88 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  89 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
  90 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
  91 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  92 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  93 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  94 #define CONFIG_SYS_DDR_MODE             0x47d00432
  95 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  96 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  97 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  98 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  99 #else
 100 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 101                                 | CSCONFIG_ROW_BIT_13 \
 102                                 | CSCONFIG_COL_BIT_10)
 103 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 104 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 105 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 106 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 107
 108 #if defined(CONFIG_DDR_32BIT)
 109 /* set burst length to 8 for 32-bit data path */
 110                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 111 #define CONFIG_SYS_DDR_MODE     0x00000023
 112 #else
 113 /* the default burst length is 4 - for 64-bit data path */
 114                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 115 #define CONFIG_SYS_DDR_MODE     0x00000022
 116 #endif
 117 #endif
 118 #endif
 119
 120 /*
 121  * SDRAM on the Local Bus
 122  */
 123 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 124 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 125
 126 /*
 127  * FLASH on the Local Bus
 128  */
 129 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 130 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 131
 132 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 133                                 | BR_PS_16      /* 16 bit port  */ \
 134                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 135                                 | BR_V)         /* valid */
 136 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 137                                 | OR_UPM_XAM \
 138                                 | OR_GPCM_CSNT \
 139                                 | OR_GPCM_ACS_DIV2 \
 140                                 | OR_GPCM_XACS \
 141                                 | OR_GPCM_SCY_15 \
 142                                 | OR_GPCM_TRLX_SET \
 143                                 | OR_GPCM_EHTR_SET \
 144                                 | OR_GPCM_EAD)
 145
 146                                         /* window base at flash base */
 147 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 148 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 149
 150 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 151 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 152
 153 #undef CONFIG_SYS_FLASH_CHECKSUM
 154 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 155 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 156
 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 158
 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 160 #define CONFIG_SYS_RAMBOOT
 161 #else
 162 #undef  CONFIG_SYS_RAMBOOT
 163 #endif
 164
 165 /*
 166  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 167  */
 168 #define CONFIG_SYS_BCSR                 0xE2400000
 169                                         /* Access window base at BCSR base */
 170 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 171 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 172 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 173                                         | BR_PS_8 \
 174                                         | BR_MS_GPCM \
 175                                         | BR_V)
 176                                         /* 0x00000801 */
 177 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 178                                         | OR_GPCM_XAM \
 179                                         | OR_GPCM_CSNT \
 180                                         | OR_GPCM_SCY_15 \
 181                                         | OR_GPCM_TRLX_CLEAR \
 182                                         | OR_GPCM_EHTR_CLEAR)
 183                                         /* 0xFFFFE8F0 */
 184
 185 #define CONFIG_SYS_INIT_RAM_LOCK        1
 186 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 187 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 188
 189 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 190                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 191 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 192
 193 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 194 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 195
 196 /*
 197  * Local Bus LCRR and LBCR regs
 198  *    LCRR:  DLL bypass, Clock divider is 4
 199  * External Local Bus rate is
 200  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 201  */
 202 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 203 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 204 #define CONFIG_SYS_LBC_LBCR     0x00000000
 205
 206 /*
 207  * Serial Port
 208  */
 209 #define CONFIG_SYS_NS16550_SERIAL
 210 #define CONFIG_SYS_NS16550_REG_SIZE    1
 211 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 212
 213 #define CONFIG_SYS_BAUDRATE_TABLE  \
 214                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 215
 216 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 217 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 218
 219 /* I2C */
 220 #define CONFIG_SYS_I2C
 221 #define CONFIG_SYS_I2C_FSL
 222 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 223 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 224 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 225 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 226 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 227 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 228 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 229
 230 /* SPI */
 231 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 232
 233 /* GPIOs.  Used as SPI chip selects */
 234 #define CONFIG_SYS_GPIO1_PRELIM
 235 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 236 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 237
 238 /* TSEC */
 239 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 240 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 241 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 242 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 243
 244 /* USB */
 245 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 246
 247 /*
 248  * General PCI
 249  * Addresses are mapped 1-1.
 250  */
 251 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 252 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 253 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 254 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 255 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 256 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 257 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 258 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 259 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 260
 261 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 262 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 263 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 264 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 265 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 266 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 267 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 268 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 269 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 270
 271 #if defined(CONFIG_PCI)
 272
 273 #define CONFIG_83XX_PCI_STREAMING
 274
 275 #undef CONFIG_EEPRO100
 276 #undef CONFIG_TULIP
 277
 278 #if !defined(CONFIG_PCI_PNP)
 279         #define PCI_ENET0_IOADDR        0xFIXME
 280         #define PCI_ENET0_MEMADDR       0xFIXME
 281         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 282 #endif
 283
 284 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 285 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 286
 287 #endif  /* CONFIG_PCI */
 288
 289 /*
 290  * TSEC configuration
 291  */
 292
 293 #if defined(CONFIG_TSEC_ENET)
 294
 295 #define CONFIG_GMII             1       /* MII PHY management */
 296 #define CONFIG_TSEC1            1
 297 #define CONFIG_TSEC1_NAME       "TSEC0"
 298 #define CONFIG_TSEC2            1
 299 #define CONFIG_TSEC2_NAME       "TSEC1"
 300 #define TSEC1_PHY_ADDR          0
 301 #define TSEC2_PHY_ADDR          1
 302 #define TSEC1_PHYIDX            0
 303 #define TSEC2_PHYIDX            0
 304 #define TSEC1_FLAGS             TSEC_GIGABIT
 305 #define TSEC2_FLAGS             TSEC_GIGABIT
 306
 307 /* Options are: TSEC[0-1] */
 308 #define CONFIG_ETHPRIME         "TSEC0"
 309
 310 #endif  /* CONFIG_TSEC_ENET */
 311
 312 /*
 313  * Configure on-board RTC
 314  */
 315 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 316 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 317
 318 /*
 319  * Environment
 320  */
 321 #ifndef CONFIG_SYS_RAMBOOT
 322         #define CONFIG_ENV_ADDR         \
 323                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 324         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 325         #define CONFIG_ENV_SIZE         0x2000
 326
 327 /* Address and size of Redundant Environment Sector     */
 328 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 329 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 330
 331 #else
 332         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 333         #define CONFIG_ENV_SIZE         0x2000
 334 #endif
 335
 336 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 337 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 338
 339 /*
 340  * BOOTP options
 341  */
 342 #define CONFIG_BOOTP_BOOTFILESIZE
 343
 344 /*
 345  * Command line configuration.
 346  */
 347
 348 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 349
 350 /*
 351  * Miscellaneous configurable options
 352  */
 353 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 354
 355 /*
 356  * For booting Linux, the board info and command line data
 357  * have to be in the first 256 MB of memory, since this is
 358  * the maximum mapped by the Linux kernel during initialization.
 359  */
 360                                 /* Initial Memory map for Linux*/
 361 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 362 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 363
 364 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 365
 366 #if 1 /*528/264*/
 367 #define CONFIG_SYS_HRCW_LOW (\
 368         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 369         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 370         HRCWL_CSB_TO_CLKIN |\
 371         HRCWL_VCO_1X2 |\
 372         HRCWL_CORE_TO_CSB_2X1)
 373 #elif 0 /*396/132*/
 374 #define CONFIG_SYS_HRCW_LOW (\
 375         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 376         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 377         HRCWL_CSB_TO_CLKIN |\
 378         HRCWL_VCO_1X4 |\
 379         HRCWL_CORE_TO_CSB_3X1)
 380 #elif 0 /*264/132*/
 381 #define CONFIG_SYS_HRCW_LOW (\
 382         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 383         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 384         HRCWL_CSB_TO_CLKIN |\
 385         HRCWL_VCO_1X4 |\
 386         HRCWL_CORE_TO_CSB_2X1)
 387 #elif 0 /*132/132*/
 388 #define CONFIG_SYS_HRCW_LOW (\
 389         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 390         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 391         HRCWL_CSB_TO_CLKIN |\
 392         HRCWL_VCO_1X4 |\
 393         HRCWL_CORE_TO_CSB_1X1)
 394 #elif 0 /*264/264 */
 395 #define CONFIG_SYS_HRCW_LOW (\
 396         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 397         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 398         HRCWL_CSB_TO_CLKIN |\
 399         HRCWL_VCO_1X4 |\
 400         HRCWL_CORE_TO_CSB_1X1)
 401 #endif
 402
 403 #ifdef CONFIG_PCISLAVE
 404 #define CONFIG_SYS_HRCW_HIGH (\
 405         HRCWH_PCI_AGENT |\
 406         HRCWH_64_BIT_PCI |\
 407         HRCWH_PCI1_ARBITER_DISABLE |\
 408         HRCWH_PCI2_ARBITER_DISABLE |\
 409         HRCWH_CORE_ENABLE |\
 410         HRCWH_FROM_0X00000100 |\
 411         HRCWH_BOOTSEQ_DISABLE |\
 412         HRCWH_SW_WATCHDOG_DISABLE |\
 413         HRCWH_ROM_LOC_LOCAL_16BIT |\
 414         HRCWH_TSEC1M_IN_GMII |\
 415         HRCWH_TSEC2M_IN_GMII)
 416 #else
 417 #if defined(CONFIG_PCI_64BIT)
 418 #define CONFIG_SYS_HRCW_HIGH (\
 419         HRCWH_PCI_HOST |\
 420         HRCWH_64_BIT_PCI |\
 421         HRCWH_PCI1_ARBITER_ENABLE |\
 422         HRCWH_PCI2_ARBITER_DISABLE |\
 423         HRCWH_CORE_ENABLE |\
 424         HRCWH_FROM_0X00000100 |\
 425         HRCWH_BOOTSEQ_DISABLE |\
 426         HRCWH_SW_WATCHDOG_DISABLE |\
 427         HRCWH_ROM_LOC_LOCAL_16BIT |\
 428         HRCWH_TSEC1M_IN_GMII |\
 429         HRCWH_TSEC2M_IN_GMII)
 430 #else
 431 #define CONFIG_SYS_HRCW_HIGH (\
 432         HRCWH_PCI_HOST |\
 433         HRCWH_32_BIT_PCI |\
 434         HRCWH_PCI1_ARBITER_ENABLE |\
 435         HRCWH_PCI2_ARBITER_ENABLE |\
 436         HRCWH_CORE_ENABLE |\
 437         HRCWH_FROM_0X00000100 |\
 438         HRCWH_BOOTSEQ_DISABLE |\
 439         HRCWH_SW_WATCHDOG_DISABLE |\
 440         HRCWH_ROM_LOC_LOCAL_16BIT |\
 441         HRCWH_TSEC1M_IN_GMII |\
 442         HRCWH_TSEC2M_IN_GMII)
 443 #endif /* CONFIG_PCI_64BIT */
 444 #endif /* CONFIG_PCISLAVE */
 445
 446 /*
 447  * System performance
 448  */
 449 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 450 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 451 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 452 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 453 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 454 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 455
 456 /* System IO Config */
 457 #define CONFIG_SYS_SICRH 0
 458 #define CONFIG_SYS_SICRL SICRL_LDP_A
 459
 460 #define CONFIG_SYS_HID0_INIT    0x000000000
 461 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 462                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 463
 464 /* #define CONFIG_SYS_HID0_FINAL        (\
 465         HID0_ENABLE_INSTRUCTION_CACHE |\
 466         HID0_ENABLE_M_BIT |\
 467         HID0_ENABLE_ADDRESS_BROADCAST) */
 468
 469 #define CONFIG_SYS_HID2 HID2_HBE
 470 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 471
 472 /* DDR @ 0x00000000 */
 473 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 474                                 | BATL_PP_RW \
 475                                 | BATL_MEMCOHERENCE)
 476 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 477                                 | BATU_BL_256M \
 478                                 | BATU_VS \
 479                                 | BATU_VP)
 480
 481 /* PCI @ 0x80000000 */
 482 #ifdef CONFIG_PCI
 483 #define CONFIG_PCI_INDIRECT_BRIDGE
 484 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 485                                 | BATL_PP_RW \
 486                                 | BATL_MEMCOHERENCE)
 487 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 488                                 | BATU_BL_256M \
 489                                 | BATU_VS \
 490                                 | BATU_VP)
 491 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 492                                 | BATL_PP_RW \
 493                                 | BATL_CACHEINHIBIT \
 494                                 | BATL_GUARDEDSTORAGE)
 495 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 496                                 | BATU_BL_256M \
 497                                 | BATU_VS \
 498                                 | BATU_VP)
 499 #else
 500 #define CONFIG_SYS_IBAT1L       (0)
 501 #define CONFIG_SYS_IBAT1U       (0)
 502 #define CONFIG_SYS_IBAT2L       (0)
 503 #define CONFIG_SYS_IBAT2U       (0)
 504 #endif
 505
 506 #ifdef CONFIG_MPC83XX_PCI2
 507 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 508                                 | BATL_PP_RW \
 509                                 | BATL_MEMCOHERENCE)
 510 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 511                                 | BATU_BL_256M \
 512                                 | BATU_VS \
 513                                 | BATU_VP)
 514 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 515                                 | BATL_PP_RW \
 516                                 | BATL_CACHEINHIBIT \
 517                                 | BATL_GUARDEDSTORAGE)
 518 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 519                                 | BATU_BL_256M \
 520                                 | BATU_VS \
 521                                 | BATU_VP)
 522 #else
 523 #define CONFIG_SYS_IBAT3L       (0)
 524 #define CONFIG_SYS_IBAT3U       (0)
 525 #define CONFIG_SYS_IBAT4L       (0)
 526 #define CONFIG_SYS_IBAT4U       (0)
 527 #endif
 528
 529 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 530 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 531                                 | BATL_PP_RW \
 532                                 | BATL_CACHEINHIBIT \
 533                                 | BATL_GUARDEDSTORAGE)
 534 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 535                                 | BATU_BL_256M \
 536                                 | BATU_VS \
 537                                 | BATU_VP)
 538
 539 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 540 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 541                                 | BATL_PP_RW \
 542                                 | BATL_MEMCOHERENCE \
 543                                 | BATL_GUARDEDSTORAGE)
 544 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 545                                 | BATU_BL_256M \
 546                                 | BATU_VS \
 547                                 | BATU_VP)
 548
 549 #define CONFIG_SYS_IBAT7L       (0)
 550 #define CONFIG_SYS_IBAT7U       (0)
 551
 552 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 553 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 554 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 555 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 556 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 557 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 558 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 559 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 560 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 561 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 562 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 563 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 564 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 565 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 566 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 567 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 568
 569 #if defined(CONFIG_CMD_KGDB)
 570 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 571 #endif
 572
 573 /*
 574  * Environment Configuration
 575  */
 576 #define CONFIG_ENV_OVERWRITE
 577
 578 #if defined(CONFIG_TSEC_ENET)
 579 #define CONFIG_HAS_ETH1
 580 #define CONFIG_HAS_ETH0
 581 #endif
 582
 583 #define CONFIG_HOSTNAME         "mpc8349emds"
 584 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 585 #define CONFIG_BOOTFILE         "uImage"
 586
 587 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 588
 589 #define CONFIG_PREBOOT  "echo;" \
 590         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 591         "echo"
 592
 593 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 594         "netdev=eth0\0"                                                 \
 595         "hostname=mpc8349emds\0"                                        \
 596         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 597                 "nfsroot=${serverip}:${rootpath}\0"                     \
 598         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 599         "addip=setenv bootargs ${bootargs} "                            \
 600                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 601                 ":${hostname}:${netdev}:off panic=1\0"                  \
 602         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 603         "flash_nfs=run nfsargs addip addtty;"                           \
 604                 "bootm ${kernel_addr}\0"                                \
 605         "flash_self=run ramargs addip addtty;"                          \
 606                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 607         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 608                 "bootm\0"                                               \
 609         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 610         "update=protect off fe000000 fe03ffff; "                        \
 611                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 612         "upd=run load update\0"                                         \
 613         "fdtaddr=780000\0"                                              \
 614         "fdtfile=mpc834x_mds.dtb\0"                                     \
 615         ""
 616
 617 #define CONFIG_NFSBOOTCOMMAND                                           \
 618         "setenv bootargs root=/dev/nfs rw "                             \
 619                 "nfsroot=$serverip:$rootpath "                          \
 620                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 621                                                         "$netdev:off "  \
 622                 "console=$consoledev,$baudrate $othbootargs;"           \
 623         "tftp $loadaddr $bootfile;"                                     \
 624         "tftp $fdtaddr $fdtfile;"                                       \
 625         "bootm $loadaddr - $fdtaddr"
 626
 627 #define CONFIG_RAMBOOTCOMMAND                                           \
 628         "setenv bootargs root=/dev/ram rw "                             \
 629                 "console=$consoledev,$baudrate $othbootargs;"           \
 630         "tftp $ramdiskaddr $ramdiskfile;"                               \
 631         "tftp $loadaddr $bootfile;"                                     \
 632         "tftp $fdtaddr $fdtfile;"                                       \
 633         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 634
 635 #define CONFIG_BOOTCOMMAND      "run flash_self"
 636
 637 #endif  /* __CONFIG_H */