Move defaults from config_cmd_default.h to Kconfig
[platform/kernel/u-boot.git] / include / configs / MPC8349EMDS.h
1 /*
2  * (C) Copyright 2006-2010
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * mpc8349emds board configuration file
10  *
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 #define CONFIG_SYS_GENERIC_BOARD
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 /*
20  * High Level Configuration Options
21  */
22 #define CONFIG_E300             1       /* E300 Family */
23 #define CONFIG_MPC834x          1       /* MPC834x family */
24 #define CONFIG_MPC8349          1       /* MPC8349 specific */
25 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
26
27 #define CONFIG_SYS_TEXT_BASE    0xFE000000
28
29 #define CONFIG_PCI_66M
30 #ifdef CONFIG_PCI_66M
31 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
32 #else
33 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
34 #endif
35
36 #ifdef CONFIG_PCISLAVE
37 #define CONFIG_PCI
38 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
39 #endif /* CONFIG_PCISLAVE */
40
41 #ifndef CONFIG_SYS_CLK_FREQ
42 #ifdef CONFIG_PCI_66M
43 #define CONFIG_SYS_CLK_FREQ     66000000
44 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
45 #else
46 #define CONFIG_SYS_CLK_FREQ     33000000
47 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
48 #endif
49 #endif
50
51 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
52
53 #define CONFIG_SYS_IMMR         0xE0000000
54
55 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
56 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
57 #define CONFIG_SYS_MEMTEST_END          0x00100000
58
59 /*
60  * DDR Setup
61  */
62 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
63 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
64 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
65
66 /*
67  * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
68  * undefine it to use old spd_sdram.c
69  */
70 #define CONFIG_SYS_FSL_DDR2
71 #ifdef CONFIG_SYS_FSL_DDR2
72 #define CONFIG_SYS_FSL_DDRC_GEN2
73 #define CONFIG_SYS_SPD_BUS_NUM  0
74 #define SPD_EEPROM_ADDRESS1     0x52
75 #define SPD_EEPROM_ADDRESS2     0x51
76 #define CONFIG_NUM_DDR_CONTROLLERS      1
77 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
78 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
79 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
80 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
81 #endif
82
83 /*
84  * 32-bit data path mode.
85  *
86  * Please note that using this mode for devices with the real density of 64-bit
87  * effectively reduces the amount of available memory due to the effect of
88  * wrapping around while translating address to row/columns, for example in the
89  * 256MB module the upper 128MB get aliased with contents of the lower
90  * 128MB); normally this define should be used for devices with real 32-bit
91  * data path.
92  */
93 #undef CONFIG_DDR_32BIT
94
95 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
96 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
97 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
98 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
99                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
100 #undef  CONFIG_DDR_2T_TIMING
101
102 /*
103  * DDRCDR - DDR Control Driver Register
104  */
105 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
106
107 #if defined(CONFIG_SPD_EEPROM)
108 /*
109  * Determine DDR configuration from I2C interface.
110  */
111 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
112 #else
113 /*
114  * Manually set up DDR parameters
115  */
116 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
117 #if defined(CONFIG_DDR_II)
118 #define CONFIG_SYS_DDRCDR               0x80080001
119 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
120 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
121 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
122 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
123 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
124 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
125 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
126 #define CONFIG_SYS_DDR_MODE             0x47d00432
127 #define CONFIG_SYS_DDR_MODE2            0x8000c000
128 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
129 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
130 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
131 #else
132 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
133                                 | CSCONFIG_ROW_BIT_13 \
134                                 | CSCONFIG_COL_BIT_10)
135 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
136 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
137 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
138 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
139
140 #if defined(CONFIG_DDR_32BIT)
141 /* set burst length to 8 for 32-bit data path */
142                                 /* DLL,normal,seq,4/2.5, 8 burst len */
143 #define CONFIG_SYS_DDR_MODE     0x00000023
144 #else
145 /* the default burst length is 4 - for 64-bit data path */
146                                 /* DLL,normal,seq,4/2.5, 4 burst len */
147 #define CONFIG_SYS_DDR_MODE     0x00000022
148 #endif
149 #endif
150 #endif
151
152 /*
153  * SDRAM on the Local Bus
154  */
155 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
156 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
157
158 /*
159  * FLASH on the Local Bus
160  */
161 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
162 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
163 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
164 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
165 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
166 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
167
168 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
169                                 | BR_PS_16      /* 16 bit port  */ \
170                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
171                                 | BR_V)         /* valid */
172 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
173                                 | OR_UPM_XAM \
174                                 | OR_GPCM_CSNT \
175                                 | OR_GPCM_ACS_DIV2 \
176                                 | OR_GPCM_XACS \
177                                 | OR_GPCM_SCY_15 \
178                                 | OR_GPCM_TRLX_SET \
179                                 | OR_GPCM_EHTR_SET \
180                                 | OR_GPCM_EAD)
181
182                                         /* window base at flash base */
183 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
184 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
185
186 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
187 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
188
189 #undef CONFIG_SYS_FLASH_CHECKSUM
190 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
191 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
192
193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
194
195 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
196 #define CONFIG_SYS_RAMBOOT
197 #else
198 #undef  CONFIG_SYS_RAMBOOT
199 #endif
200
201 /*
202  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
203  */
204 #define CONFIG_SYS_BCSR                 0xE2400000
205                                         /* Access window base at BCSR base */
206 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
207 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
208 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
209                                         | BR_PS_8 \
210                                         | BR_MS_GPCM \
211                                         | BR_V)
212                                         /* 0x00000801 */
213 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
214                                         | OR_GPCM_XAM \
215                                         | OR_GPCM_CSNT \
216                                         | OR_GPCM_SCY_15 \
217                                         | OR_GPCM_TRLX_CLEAR \
218                                         | OR_GPCM_EHTR_CLEAR)
219                                         /* 0xFFFFE8F0 */
220
221 #define CONFIG_SYS_INIT_RAM_LOCK        1
222 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
223 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
224
225 #define CONFIG_SYS_GBL_DATA_OFFSET      \
226                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
227 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
228
229 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
230 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
231
232 /*
233  * Local Bus LCRR and LBCR regs
234  *    LCRR:  DLL bypass, Clock divider is 4
235  * External Local Bus rate is
236  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
237  */
238 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
239 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
240 #define CONFIG_SYS_LBC_LBCR     0x00000000
241
242 /*
243  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
244  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
245  */
246 #undef CONFIG_SYS_LB_SDRAM
247
248 #ifdef CONFIG_SYS_LB_SDRAM
249 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
250 /*
251  * Base Register 2 and Option Register 2 configure SDRAM.
252  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
253  *
254  * For BR2, need:
255  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
256  *    port-size = 32-bits = BR2[19:20] = 11
257  *    no parity checking = BR2[21:22] = 00
258  *    SDRAM for MSEL = BR2[24:26] = 011
259  *    Valid = BR[31] = 1
260  *
261  * 0    4    8    12   16   20   24   28
262  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
263  */
264
265 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
266                                         | BR_PS_32      /* 32-bit port */ \
267                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
268                                         | BR_V)         /* Valid */
269                                         /* 0xF0001861 */
270 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
271 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
272
273 /*
274  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
275  *
276  * For OR2, need:
277  *    64MB mask for AM, OR2[0:7] = 1111 1100
278  *                 XAM, OR2[17:18] = 11
279  *    9 columns OR2[19-21] = 010
280  *    13 rows   OR2[23-25] = 100
281  *    EAD set for extra time OR[31] = 1
282  *
283  * 0    4    8    12   16   20   24   28
284  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
285  */
286
287 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
288                         | OR_SDRAM_XAM \
289                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
290                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
291                         | OR_SDRAM_EAD)
292                         /* 0xFC006901 */
293
294                                 /* LB sdram refresh timer, about 6us */
295 #define CONFIG_SYS_LBC_LSRT     0x32000000
296                                 /* LB refresh timer prescal, 266MHz/32 */
297 #define CONFIG_SYS_LBC_MRTPR    0x20000000
298
299 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
300                                 | LSDMR_BSMA1516        \
301                                 | LSDMR_RFCR8           \
302                                 | LSDMR_PRETOACT6       \
303                                 | LSDMR_ACTTORW3        \
304                                 | LSDMR_BL8             \
305                                 | LSDMR_WRC3            \
306                                 | LSDMR_CL3)
307
308 /*
309  * SDRAM Controller configuration sequence.
310  */
311 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
312 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
313 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
314 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
315 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
316 #endif
317
318 /*
319  * Serial Port
320  */
321 #define CONFIG_CONS_INDEX     1
322 #define CONFIG_SYS_NS16550
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE    1
325 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
326
327 #define CONFIG_SYS_BAUDRATE_TABLE  \
328                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
329
330 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
331 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
332
333 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
334 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
335 /* Use the HUSH parser */
336 #define CONFIG_SYS_HUSH_PARSER
337
338 /* pass open firmware flat tree */
339 #define CONFIG_OF_LIBFDT        1
340 #define CONFIG_OF_BOARD_SETUP   1
341 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
342
343 /* I2C */
344 #define CONFIG_SYS_I2C
345 #define CONFIG_SYS_I2C_FSL
346 #define CONFIG_SYS_FSL_I2C_SPEED        400000
347 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
348 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
349 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
350 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
351 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
352 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
353
354 /* SPI */
355 #define CONFIG_MPC8XXX_SPI
356 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
357
358 /* GPIOs.  Used as SPI chip selects */
359 #define CONFIG_SYS_GPIO1_PRELIM
360 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
361 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
362
363 /* TSEC */
364 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
365 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
366 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
367 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
368
369 /* USB */
370 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
371
372 /*
373  * General PCI
374  * Addresses are mapped 1-1.
375  */
376 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
377 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
378 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
379 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
380 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
381 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
382 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
383 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
384 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
385
386 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
387 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
388 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
389 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
390 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
391 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
392 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
393 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
394 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
395
396 #if defined(CONFIG_PCI)
397
398 #define PCI_ONE_PCI1
399 #if defined(PCI_64BIT)
400 #undef PCI_ALL_PCI1
401 #undef PCI_TWO_PCI1
402 #undef PCI_ONE_PCI1
403 #endif
404
405 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
406 #define CONFIG_83XX_PCI_STREAMING
407
408 #undef CONFIG_EEPRO100
409 #undef CONFIG_TULIP
410
411 #if !defined(CONFIG_PCI_PNP)
412         #define PCI_ENET0_IOADDR        0xFIXME
413         #define PCI_ENET0_MEMADDR       0xFIXME
414         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
415 #endif
416
417 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
418 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
419
420 #endif  /* CONFIG_PCI */
421
422 /*
423  * TSEC configuration
424  */
425 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
426
427 #if defined(CONFIG_TSEC_ENET)
428
429 #define CONFIG_GMII             1       /* MII PHY management */
430 #define CONFIG_TSEC1            1
431 #define CONFIG_TSEC1_NAME       "TSEC0"
432 #define CONFIG_TSEC2            1
433 #define CONFIG_TSEC2_NAME       "TSEC1"
434 #define TSEC1_PHY_ADDR          0
435 #define TSEC2_PHY_ADDR          1
436 #define TSEC1_PHYIDX            0
437 #define TSEC2_PHYIDX            0
438 #define TSEC1_FLAGS             TSEC_GIGABIT
439 #define TSEC2_FLAGS             TSEC_GIGABIT
440
441 /* Options are: TSEC[0-1] */
442 #define CONFIG_ETHPRIME         "TSEC0"
443
444 #endif  /* CONFIG_TSEC_ENET */
445
446 /*
447  * Configure on-board RTC
448  */
449 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
450 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
451
452 /*
453  * Environment
454  */
455 #ifndef CONFIG_SYS_RAMBOOT
456         #define CONFIG_ENV_IS_IN_FLASH  1
457         #define CONFIG_ENV_ADDR         \
458                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
459         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
460         #define CONFIG_ENV_SIZE         0x2000
461
462 /* Address and size of Redundant Environment Sector     */
463 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
464 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
465
466 #else
467         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
468         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
469         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
470         #define CONFIG_ENV_SIZE         0x2000
471 #endif
472
473 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
474 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
475
476
477 /*
478  * BOOTP options
479  */
480 #define CONFIG_BOOTP_BOOTFILESIZE
481 #define CONFIG_BOOTP_BOOTPATH
482 #define CONFIG_BOOTP_GATEWAY
483 #define CONFIG_BOOTP_HOSTNAME
484
485
486 /*
487  * Command line configuration.
488  */
489 #define CONFIG_CMD_PING
490 #define CONFIG_CMD_I2C
491 #define CONFIG_CMD_DATE
492 #define CONFIG_CMD_MII
493
494 #if defined(CONFIG_PCI)
495     #define CONFIG_CMD_PCI
496 #endif
497
498 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
499
500 /*
501  * Miscellaneous configurable options
502  */
503 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
504 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
505
506 #if defined(CONFIG_CMD_KGDB)
507         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
508 #else
509         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
510 #endif
511
512                                 /* Print Buffer Size */
513 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
514 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
515                                 /* Boot Argument Buffer Size */
516 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
517
518 /*
519  * For booting Linux, the board info and command line data
520  * have to be in the first 256 MB of memory, since this is
521  * the maximum mapped by the Linux kernel during initialization.
522  */
523                                 /* Initial Memory map for Linux*/
524 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
525
526 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
527
528 #if 1 /*528/264*/
529 #define CONFIG_SYS_HRCW_LOW (\
530         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
531         HRCWL_DDR_TO_SCB_CLK_1X1 |\
532         HRCWL_CSB_TO_CLKIN |\
533         HRCWL_VCO_1X2 |\
534         HRCWL_CORE_TO_CSB_2X1)
535 #elif 0 /*396/132*/
536 #define CONFIG_SYS_HRCW_LOW (\
537         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
538         HRCWL_DDR_TO_SCB_CLK_1X1 |\
539         HRCWL_CSB_TO_CLKIN |\
540         HRCWL_VCO_1X4 |\
541         HRCWL_CORE_TO_CSB_3X1)
542 #elif 0 /*264/132*/
543 #define CONFIG_SYS_HRCW_LOW (\
544         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
545         HRCWL_DDR_TO_SCB_CLK_1X1 |\
546         HRCWL_CSB_TO_CLKIN |\
547         HRCWL_VCO_1X4 |\
548         HRCWL_CORE_TO_CSB_2X1)
549 #elif 0 /*132/132*/
550 #define CONFIG_SYS_HRCW_LOW (\
551         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
552         HRCWL_DDR_TO_SCB_CLK_1X1 |\
553         HRCWL_CSB_TO_CLKIN |\
554         HRCWL_VCO_1X4 |\
555         HRCWL_CORE_TO_CSB_1X1)
556 #elif 0 /*264/264 */
557 #define CONFIG_SYS_HRCW_LOW (\
558         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
559         HRCWL_DDR_TO_SCB_CLK_1X1 |\
560         HRCWL_CSB_TO_CLKIN |\
561         HRCWL_VCO_1X4 |\
562         HRCWL_CORE_TO_CSB_1X1)
563 #endif
564
565 #ifdef CONFIG_PCISLAVE
566 #define CONFIG_SYS_HRCW_HIGH (\
567         HRCWH_PCI_AGENT |\
568         HRCWH_64_BIT_PCI |\
569         HRCWH_PCI1_ARBITER_DISABLE |\
570         HRCWH_PCI2_ARBITER_DISABLE |\
571         HRCWH_CORE_ENABLE |\
572         HRCWH_FROM_0X00000100 |\
573         HRCWH_BOOTSEQ_DISABLE |\
574         HRCWH_SW_WATCHDOG_DISABLE |\
575         HRCWH_ROM_LOC_LOCAL_16BIT |\
576         HRCWH_TSEC1M_IN_GMII |\
577         HRCWH_TSEC2M_IN_GMII)
578 #else
579 #if defined(PCI_64BIT)
580 #define CONFIG_SYS_HRCW_HIGH (\
581         HRCWH_PCI_HOST |\
582         HRCWH_64_BIT_PCI |\
583         HRCWH_PCI1_ARBITER_ENABLE |\
584         HRCWH_PCI2_ARBITER_DISABLE |\
585         HRCWH_CORE_ENABLE |\
586         HRCWH_FROM_0X00000100 |\
587         HRCWH_BOOTSEQ_DISABLE |\
588         HRCWH_SW_WATCHDOG_DISABLE |\
589         HRCWH_ROM_LOC_LOCAL_16BIT |\
590         HRCWH_TSEC1M_IN_GMII |\
591         HRCWH_TSEC2M_IN_GMII)
592 #else
593 #define CONFIG_SYS_HRCW_HIGH (\
594         HRCWH_PCI_HOST |\
595         HRCWH_32_BIT_PCI |\
596         HRCWH_PCI1_ARBITER_ENABLE |\
597         HRCWH_PCI2_ARBITER_ENABLE |\
598         HRCWH_CORE_ENABLE |\
599         HRCWH_FROM_0X00000100 |\
600         HRCWH_BOOTSEQ_DISABLE |\
601         HRCWH_SW_WATCHDOG_DISABLE |\
602         HRCWH_ROM_LOC_LOCAL_16BIT |\
603         HRCWH_TSEC1M_IN_GMII |\
604         HRCWH_TSEC2M_IN_GMII)
605 #endif /* PCI_64BIT */
606 #endif /* CONFIG_PCISLAVE */
607
608 /*
609  * System performance
610  */
611 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
612 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
613 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
614 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
615 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
616 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
617
618 /* System IO Config */
619 #define CONFIG_SYS_SICRH 0
620 #define CONFIG_SYS_SICRL SICRL_LDP_A
621
622 #define CONFIG_SYS_HID0_INIT    0x000000000
623 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
624                                 | HID0_ENABLE_INSTRUCTION_CACHE)
625
626 /* #define CONFIG_SYS_HID0_FINAL        (\
627         HID0_ENABLE_INSTRUCTION_CACHE |\
628         HID0_ENABLE_M_BIT |\
629         HID0_ENABLE_ADDRESS_BROADCAST) */
630
631
632 #define CONFIG_SYS_HID2 HID2_HBE
633 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
634
635 /* DDR @ 0x00000000 */
636 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
637                                 | BATL_PP_RW \
638                                 | BATL_MEMCOHERENCE)
639 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
640                                 | BATU_BL_256M \
641                                 | BATU_VS \
642                                 | BATU_VP)
643
644 /* PCI @ 0x80000000 */
645 #ifdef CONFIG_PCI
646 #define CONFIG_PCI_INDIRECT_BRIDGE
647 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
648                                 | BATL_PP_RW \
649                                 | BATL_MEMCOHERENCE)
650 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
651                                 | BATU_BL_256M \
652                                 | BATU_VS \
653                                 | BATU_VP)
654 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
655                                 | BATL_PP_RW \
656                                 | BATL_CACHEINHIBIT \
657                                 | BATL_GUARDEDSTORAGE)
658 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
659                                 | BATU_BL_256M \
660                                 | BATU_VS \
661                                 | BATU_VP)
662 #else
663 #define CONFIG_SYS_IBAT1L       (0)
664 #define CONFIG_SYS_IBAT1U       (0)
665 #define CONFIG_SYS_IBAT2L       (0)
666 #define CONFIG_SYS_IBAT2U       (0)
667 #endif
668
669 #ifdef CONFIG_MPC83XX_PCI2
670 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
671                                 | BATL_PP_RW \
672                                 | BATL_MEMCOHERENCE)
673 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
674                                 | BATU_BL_256M \
675                                 | BATU_VS \
676                                 | BATU_VP)
677 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
678                                 | BATL_PP_RW \
679                                 | BATL_CACHEINHIBIT \
680                                 | BATL_GUARDEDSTORAGE)
681 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
682                                 | BATU_BL_256M \
683                                 | BATU_VS \
684                                 | BATU_VP)
685 #else
686 #define CONFIG_SYS_IBAT3L       (0)
687 #define CONFIG_SYS_IBAT3U       (0)
688 #define CONFIG_SYS_IBAT4L       (0)
689 #define CONFIG_SYS_IBAT4U       (0)
690 #endif
691
692 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
693 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
694                                 | BATL_PP_RW \
695                                 | BATL_CACHEINHIBIT \
696                                 | BATL_GUARDEDSTORAGE)
697 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
698                                 | BATU_BL_256M \
699                                 | BATU_VS \
700                                 | BATU_VP)
701
702 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
703 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
704                                 | BATL_PP_RW \
705                                 | BATL_MEMCOHERENCE \
706                                 | BATL_GUARDEDSTORAGE)
707 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
708                                 | BATU_BL_256M \
709                                 | BATU_VS \
710                                 | BATU_VP)
711
712 #define CONFIG_SYS_IBAT7L       (0)
713 #define CONFIG_SYS_IBAT7U       (0)
714
715 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
716 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
717 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
718 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
719 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
720 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
721 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
722 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
723 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
724 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
725 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
726 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
727 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
728 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
729 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
730 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
731
732 #if defined(CONFIG_CMD_KGDB)
733 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
734 #endif
735
736 /*
737  * Environment Configuration
738  */
739 #define CONFIG_ENV_OVERWRITE
740
741 #if defined(CONFIG_TSEC_ENET)
742 #define CONFIG_HAS_ETH1
743 #define CONFIG_HAS_ETH0
744 #endif
745
746 #define CONFIG_HOSTNAME         mpc8349emds
747 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
748 #define CONFIG_BOOTFILE         "uImage"
749
750 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
751
752 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
753 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
754
755 #define CONFIG_BAUDRATE  115200
756
757 #define CONFIG_PREBOOT  "echo;" \
758         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
759         "echo"
760
761 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
762         "netdev=eth0\0"                                                 \
763         "hostname=mpc8349emds\0"                                        \
764         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
765                 "nfsroot=${serverip}:${rootpath}\0"                     \
766         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
767         "addip=setenv bootargs ${bootargs} "                            \
768                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
769                 ":${hostname}:${netdev}:off panic=1\0"                  \
770         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
771         "flash_nfs=run nfsargs addip addtty;"                           \
772                 "bootm ${kernel_addr}\0"                                \
773         "flash_self=run ramargs addip addtty;"                          \
774                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
775         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
776                 "bootm\0"                                               \
777         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
778         "update=protect off fe000000 fe03ffff; "                        \
779                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
780         "upd=run load update\0"                                         \
781         "fdtaddr=780000\0"                                              \
782         "fdtfile=mpc834x_mds.dtb\0"                                     \
783         ""
784
785 #define CONFIG_NFSBOOTCOMMAND                                           \
786         "setenv bootargs root=/dev/nfs rw "                             \
787                 "nfsroot=$serverip:$rootpath "                          \
788                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
789                                                         "$netdev:off "  \
790                 "console=$consoledev,$baudrate $othbootargs;"           \
791         "tftp $loadaddr $bootfile;"                                     \
792         "tftp $fdtaddr $fdtfile;"                                       \
793         "bootm $loadaddr - $fdtaddr"
794
795 #define CONFIG_RAMBOOTCOMMAND                                           \
796         "setenv bootargs root=/dev/ram rw "                             \
797                 "console=$consoledev,$baudrate $othbootargs;"           \
798         "tftp $ramdiskaddr $ramdiskfile;"                               \
799         "tftp $loadaddr $bootfile;"                                     \
800         "tftp $fdtaddr $fdtfile;"                                       \
801         "bootm $loadaddr $ramdiskaddr $fdtaddr"
802
803 #define CONFIG_BOOTCOMMAND      "run flash_self"
804
805 #endif  /* __CONFIG_H */