1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
25 #define CONFIG_DDR_ECC /* support DDR ECC function */
26 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
27 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
30 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
31 * unselect it to use old spd_sdram.c
33 #define CONFIG_SYS_SPD_BUS_NUM 0
34 #define SPD_EEPROM_ADDRESS1 0x52
35 #define SPD_EEPROM_ADDRESS2 0x51
36 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
37 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
39 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
41 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
42 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
43 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
45 * DDRCDR - DDR Control Driver Register
47 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
49 #if defined(CONFIG_SPD_EEPROM)
51 * Determine DDR configuration from I2C interface.
53 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
56 * Manually set up DDR parameters
58 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
59 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
60 | CSCONFIG_ROW_BIT_13 \
61 | CSCONFIG_COL_BIT_10)
62 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
63 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
64 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
65 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
67 /* the default burst length is 4 - for 64-bit data path */
68 /* DLL,normal,seq,4/2.5, 4 burst len */
69 #define CONFIG_SYS_DDR_MODE 0x00000022
73 * SDRAM on the Local Bus
75 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
76 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
79 * FLASH on the Local Bus
81 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
82 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
85 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
86 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
88 #undef CONFIG_SYS_FLASH_CHECKSUM
89 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
90 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
94 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
95 #define CONFIG_SYS_RAMBOOT
97 #undef CONFIG_SYS_RAMBOOT
101 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
103 #define CONFIG_SYS_BCSR 0xE2400000
104 /* Access window base at BCSR base */
107 #define CONFIG_SYS_INIT_RAM_LOCK 1
108 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
109 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
111 #define CONFIG_SYS_GBL_DATA_OFFSET \
112 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
113 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
115 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
116 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
121 #define CONFIG_SYS_NS16550_SERIAL
122 #define CONFIG_SYS_NS16550_REG_SIZE 1
123 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
125 #define CONFIG_SYS_BAUDRATE_TABLE \
126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
128 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
129 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
132 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
135 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
137 /* GPIOs. Used as SPI chip selects */
138 #define CONFIG_SYS_GPIO1_PRELIM
139 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
140 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
143 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
144 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
145 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
146 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
149 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
153 * Addresses are mapped 1-1.
155 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
156 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
157 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
158 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
159 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
160 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
161 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
162 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
163 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
165 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
166 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
167 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
168 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
169 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
170 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
171 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
172 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
173 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
175 #if defined(CONFIG_PCI)
177 #if !defined(CONFIG_PCI_PNP)
178 #define PCI_ENET0_IOADDR 0xFIXME
179 #define PCI_ENET0_MEMADDR 0xFIXME
180 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
183 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
185 #endif /* CONFIG_PCI */
191 #if defined(CONFIG_TSEC_ENET)
193 #define CONFIG_GMII 1 /* MII PHY management */
194 #define CONFIG_TSEC1 1
195 #define CONFIG_TSEC1_NAME "TSEC0"
196 #define CONFIG_TSEC2 1
197 #define CONFIG_TSEC2_NAME "TSEC1"
198 #define TSEC1_PHY_ADDR 0
199 #define TSEC2_PHY_ADDR 1
200 #define TSEC1_PHYIDX 0
201 #define TSEC2_PHYIDX 0
202 #define TSEC1_FLAGS TSEC_GIGABIT
203 #define TSEC2_FLAGS TSEC_GIGABIT
205 /* Options are: TSEC[0-1] */
206 #define CONFIG_ETHPRIME "TSEC0"
208 #endif /* CONFIG_TSEC_ENET */
211 * Configure on-board RTC
213 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
214 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
219 #ifndef CONFIG_SYS_RAMBOOT
220 /* Address and size of Redundant Environment Sector */
223 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
224 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
229 #define CONFIG_BOOTP_BOOTFILESIZE
231 #undef CONFIG_WATCHDOG /* watchdog disabled */
234 * Miscellaneous configurable options
236 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
239 * For booting Linux, the board info and command line data
240 * have to be in the first 256 MB of memory, since this is
241 * the maximum mapped by the Linux kernel during initialization.
243 /* Initial Memory map for Linux*/
244 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
245 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
247 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
252 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
253 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
255 /* System IO Config */
256 #define CONFIG_SYS_SICRH 0
257 #define CONFIG_SYS_SICRL SICRL_LDP_A
260 #define CONFIG_PCI_INDIRECT_BRIDGE
263 #if defined(CONFIG_CMD_KGDB)
264 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
268 * Environment Configuration
271 #if defined(CONFIG_TSEC_ENET)
272 #define CONFIG_HAS_ETH1
273 #define CONFIG_HAS_ETH0
276 #define CONFIG_HOSTNAME "mpc8349emds"
277 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
278 #define CONFIG_BOOTFILE "uImage"
280 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
282 #define CONFIG_EXTRA_ENV_SETTINGS \
284 "hostname=mpc8349emds\0" \
285 "nfsargs=setenv bootargs root=/dev/nfs rw " \
286 "nfsroot=${serverip}:${rootpath}\0" \
287 "ramargs=setenv bootargs root=/dev/ram rw\0" \
288 "addip=setenv bootargs ${bootargs} " \
289 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
290 ":${hostname}:${netdev}:off panic=1\0" \
291 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
292 "flash_nfs=run nfsargs addip addtty;" \
293 "bootm ${kernel_addr}\0" \
294 "flash_self=run ramargs addip addtty;" \
295 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
296 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
298 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
299 "update=protect off fe000000 fe03ffff; " \
300 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
301 "upd=run load update\0" \
303 "fdtfile=mpc834x_mds.dtb\0" \
306 #define NFSBOOTCOMMAND \
307 "setenv bootargs root=/dev/nfs rw " \
308 "nfsroot=$serverip:$rootpath " \
309 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
311 "console=$consoledev,$baudrate $othbootargs;" \
312 "tftp $loadaddr $bootfile;" \
313 "tftp $fdtaddr $fdtfile;" \
314 "bootm $loadaddr - $fdtaddr"
316 #define RAMBOOTCOMMAND \
317 "setenv bootargs root=/dev/ram rw " \
318 "console=$consoledev,$baudrate $othbootargs;" \
319 "tftp $ramdiskaddr $ramdiskfile;" \
320 "tftp $loadaddr $bootfile;" \
321 "tftp $fdtaddr $fdtfile;" \
322 "bootm $loadaddr $ramdiskaddr $fdtaddr"
324 #define CONFIG_BOOTCOMMAND "run flash_self"
326 #endif /* __CONFIG_H */