include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * mpc8349emds board configuration file
  26  *
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 /*
  33  * High Level Configuration Options
  34  */
  35 #define CONFIG_E300             1       /* E300 Family */
  36 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  37 #define CONFIG_MPC834x          1       /* MPC834x family */
  38 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  39 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  40
  41 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  42
  43 #define CONFIG_PCI_66M
  44 #ifdef CONFIG_PCI_66M
  45 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  46 #else
  47 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  48 #endif
  49
  50 #ifdef CONFIG_PCISLAVE
  51 #define CONFIG_PCI
  52 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  53 #endif /* CONFIG_PCISLAVE */
  54
  55 #ifndef CONFIG_SYS_CLK_FREQ
  56 #ifdef CONFIG_PCI_66M
  57 #define CONFIG_SYS_CLK_FREQ     66000000
  58 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  59 #else
  60 #define CONFIG_SYS_CLK_FREQ     33000000
  61 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  62 #endif
  63 #endif
  64
  65 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  66
  67 #define CONFIG_SYS_IMMR         0xE0000000
  68
  69 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  70 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  71 #define CONFIG_SYS_MEMTEST_END          0x00100000
  72
  73 /*
  74  * DDR Setup
  75  */
  76 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  77 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  78 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  79
  80 /*
  81  * define CONFIG_FSL_DDR2 to use unified DDR driver
  82  * undefine it to use old spd_sdram.c
  83  */
  84 #define CONFIG_FSL_DDR2
  85 #ifdef CONFIG_FSL_DDR2
  86 #define CONFIG_SYS_SPD_BUS_NUM  0
  87 #define SPD_EEPROM_ADDRESS1     0x52
  88 #define SPD_EEPROM_ADDRESS2     0x51
  89 #define CONFIG_NUM_DDR_CONTROLLERS      1
  90 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  91 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  93 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  94 #endif
  95
  96 /*
  97  * 32-bit data path mode.
  98  *
  99  * Please note that using this mode for devices with the real density of 64-bit
 100  * effectively reduces the amount of available memory due to the effect of
 101  * wrapping around while translating address to row/columns, for example in the
 102  * 256MB module the upper 128MB get aliased with contents of the lower
 103  * 128MB); normally this define should be used for devices with real 32-bit
 104  * data path.
 105  */
 106 #undef CONFIG_DDR_32BIT
 107
 108 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
 109 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
 110 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 111 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
 112                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 113 #undef  CONFIG_DDR_2T_TIMING
 114
 115 /*
 116  * DDRCDR - DDR Control Driver Register
 117  */
 118 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 119
 120 #if defined(CONFIG_SPD_EEPROM)
 121 /*
 122  * Determine DDR configuration from I2C interface.
 123  */
 124 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 125 #else
 126 /*
 127  * Manually set up DDR parameters
 128  */
 129 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 130 #if defined(CONFIG_DDR_II)
 131 #define CONFIG_SYS_DDRCDR               0x80080001
 132 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
 133 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 134 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 135 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 136 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 137 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 138 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 139 #define CONFIG_SYS_DDR_MODE             0x47d00432
 140 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 141 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 142 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 143 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 144 #else
 145 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 146                                 | CSCONFIG_ROW_BIT_13 \
 147                                 | CSCONFIG_COL_BIT_10)
 148 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 149 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 150 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 151 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 152
 153 #if defined(CONFIG_DDR_32BIT)
 154 /* set burst length to 8 for 32-bit data path */
 155                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 156 #define CONFIG_SYS_DDR_MODE     0x00000023
 157 #else
 158 /* the default burst length is 4 - for 64-bit data path */
 159                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 160 #define CONFIG_SYS_DDR_MODE     0x00000022
 161 #endif
 162 #endif
 163 #endif
 164
 165 /*
 166  * SDRAM on the Local Bus
 167  */
 168 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 169 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 170
 171 /*
 172  * FLASH on the Local Bus
 173  */
 174 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 175 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 176 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 177 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 178 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 179 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 180
 181 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 182                                 | BR_PS_16      /* 16 bit port  */ \
 183                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 184                                 | BR_V)         /* valid */
 185 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 186                                 | OR_UPM_XAM \
 187                                 | OR_GPCM_CSNT \
 188                                 | OR_GPCM_ACS_DIV2 \
 189                                 | OR_GPCM_XACS \
 190                                 | OR_GPCM_SCY_15 \
 191                                 | OR_GPCM_TRLX_SET \
 192                                 | OR_GPCM_EHTR_SET \
 193                                 | OR_GPCM_EAD)
 194
 195                                         /* window base at flash base */
 196 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 197 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 198
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 200 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 201
 202 #undef CONFIG_SYS_FLASH_CHECKSUM
 203 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 204 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 205
 206 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 207
 208 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 209 #define CONFIG_SYS_RAMBOOT
 210 #else
 211 #undef  CONFIG_SYS_RAMBOOT
 212 #endif
 213
 214 /*
 215  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 216  */
 217 #define CONFIG_SYS_BCSR                 0xE2400000
 218                                         /* Access window base at BCSR base */
 219 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 220 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 221 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 222                                         | BR_PS_8 \
 223                                         | BR_MS_GPCM \
 224                                         | BR_V)
 225                                         /* 0x00000801 */
 226 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 227                                         | OR_GPCM_XAM \
 228                                         | OR_GPCM_CSNT \
 229                                         | OR_GPCM_SCY_15 \
 230                                         | OR_GPCM_TRLX_CLEAR \
 231                                         | OR_GPCM_EHTR_CLEAR)
 232                                         /* 0xFFFFE8F0 */
 233
 234 #define CONFIG_SYS_INIT_RAM_LOCK        1
 235 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 236 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 237
 238 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 239                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 240 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 241
 242 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 243 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 244
 245 /*
 246  * Local Bus LCRR and LBCR regs
 247  *    LCRR:  DLL bypass, Clock divider is 4
 248  * External Local Bus rate is
 249  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 250  */
 251 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 252 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 253 #define CONFIG_SYS_LBC_LBCR     0x00000000
 254
 255 /*
 256  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 257  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 258  */
 259 #undef CONFIG_SYS_LB_SDRAM
 260
 261 #ifdef CONFIG_SYS_LB_SDRAM
 262 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 263 /*
 264  * Base Register 2 and Option Register 2 configure SDRAM.
 265  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 266  *
 267  * For BR2, need:
 268  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 269  *    port-size = 32-bits = BR2[19:20] = 11
 270  *    no parity checking = BR2[21:22] = 00
 271  *    SDRAM for MSEL = BR2[24:26] = 011
 272  *    Valid = BR[31] = 1
 273  *
 274  * 0    4    8    12   16   20   24   28
 275  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 276  */
 277
 278 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 279                                         | BR_PS_32      /* 32-bit port */ \
 280                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 281                                         | BR_V)         /* Valid */
 282                                         /* 0xF0001861 */
 283 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 284 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 285
 286 /*
 287  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 288  *
 289  * For OR2, need:
 290  *    64MB mask for AM, OR2[0:7] = 1111 1100
 291  *                 XAM, OR2[17:18] = 11
 292  *    9 columns OR2[19-21] = 010
 293  *    13 rows   OR2[23-25] = 100
 294  *    EAD set for extra time OR[31] = 1
 295  *
 296  * 0    4    8    12   16   20   24   28
 297  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 298  */
 299
 300 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 301                         | OR_SDRAM_XAM \
 302                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 303                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 304                         | OR_SDRAM_EAD)
 305                         /* 0xFC006901 */
 306
 307                                 /* LB sdram refresh timer, about 6us */
 308 #define CONFIG_SYS_LBC_LSRT     0x32000000
 309                                 /* LB refresh timer prescal, 266MHz/32 */
 310 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 311
 312 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 313                                 | LSDMR_BSMA1516        \
 314                                 | LSDMR_RFCR8           \
 315                                 | LSDMR_PRETOACT6       \
 316                                 | LSDMR_ACTTORW3        \
 317                                 | LSDMR_BL8             \
 318                                 | LSDMR_WRC3            \
 319                                 | LSDMR_CL3)
 320
 321 /*
 322  * SDRAM Controller configuration sequence.
 323  */
 324 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 325 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 326 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 327 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 328 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 329 #endif
 330
 331 /*
 332  * Serial Port
 333  */
 334 #define CONFIG_CONS_INDEX     1
 335 #define CONFIG_SYS_NS16550
 336 #define CONFIG_SYS_NS16550_SERIAL
 337 #define CONFIG_SYS_NS16550_REG_SIZE    1
 338 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 339
 340 #define CONFIG_SYS_BAUDRATE_TABLE  \
 341                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 342
 343 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 344 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 345
 346 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 347 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 348 /* Use the HUSH parser */
 349 #define CONFIG_SYS_HUSH_PARSER
 350
 351 /* pass open firmware flat tree */
 352 #define CONFIG_OF_LIBFDT        1
 353 #define CONFIG_OF_BOARD_SETUP   1
 354 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 355
 356 /* I2C */
 357 #define CONFIG_SYS_I2C
 358 #define CONFIG_SYS_I2C_FSL
 359 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 360 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 361 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 362 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 363 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 364 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 365 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 366
 367 /* SPI */
 368 #define CONFIG_MPC8XXX_SPI
 369 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 370
 371 /* GPIOs.  Used as SPI chip selects */
 372 #define CONFIG_SYS_GPIO1_PRELIM
 373 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 374 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 375
 376 /* TSEC */
 377 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 378 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 379 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 380 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 381
 382 /* USB */
 383 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 384
 385 /*
 386  * General PCI
 387  * Addresses are mapped 1-1.
 388  */
 389 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 390 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 391 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 392 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 393 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 394 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 395 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 396 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 397 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 398
 399 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 400 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 401 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 402 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 403 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 404 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 405 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 406 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 407 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 408
 409 #if defined(CONFIG_PCI)
 410
 411 #define PCI_ONE_PCI1
 412 #if defined(PCI_64BIT)
 413 #undef PCI_ALL_PCI1
 414 #undef PCI_TWO_PCI1
 415 #undef PCI_ONE_PCI1
 416 #endif
 417
 418 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 419 #define CONFIG_83XX_PCI_STREAMING
 420
 421 #undef CONFIG_EEPRO100
 422 #undef CONFIG_TULIP
 423
 424 #if !defined(CONFIG_PCI_PNP)
 425         #define PCI_ENET0_IOADDR        0xFIXME
 426         #define PCI_ENET0_MEMADDR       0xFIXME
 427         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 428 #endif
 429
 430 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 431 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 432
 433 #endif  /* CONFIG_PCI */
 434
 435 /*
 436  * TSEC configuration
 437  */
 438 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 439
 440 #if defined(CONFIG_TSEC_ENET)
 441
 442 #define CONFIG_GMII             1       /* MII PHY management */
 443 #define CONFIG_TSEC1            1
 444 #define CONFIG_TSEC1_NAME       "TSEC0"
 445 #define CONFIG_TSEC2            1
 446 #define CONFIG_TSEC2_NAME       "TSEC1"
 447 #define TSEC1_PHY_ADDR          0
 448 #define TSEC2_PHY_ADDR          1
 449 #define TSEC1_PHYIDX            0
 450 #define TSEC2_PHYIDX            0
 451 #define TSEC1_FLAGS             TSEC_GIGABIT
 452 #define TSEC2_FLAGS             TSEC_GIGABIT
 453
 454 /* Options are: TSEC[0-1] */
 455 #define CONFIG_ETHPRIME         "TSEC0"
 456
 457 #endif  /* CONFIG_TSEC_ENET */
 458
 459 /*
 460  * Configure on-board RTC
 461  */
 462 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 463 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 464
 465 /*
 466  * Environment
 467  */
 468 #ifndef CONFIG_SYS_RAMBOOT
 469         #define CONFIG_ENV_IS_IN_FLASH  1
 470         #define CONFIG_ENV_ADDR         \
 471                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 472         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 473         #define CONFIG_ENV_SIZE         0x2000
 474
 475 /* Address and size of Redundant Environment Sector     */
 476 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 477 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 478
 479 #else
 480         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 481         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 482         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 483         #define CONFIG_ENV_SIZE         0x2000
 484 #endif
 485
 486 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 487 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 488
 489
 490 /*
 491  * BOOTP options
 492  */
 493 #define CONFIG_BOOTP_BOOTFILESIZE
 494 #define CONFIG_BOOTP_BOOTPATH
 495 #define CONFIG_BOOTP_GATEWAY
 496 #define CONFIG_BOOTP_HOSTNAME
 497
 498
 499 /*
 500  * Command line configuration.
 501  */
 502 #include <config_cmd_default.h>
 503
 504 #define CONFIG_CMD_PING
 505 #define CONFIG_CMD_I2C
 506 #define CONFIG_CMD_DATE
 507 #define CONFIG_CMD_MII
 508
 509 #if defined(CONFIG_PCI)
 510     #define CONFIG_CMD_PCI
 511 #endif
 512
 513 #if defined(CONFIG_SYS_RAMBOOT)
 514     #undef CONFIG_CMD_SAVEENV
 515     #undef CONFIG_CMD_LOADS
 516 #endif
 517
 518
 519 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 520
 521 /*
 522  * Miscellaneous configurable options
 523  */
 524 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 525 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 526 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 527
 528 #if defined(CONFIG_CMD_KGDB)
 529         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 530 #else
 531         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 532 #endif
 533
 534                                 /* Print Buffer Size */
 535 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 536 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 537                                 /* Boot Argument Buffer Size */
 538 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 539 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 540
 541 /*
 542  * For booting Linux, the board info and command line data
 543  * have to be in the first 256 MB of memory, since this is
 544  * the maximum mapped by the Linux kernel during initialization.
 545  */
 546                                 /* Initial Memory map for Linux*/
 547 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 548
 549 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 550
 551 #if 1 /*528/264*/
 552 #define CONFIG_SYS_HRCW_LOW (\
 553         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 554         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 555         HRCWL_CSB_TO_CLKIN |\
 556         HRCWL_VCO_1X2 |\
 557         HRCWL_CORE_TO_CSB_2X1)
 558 #elif 0 /*396/132*/
 559 #define CONFIG_SYS_HRCW_LOW (\
 560         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 561         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 562         HRCWL_CSB_TO_CLKIN |\
 563         HRCWL_VCO_1X4 |\
 564         HRCWL_CORE_TO_CSB_3X1)
 565 #elif 0 /*264/132*/
 566 #define CONFIG_SYS_HRCW_LOW (\
 567         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 568         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 569         HRCWL_CSB_TO_CLKIN |\
 570         HRCWL_VCO_1X4 |\
 571         HRCWL_CORE_TO_CSB_2X1)
 572 #elif 0 /*132/132*/
 573 #define CONFIG_SYS_HRCW_LOW (\
 574         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 575         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 576         HRCWL_CSB_TO_CLKIN |\
 577         HRCWL_VCO_1X4 |\
 578         HRCWL_CORE_TO_CSB_1X1)
 579 #elif 0 /*264/264 */
 580 #define CONFIG_SYS_HRCW_LOW (\
 581         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 582         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 583         HRCWL_CSB_TO_CLKIN |\
 584         HRCWL_VCO_1X4 |\
 585         HRCWL_CORE_TO_CSB_1X1)
 586 #endif
 587
 588 #ifdef CONFIG_PCISLAVE
 589 #define CONFIG_SYS_HRCW_HIGH (\
 590         HRCWH_PCI_AGENT |\
 591         HRCWH_64_BIT_PCI |\
 592         HRCWH_PCI1_ARBITER_DISABLE |\
 593         HRCWH_PCI2_ARBITER_DISABLE |\
 594         HRCWH_CORE_ENABLE |\
 595         HRCWH_FROM_0X00000100 |\
 596         HRCWH_BOOTSEQ_DISABLE |\
 597         HRCWH_SW_WATCHDOG_DISABLE |\
 598         HRCWH_ROM_LOC_LOCAL_16BIT |\
 599         HRCWH_TSEC1M_IN_GMII |\
 600         HRCWH_TSEC2M_IN_GMII)
 601 #else
 602 #if defined(PCI_64BIT)
 603 #define CONFIG_SYS_HRCW_HIGH (\
 604         HRCWH_PCI_HOST |\
 605         HRCWH_64_BIT_PCI |\
 606         HRCWH_PCI1_ARBITER_ENABLE |\
 607         HRCWH_PCI2_ARBITER_DISABLE |\
 608         HRCWH_CORE_ENABLE |\
 609         HRCWH_FROM_0X00000100 |\
 610         HRCWH_BOOTSEQ_DISABLE |\
 611         HRCWH_SW_WATCHDOG_DISABLE |\
 612         HRCWH_ROM_LOC_LOCAL_16BIT |\
 613         HRCWH_TSEC1M_IN_GMII |\
 614         HRCWH_TSEC2M_IN_GMII)
 615 #else
 616 #define CONFIG_SYS_HRCW_HIGH (\
 617         HRCWH_PCI_HOST |\
 618         HRCWH_32_BIT_PCI |\
 619         HRCWH_PCI1_ARBITER_ENABLE |\
 620         HRCWH_PCI2_ARBITER_ENABLE |\
 621         HRCWH_CORE_ENABLE |\
 622         HRCWH_FROM_0X00000100 |\
 623         HRCWH_BOOTSEQ_DISABLE |\
 624         HRCWH_SW_WATCHDOG_DISABLE |\
 625         HRCWH_ROM_LOC_LOCAL_16BIT |\
 626         HRCWH_TSEC1M_IN_GMII |\
 627         HRCWH_TSEC2M_IN_GMII)
 628 #endif /* PCI_64BIT */
 629 #endif /* CONFIG_PCISLAVE */
 630
 631 /*
 632  * System performance
 633  */
 634 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 635 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 636 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 637 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 638 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 639 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 640
 641 /* System IO Config */
 642 #define CONFIG_SYS_SICRH 0
 643 #define CONFIG_SYS_SICRL SICRL_LDP_A
 644
 645 #define CONFIG_SYS_HID0_INIT    0x000000000
 646 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 647                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 648
 649 /* #define CONFIG_SYS_HID0_FINAL        (\
 650         HID0_ENABLE_INSTRUCTION_CACHE |\
 651         HID0_ENABLE_M_BIT |\
 652         HID0_ENABLE_ADDRESS_BROADCAST) */
 653
 654
 655 #define CONFIG_SYS_HID2 HID2_HBE
 656 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 657
 658 /* DDR @ 0x00000000 */
 659 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 660                                 | BATL_PP_RW \
 661                                 | BATL_MEMCOHERENCE)
 662 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 663                                 | BATU_BL_256M \
 664                                 | BATU_VS \
 665                                 | BATU_VP)
 666
 667 /* PCI @ 0x80000000 */
 668 #ifdef CONFIG_PCI
 669 #define CONFIG_PCI_INDIRECT_BRIDGE
 670 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 671                                 | BATL_PP_RW \
 672                                 | BATL_MEMCOHERENCE)
 673 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 674                                 | BATU_BL_256M \
 675                                 | BATU_VS \
 676                                 | BATU_VP)
 677 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 678                                 | BATL_PP_RW \
 679                                 | BATL_CACHEINHIBIT \
 680                                 | BATL_GUARDEDSTORAGE)
 681 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 682                                 | BATU_BL_256M \
 683                                 | BATU_VS \
 684                                 | BATU_VP)
 685 #else
 686 #define CONFIG_SYS_IBAT1L       (0)
 687 #define CONFIG_SYS_IBAT1U       (0)
 688 #define CONFIG_SYS_IBAT2L       (0)
 689 #define CONFIG_SYS_IBAT2U       (0)
 690 #endif
 691
 692 #ifdef CONFIG_MPC83XX_PCI2
 693 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 694                                 | BATL_PP_RW \
 695                                 | BATL_MEMCOHERENCE)
 696 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 697                                 | BATU_BL_256M \
 698                                 | BATU_VS \
 699                                 | BATU_VP)
 700 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 701                                 | BATL_PP_RW \
 702                                 | BATL_CACHEINHIBIT \
 703                                 | BATL_GUARDEDSTORAGE)
 704 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 705                                 | BATU_BL_256M \
 706                                 | BATU_VS \
 707                                 | BATU_VP)
 708 #else
 709 #define CONFIG_SYS_IBAT3L       (0)
 710 #define CONFIG_SYS_IBAT3U       (0)
 711 #define CONFIG_SYS_IBAT4L       (0)
 712 #define CONFIG_SYS_IBAT4U       (0)
 713 #endif
 714
 715 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 716 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 717                                 | BATL_PP_RW \
 718                                 | BATL_CACHEINHIBIT \
 719                                 | BATL_GUARDEDSTORAGE)
 720 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 721                                 | BATU_BL_256M \
 722                                 | BATU_VS \
 723                                 | BATU_VP)
 724
 725 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 726 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 727                                 | BATL_PP_RW \
 728                                 | BATL_MEMCOHERENCE \
 729                                 | BATL_GUARDEDSTORAGE)
 730 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 731                                 | BATU_BL_256M \
 732                                 | BATU_VS \
 733                                 | BATU_VP)
 734
 735 #define CONFIG_SYS_IBAT7L       (0)
 736 #define CONFIG_SYS_IBAT7U       (0)
 737
 738 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 739 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 740 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 741 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 742 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 743 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 744 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 745 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 746 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 747 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 748 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 749 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 750 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 751 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 752 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 753 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 754
 755 #if defined(CONFIG_CMD_KGDB)
 756 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 757 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 758 #endif
 759
 760 /*
 761  * Environment Configuration
 762  */
 763 #define CONFIG_ENV_OVERWRITE
 764
 765 #if defined(CONFIG_TSEC_ENET)
 766 #define CONFIG_HAS_ETH1
 767 #define CONFIG_HAS_ETH0
 768 #endif
 769
 770 #define CONFIG_HOSTNAME         mpc8349emds
 771 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 772 #define CONFIG_BOOTFILE         "uImage"
 773
 774 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 775
 776 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 777 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 778
 779 #define CONFIG_BAUDRATE  115200
 780
 781 #define CONFIG_PREBOOT  "echo;" \
 782         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 783         "echo"
 784
 785 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 786         "netdev=eth0\0"                                                 \
 787         "hostname=mpc8349emds\0"                                        \
 788         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 789                 "nfsroot=${serverip}:${rootpath}\0"                     \
 790         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 791         "addip=setenv bootargs ${bootargs} "                            \
 792                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 793                 ":${hostname}:${netdev}:off panic=1\0"                  \
 794         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 795         "flash_nfs=run nfsargs addip addtty;"                           \
 796                 "bootm ${kernel_addr}\0"                                \
 797         "flash_self=run ramargs addip addtty;"                          \
 798                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 799         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 800                 "bootm\0"                                               \
 801         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 802         "update=protect off fe000000 fe03ffff; "                        \
 803                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 804         "upd=run load update\0"                                         \
 805         "fdtaddr=780000\0"                                              \
 806         "fdtfile=mpc834x_mds.dtb\0"                                     \
 807         ""
 808
 809 #define CONFIG_NFSBOOTCOMMAND                                           \
 810         "setenv bootargs root=/dev/nfs rw "                             \
 811                 "nfsroot=$serverip:$rootpath "                          \
 812                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 813                                                         "$netdev:off "  \
 814                 "console=$consoledev,$baudrate $othbootargs;"           \
 815         "tftp $loadaddr $bootfile;"                                     \
 816         "tftp $fdtaddr $fdtfile;"                                       \
 817         "bootm $loadaddr - $fdtaddr"
 818
 819 #define CONFIG_RAMBOOTCOMMAND                                           \
 820         "setenv bootargs root=/dev/ram rw "                             \
 821                 "console=$consoledev,$baudrate $othbootargs;"           \
 822         "tftp $ramdiskaddr $ramdiskfile;"                               \
 823         "tftp $loadaddr $bootfile;"                                     \
 824         "tftp $fdtaddr $fdtfile;"                                       \
 825         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 826
 827 #define CONFIG_BOOTCOMMAND      "run flash_self"
 828
 829 #endif  /* __CONFIG_H */