2 * (C) Copyright 2006-2010
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * mpc8349emds board configuration file
17 * High Level Configuration Options
19 #define CONFIG_E300 1 /* E300 Family */
20 #define CONFIG_MPC834x 1 /* MPC834x family */
21 #define CONFIG_MPC8349 1 /* MPC8349 specific */
22 #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
24 #define CONFIG_SYS_TEXT_BASE 0xFE000000
26 #define CONFIG_PCI_66M
28 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
30 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
33 #ifdef CONFIG_PCISLAVE
34 #define CONFIG_83XX_PCICLK 66666666 /* in Hz */
35 #endif /* CONFIG_PCISLAVE */
37 #ifndef CONFIG_SYS_CLK_FREQ
39 #define CONFIG_SYS_CLK_FREQ 66000000
40 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
42 #define CONFIG_SYS_CLK_FREQ 33000000
43 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
47 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
49 #define CONFIG_SYS_IMMR 0xE0000000
51 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
52 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
53 #define CONFIG_SYS_MEMTEST_END 0x00100000
58 #define CONFIG_DDR_ECC /* support DDR ECC function */
59 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
60 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
63 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
64 * unselect it to use old spd_sdram.c
66 #define CONFIG_SYS_SPD_BUS_NUM 0
67 #define SPD_EEPROM_ADDRESS1 0x52
68 #define SPD_EEPROM_ADDRESS2 0x51
69 #define CONFIG_NUM_DDR_CONTROLLERS 1
70 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
72 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
73 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76 * 32-bit data path mode.
78 * Please note that using this mode for devices with the real density of 64-bit
79 * effectively reduces the amount of available memory due to the effect of
80 * wrapping around while translating address to row/columns, for example in the
81 * 256MB module the upper 128MB get aliased with contents of the lower
82 * 128MB); normally this define should be used for devices with real 32-bit
85 #undef CONFIG_DDR_32BIT
87 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
89 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
90 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
91 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
92 #undef CONFIG_DDR_2T_TIMING
95 * DDRCDR - DDR Control Driver Register
97 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
99 #if defined(CONFIG_SPD_EEPROM)
101 * Determine DDR configuration from I2C interface.
103 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
106 * Manually set up DDR parameters
108 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
109 #if defined(CONFIG_DDR_II)
110 #define CONFIG_SYS_DDRCDR 0x80080001
111 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
112 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
113 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
114 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
115 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
116 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
117 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
118 #define CONFIG_SYS_DDR_MODE 0x47d00432
119 #define CONFIG_SYS_DDR_MODE2 0x8000c000
120 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
121 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
122 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
124 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
125 | CSCONFIG_ROW_BIT_13 \
126 | CSCONFIG_COL_BIT_10)
127 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
128 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
129 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
130 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
132 #if defined(CONFIG_DDR_32BIT)
133 /* set burst length to 8 for 32-bit data path */
134 /* DLL,normal,seq,4/2.5, 8 burst len */
135 #define CONFIG_SYS_DDR_MODE 0x00000023
137 /* the default burst length is 4 - for 64-bit data path */
138 /* DLL,normal,seq,4/2.5, 4 burst len */
139 #define CONFIG_SYS_DDR_MODE 0x00000022
145 * SDRAM on the Local Bus
147 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
148 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
151 * FLASH on the Local Bus
153 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
154 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
155 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
156 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
157 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
158 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
160 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
161 | BR_PS_16 /* 16 bit port */ \
162 | BR_MS_GPCM /* MSEL = GPCM */ \
164 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
174 /* window base at flash base */
175 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
176 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
178 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
179 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
181 #undef CONFIG_SYS_FLASH_CHECKSUM
182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
187 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
188 #define CONFIG_SYS_RAMBOOT
190 #undef CONFIG_SYS_RAMBOOT
194 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
196 #define CONFIG_SYS_BCSR 0xE2400000
197 /* Access window base at BCSR base */
198 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
199 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
200 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
205 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
209 | OR_GPCM_TRLX_CLEAR \
210 | OR_GPCM_EHTR_CLEAR)
213 #define CONFIG_SYS_INIT_RAM_LOCK 1
214 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
215 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
217 #define CONFIG_SYS_GBL_DATA_OFFSET \
218 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
221 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
222 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
225 * Local Bus LCRR and LBCR regs
226 * LCRR: DLL bypass, Clock divider is 4
227 * External Local Bus rate is
228 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
230 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
231 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
232 #define CONFIG_SYS_LBC_LBCR 0x00000000
235 * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
236 * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
238 #undef CONFIG_SYS_LB_SDRAM
240 #ifdef CONFIG_SYS_LB_SDRAM
241 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
243 * Base Register 2 and Option Register 2 configure SDRAM.
244 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
247 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
248 * port-size = 32-bits = BR2[19:20] = 11
249 * no parity checking = BR2[21:22] = 00
250 * SDRAM for MSEL = BR2[24:26] = 011
253 * 0 4 8 12 16 20 24 28
254 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
257 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
258 | BR_PS_32 /* 32-bit port */ \
259 | BR_MS_SDRAM /* MSEL = SDRAM */ \
262 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
263 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
266 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
269 * 64MB mask for AM, OR2[0:7] = 1111 1100
270 * XAM, OR2[17:18] = 11
271 * 9 columns OR2[19-21] = 010
272 * 13 rows OR2[23-25] = 100
273 * EAD set for extra time OR[31] = 1
275 * 0 4 8 12 16 20 24 28
276 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
279 #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
281 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
282 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
286 /* LB sdram refresh timer, about 6us */
287 #define CONFIG_SYS_LBC_LSRT 0x32000000
288 /* LB refresh timer prescal, 266MHz/32 */
289 #define CONFIG_SYS_LBC_MRTPR 0x20000000
291 #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
301 * SDRAM Controller configuration sequence.
303 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
304 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
305 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
306 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
307 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
313 #define CONFIG_CONS_INDEX 1
314 #define CONFIG_SYS_NS16550_SERIAL
315 #define CONFIG_SYS_NS16550_REG_SIZE 1
316 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
318 #define CONFIG_SYS_BAUDRATE_TABLE \
319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
324 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
325 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
328 #define CONFIG_SYS_I2C
329 #define CONFIG_SYS_I2C_FSL
330 #define CONFIG_SYS_FSL_I2C_SPEED 400000
331 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
332 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
333 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
334 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
335 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
336 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
339 #define CONFIG_MPC8XXX_SPI
340 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
342 /* GPIOs. Used as SPI chip selects */
343 #define CONFIG_SYS_GPIO1_PRELIM
344 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
345 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
348 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
349 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
350 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
351 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
354 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
358 * Addresses are mapped 1-1.
360 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
361 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
362 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
363 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
364 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
365 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
366 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
367 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
368 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
370 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
371 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
372 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
373 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
374 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
375 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
376 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
377 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
378 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
380 #if defined(CONFIG_PCI)
383 #if defined(PCI_64BIT)
389 #define CONFIG_83XX_PCI_STREAMING
391 #undef CONFIG_EEPRO100
394 #if !defined(CONFIG_PCI_PNP)
395 #define PCI_ENET0_IOADDR 0xFIXME
396 #define PCI_ENET0_MEMADDR 0xFIXME
397 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
400 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
401 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
403 #endif /* CONFIG_PCI */
408 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
410 #if defined(CONFIG_TSEC_ENET)
412 #define CONFIG_GMII 1 /* MII PHY management */
413 #define CONFIG_TSEC1 1
414 #define CONFIG_TSEC1_NAME "TSEC0"
415 #define CONFIG_TSEC2 1
416 #define CONFIG_TSEC2_NAME "TSEC1"
417 #define TSEC1_PHY_ADDR 0
418 #define TSEC2_PHY_ADDR 1
419 #define TSEC1_PHYIDX 0
420 #define TSEC2_PHYIDX 0
421 #define TSEC1_FLAGS TSEC_GIGABIT
422 #define TSEC2_FLAGS TSEC_GIGABIT
424 /* Options are: TSEC[0-1] */
425 #define CONFIG_ETHPRIME "TSEC0"
427 #endif /* CONFIG_TSEC_ENET */
430 * Configure on-board RTC
432 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
433 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
438 #ifndef CONFIG_SYS_RAMBOOT
439 #define CONFIG_ENV_IS_IN_FLASH 1
440 #define CONFIG_ENV_ADDR \
441 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
442 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
443 #define CONFIG_ENV_SIZE 0x2000
445 /* Address and size of Redundant Environment Sector */
446 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
447 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
450 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
451 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
452 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
453 #define CONFIG_ENV_SIZE 0x2000
456 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
457 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
462 #define CONFIG_BOOTP_BOOTFILESIZE
463 #define CONFIG_BOOTP_BOOTPATH
464 #define CONFIG_BOOTP_GATEWAY
465 #define CONFIG_BOOTP_HOSTNAME
468 * Command line configuration.
470 #define CONFIG_CMD_DATE
472 #if defined(CONFIG_PCI)
473 #define CONFIG_CMD_PCI
476 #undef CONFIG_WATCHDOG /* watchdog disabled */
479 * Miscellaneous configurable options
481 #define CONFIG_SYS_LONGHELP /* undef to save memory */
482 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
484 #if defined(CONFIG_CMD_KGDB)
485 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
487 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
490 /* Print Buffer Size */
491 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
492 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
493 /* Boot Argument Buffer Size */
494 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
497 * For booting Linux, the board info and command line data
498 * have to be in the first 256 MB of memory, since this is
499 * the maximum mapped by the Linux kernel during initialization.
501 /* Initial Memory map for Linux*/
502 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
503 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
505 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
508 #define CONFIG_SYS_HRCW_LOW (\
509 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
510 HRCWL_DDR_TO_SCB_CLK_1X1 |\
511 HRCWL_CSB_TO_CLKIN |\
513 HRCWL_CORE_TO_CSB_2X1)
515 #define CONFIG_SYS_HRCW_LOW (\
516 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
517 HRCWL_DDR_TO_SCB_CLK_1X1 |\
518 HRCWL_CSB_TO_CLKIN |\
520 HRCWL_CORE_TO_CSB_3X1)
522 #define CONFIG_SYS_HRCW_LOW (\
523 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
524 HRCWL_DDR_TO_SCB_CLK_1X1 |\
525 HRCWL_CSB_TO_CLKIN |\
527 HRCWL_CORE_TO_CSB_2X1)
529 #define CONFIG_SYS_HRCW_LOW (\
530 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
531 HRCWL_DDR_TO_SCB_CLK_1X1 |\
532 HRCWL_CSB_TO_CLKIN |\
534 HRCWL_CORE_TO_CSB_1X1)
536 #define CONFIG_SYS_HRCW_LOW (\
537 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
538 HRCWL_DDR_TO_SCB_CLK_1X1 |\
539 HRCWL_CSB_TO_CLKIN |\
541 HRCWL_CORE_TO_CSB_1X1)
544 #ifdef CONFIG_PCISLAVE
545 #define CONFIG_SYS_HRCW_HIGH (\
548 HRCWH_PCI1_ARBITER_DISABLE |\
549 HRCWH_PCI2_ARBITER_DISABLE |\
551 HRCWH_FROM_0X00000100 |\
552 HRCWH_BOOTSEQ_DISABLE |\
553 HRCWH_SW_WATCHDOG_DISABLE |\
554 HRCWH_ROM_LOC_LOCAL_16BIT |\
555 HRCWH_TSEC1M_IN_GMII |\
556 HRCWH_TSEC2M_IN_GMII)
558 #if defined(PCI_64BIT)
559 #define CONFIG_SYS_HRCW_HIGH (\
562 HRCWH_PCI1_ARBITER_ENABLE |\
563 HRCWH_PCI2_ARBITER_DISABLE |\
565 HRCWH_FROM_0X00000100 |\
566 HRCWH_BOOTSEQ_DISABLE |\
567 HRCWH_SW_WATCHDOG_DISABLE |\
568 HRCWH_ROM_LOC_LOCAL_16BIT |\
569 HRCWH_TSEC1M_IN_GMII |\
570 HRCWH_TSEC2M_IN_GMII)
572 #define CONFIG_SYS_HRCW_HIGH (\
575 HRCWH_PCI1_ARBITER_ENABLE |\
576 HRCWH_PCI2_ARBITER_ENABLE |\
578 HRCWH_FROM_0X00000100 |\
579 HRCWH_BOOTSEQ_DISABLE |\
580 HRCWH_SW_WATCHDOG_DISABLE |\
581 HRCWH_ROM_LOC_LOCAL_16BIT |\
582 HRCWH_TSEC1M_IN_GMII |\
583 HRCWH_TSEC2M_IN_GMII)
584 #endif /* PCI_64BIT */
585 #endif /* CONFIG_PCISLAVE */
590 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
591 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
592 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
593 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
594 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
595 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
597 /* System IO Config */
598 #define CONFIG_SYS_SICRH 0
599 #define CONFIG_SYS_SICRL SICRL_LDP_A
601 #define CONFIG_SYS_HID0_INIT 0x000000000
602 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
603 | HID0_ENABLE_INSTRUCTION_CACHE)
605 /* #define CONFIG_SYS_HID0_FINAL (\
606 HID0_ENABLE_INSTRUCTION_CACHE |\
608 HID0_ENABLE_ADDRESS_BROADCAST) */
610 #define CONFIG_SYS_HID2 HID2_HBE
611 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
613 /* DDR @ 0x00000000 */
614 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
617 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
622 /* PCI @ 0x80000000 */
624 #define CONFIG_PCI_INDIRECT_BRIDGE
625 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
628 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
632 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
634 | BATL_CACHEINHIBIT \
635 | BATL_GUARDEDSTORAGE)
636 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
641 #define CONFIG_SYS_IBAT1L (0)
642 #define CONFIG_SYS_IBAT1U (0)
643 #define CONFIG_SYS_IBAT2L (0)
644 #define CONFIG_SYS_IBAT2U (0)
647 #ifdef CONFIG_MPC83XX_PCI2
648 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
651 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
655 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
657 | BATL_CACHEINHIBIT \
658 | BATL_GUARDEDSTORAGE)
659 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
664 #define CONFIG_SYS_IBAT3L (0)
665 #define CONFIG_SYS_IBAT3U (0)
666 #define CONFIG_SYS_IBAT4L (0)
667 #define CONFIG_SYS_IBAT4U (0)
670 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
671 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
673 | BATL_CACHEINHIBIT \
674 | BATL_GUARDEDSTORAGE)
675 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
680 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
681 #define CONFIG_SYS_IBAT6L (0xF0000000 \
683 | BATL_MEMCOHERENCE \
684 | BATL_GUARDEDSTORAGE)
685 #define CONFIG_SYS_IBAT6U (0xF0000000 \
690 #define CONFIG_SYS_IBAT7L (0)
691 #define CONFIG_SYS_IBAT7U (0)
693 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
694 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
695 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
696 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
697 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
698 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
699 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
700 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
701 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
702 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
703 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
704 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
705 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
706 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
707 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
708 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
710 #if defined(CONFIG_CMD_KGDB)
711 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
715 * Environment Configuration
717 #define CONFIG_ENV_OVERWRITE
719 #if defined(CONFIG_TSEC_ENET)
720 #define CONFIG_HAS_ETH1
721 #define CONFIG_HAS_ETH0
724 #define CONFIG_HOSTNAME mpc8349emds
725 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
726 #define CONFIG_BOOTFILE "uImage"
728 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
730 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
732 #define CONFIG_BAUDRATE 115200
734 #define CONFIG_PREBOOT "echo;" \
735 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
738 #define CONFIG_EXTRA_ENV_SETTINGS \
740 "hostname=mpc8349emds\0" \
741 "nfsargs=setenv bootargs root=/dev/nfs rw " \
742 "nfsroot=${serverip}:${rootpath}\0" \
743 "ramargs=setenv bootargs root=/dev/ram rw\0" \
744 "addip=setenv bootargs ${bootargs} " \
745 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
746 ":${hostname}:${netdev}:off panic=1\0" \
747 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
748 "flash_nfs=run nfsargs addip addtty;" \
749 "bootm ${kernel_addr}\0" \
750 "flash_self=run ramargs addip addtty;" \
751 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
752 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
754 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
755 "update=protect off fe000000 fe03ffff; " \
756 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
757 "upd=run load update\0" \
759 "fdtfile=mpc834x_mds.dtb\0" \
762 #define CONFIG_NFSBOOTCOMMAND \
763 "setenv bootargs root=/dev/nfs rw " \
764 "nfsroot=$serverip:$rootpath " \
765 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
767 "console=$consoledev,$baudrate $othbootargs;" \
768 "tftp $loadaddr $bootfile;" \
769 "tftp $fdtaddr $fdtfile;" \
770 "bootm $loadaddr - $fdtaddr"
772 #define CONFIG_RAMBOOTCOMMAND \
773 "setenv bootargs root=/dev/ram rw " \
774 "console=$consoledev,$baudrate $othbootargs;" \
775 "tftp $ramdiskaddr $ramdiskfile;" \
776 "tftp $loadaddr $bootfile;" \
777 "tftp $fdtaddr $fdtfile;" \
778 "bootm $loadaddr $ramdiskaddr $fdtaddr"
780 #define CONFIG_BOOTCOMMAND "run flash_self"
782 #endif /* __CONFIG_H */