include/configs/MPC8349EMDS.h

   1 /*
   2  * (C) Copyright 2006-2010
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * mpc8349emds board configuration file
  10  *
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 #define CONFIG_E300             1       /* E300 Family */
  22 #define CONFIG_MPC834x          1       /* MPC834x family */
  23 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  24 #define CONFIG_MPC8349EMDS      1       /* MPC8349EMDS board specific */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  27
  28 #define CONFIG_PCI_66M
  29 #ifdef CONFIG_PCI_66M
  30 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  31 #else
  32 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  33 #endif
  34
  35 #ifdef CONFIG_PCISLAVE
  36 #define CONFIG_PCI
  37 #define CONFIG_83XX_PCICLK      66666666        /* in Hz */
  38 #endif /* CONFIG_PCISLAVE */
  39
  40 #ifndef CONFIG_SYS_CLK_FREQ
  41 #ifdef CONFIG_PCI_66M
  42 #define CONFIG_SYS_CLK_FREQ     66000000
  43 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  44 #else
  45 #define CONFIG_SYS_CLK_FREQ     33000000
  46 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  47 #endif
  48 #endif
  49
  50 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_pre_init */
  51
  52 #define CONFIG_SYS_IMMR         0xE0000000
  53
  54 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  55 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  56 #define CONFIG_SYS_MEMTEST_END          0x00100000
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  62 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  63 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  64
  65 /*
  66  * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
  67  * undefine it to use old spd_sdram.c
  68  */
  69 #define CONFIG_SYS_FSL_DDR2
  70 #ifdef CONFIG_SYS_FSL_DDR2
  71 #define CONFIG_SYS_FSL_DDRC_GEN2
  72 #define CONFIG_SYS_SPD_BUS_NUM  0
  73 #define SPD_EEPROM_ADDRESS1     0x52
  74 #define SPD_EEPROM_ADDRESS2     0x51
  75 #define CONFIG_NUM_DDR_CONTROLLERS      1
  76 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  77 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  79 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  80 #endif
  81
  82 /*
  83  * 32-bit data path mode.
  84  *
  85  * Please note that using this mode for devices with the real density of 64-bit
  86  * effectively reduces the amount of available memory due to the effect of
  87  * wrapping around while translating address to row/columns, for example in the
  88  * 256MB module the upper 128MB get aliased with contents of the lower
  89  * 128MB); normally this define should be used for devices with real 32-bit
  90  * data path.
  91  */
  92 #undef CONFIG_DDR_32BIT
  93
  94 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  95 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  96 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  97 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  98                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  99 #undef  CONFIG_DDR_2T_TIMING
 100
 101 /*
 102  * DDRCDR - DDR Control Driver Register
 103  */
 104 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
 105
 106 #if defined(CONFIG_SPD_EEPROM)
 107 /*
 108  * Determine DDR configuration from I2C interface.
 109  */
 110 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
 111 #else
 112 /*
 113  * Manually set up DDR parameters
 114  */
 115 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 116 #if defined(CONFIG_DDR_II)
 117 #define CONFIG_SYS_DDRCDR               0x80080001
 118 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
 119 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
 120 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
 121 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
 122 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
 123 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
 124 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
 125 #define CONFIG_SYS_DDR_MODE             0x47d00432
 126 #define CONFIG_SYS_DDR_MODE2            0x8000c000
 127 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
 128 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
 129 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 130 #else
 131 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
 132                                 | CSCONFIG_ROW_BIT_13 \
 133                                 | CSCONFIG_COL_BIT_10)
 134 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 135 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 136 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 137 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 138
 139 #if defined(CONFIG_DDR_32BIT)
 140 /* set burst length to 8 for 32-bit data path */
 141                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 142 #define CONFIG_SYS_DDR_MODE     0x00000023
 143 #else
 144 /* the default burst length is 4 - for 64-bit data path */
 145                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 146 #define CONFIG_SYS_DDR_MODE     0x00000022
 147 #endif
 148 #endif
 149 #endif
 150
 151 /*
 152  * SDRAM on the Local Bus
 153  */
 154 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 155 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 156
 157 /*
 158  * FLASH on the Local Bus
 159  */
 160 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 161 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 162 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 163 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 164 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 165 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 166
 167 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 168                                 | BR_PS_16      /* 16 bit port  */ \
 169                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 170                                 | BR_V)         /* valid */
 171 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 172                                 | OR_UPM_XAM \
 173                                 | OR_GPCM_CSNT \
 174                                 | OR_GPCM_ACS_DIV2 \
 175                                 | OR_GPCM_XACS \
 176                                 | OR_GPCM_SCY_15 \
 177                                 | OR_GPCM_TRLX_SET \
 178                                 | OR_GPCM_EHTR_SET \
 179                                 | OR_GPCM_EAD)
 180
 181                                         /* window base at flash base */
 182 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 183 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 184
 185 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 186 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 187
 188 #undef CONFIG_SYS_FLASH_CHECKSUM
 189 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 190 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 191
 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 193
 194 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 195 #define CONFIG_SYS_RAMBOOT
 196 #else
 197 #undef  CONFIG_SYS_RAMBOOT
 198 #endif
 199
 200 /*
 201  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 202  */
 203 #define CONFIG_SYS_BCSR                 0xE2400000
 204                                         /* Access window base at BCSR base */
 205 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_BCSR
 206 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 207 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 208                                         | BR_PS_8 \
 209                                         | BR_MS_GPCM \
 210                                         | BR_V)
 211                                         /* 0x00000801 */
 212 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 213                                         | OR_GPCM_XAM \
 214                                         | OR_GPCM_CSNT \
 215                                         | OR_GPCM_SCY_15 \
 216                                         | OR_GPCM_TRLX_CLEAR \
 217                                         | OR_GPCM_EHTR_CLEAR)
 218                                         /* 0xFFFFE8F0 */
 219
 220 #define CONFIG_SYS_INIT_RAM_LOCK        1
 221 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 222 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 223
 224 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 225                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 226 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 227
 228 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 229 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 230
 231 /*
 232  * Local Bus LCRR and LBCR regs
 233  *    LCRR:  DLL bypass, Clock divider is 4
 234  * External Local Bus rate is
 235  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 236  */
 237 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 238 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 239 #define CONFIG_SYS_LBC_LBCR     0x00000000
 240
 241 /*
 242  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
 243  * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
 244  */
 245 #undef CONFIG_SYS_LB_SDRAM
 246
 247 #ifdef CONFIG_SYS_LB_SDRAM
 248 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
 249 /*
 250  * Base Register 2 and Option Register 2 configure SDRAM.
 251  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 252  *
 253  * For BR2, need:
 254  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 255  *    port-size = 32-bits = BR2[19:20] = 11
 256  *    no parity checking = BR2[21:22] = 00
 257  *    SDRAM for MSEL = BR2[24:26] = 011
 258  *    Valid = BR[31] = 1
 259  *
 260  * 0    4    8    12   16   20   24   28
 261  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 262  */
 263
 264 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 265                                         | BR_PS_32      /* 32-bit port */ \
 266                                         | BR_MS_SDRAM   /* MSEL = SDRAM */ \
 267                                         | BR_V)         /* Valid */
 268                                         /* 0xF0001861 */
 269 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 270 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 271
 272 /*
 273  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 274  *
 275  * For OR2, need:
 276  *    64MB mask for AM, OR2[0:7] = 1111 1100
 277  *                 XAM, OR2[17:18] = 11
 278  *    9 columns OR2[19-21] = 010
 279  *    13 rows   OR2[23-25] = 100
 280  *    EAD set for extra time OR[31] = 1
 281  *
 282  * 0    4    8    12   16   20   24   28
 283  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 284  */
 285
 286 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_64MB \
 287                         | OR_SDRAM_XAM \
 288                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 289                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 290                         | OR_SDRAM_EAD)
 291                         /* 0xFC006901 */
 292
 293                                 /* LB sdram refresh timer, about 6us */
 294 #define CONFIG_SYS_LBC_LSRT     0x32000000
 295                                 /* LB refresh timer prescal, 266MHz/32 */
 296 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 297
 298 #define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN      \
 299                                 | LSDMR_BSMA1516        \
 300                                 | LSDMR_RFCR8           \
 301                                 | LSDMR_PRETOACT6       \
 302                                 | LSDMR_ACTTORW3        \
 303                                 | LSDMR_BL8             \
 304                                 | LSDMR_WRC3            \
 305                                 | LSDMR_CL3)
 306
 307 /*
 308  * SDRAM Controller configuration sequence.
 309  */
 310 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 311 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 312 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 313 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 314 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 315 #endif
 316
 317 /*
 318  * Serial Port
 319  */
 320 #define CONFIG_CONS_INDEX     1
 321 #define CONFIG_SYS_NS16550_SERIAL
 322 #define CONFIG_SYS_NS16550_REG_SIZE    1
 323 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 324
 325 #define CONFIG_SYS_BAUDRATE_TABLE  \
 326                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 327
 328 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 329 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 330
 331 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 332 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 333 /* Use the HUSH parser */
 334 #define CONFIG_SYS_HUSH_PARSER
 335
 336 /* pass open firmware flat tree */
 337 #define CONFIG_OF_LIBFDT        1
 338 #define CONFIG_OF_BOARD_SETUP   1
 339 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 340
 341 /* I2C */
 342 #define CONFIG_SYS_I2C
 343 #define CONFIG_SYS_I2C_FSL
 344 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 345 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 346 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 347 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 348 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 349 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 350 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 351
 352 /* SPI */
 353 #define CONFIG_MPC8XXX_SPI
 354 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 355
 356 /* GPIOs.  Used as SPI chip selects */
 357 #define CONFIG_SYS_GPIO1_PRELIM
 358 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 359 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 360
 361 /* TSEC */
 362 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 363 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 364 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 365 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 366
 367 /* USB */
 368 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 369
 370 /*
 371  * General PCI
 372  * Addresses are mapped 1-1.
 373  */
 374 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 375 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 376 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 377 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 378 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 379 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 380 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 381 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 382 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 383
 384 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 385 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 386 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 387 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 388 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 389 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 390 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 391 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 392 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 393
 394 #if defined(CONFIG_PCI)
 395
 396 #define PCI_ONE_PCI1
 397 #if defined(PCI_64BIT)
 398 #undef PCI_ALL_PCI1
 399 #undef PCI_TWO_PCI1
 400 #undef PCI_ONE_PCI1
 401 #endif
 402
 403 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 404 #define CONFIG_83XX_PCI_STREAMING
 405
 406 #undef CONFIG_EEPRO100
 407 #undef CONFIG_TULIP
 408
 409 #if !defined(CONFIG_PCI_PNP)
 410         #define PCI_ENET0_IOADDR        0xFIXME
 411         #define PCI_ENET0_MEMADDR       0xFIXME
 412         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 413 #endif
 414
 415 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 416 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 417
 418 #endif  /* CONFIG_PCI */
 419
 420 /*
 421  * TSEC configuration
 422  */
 423 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 424
 425 #if defined(CONFIG_TSEC_ENET)
 426
 427 #define CONFIG_GMII             1       /* MII PHY management */
 428 #define CONFIG_TSEC1            1
 429 #define CONFIG_TSEC1_NAME       "TSEC0"
 430 #define CONFIG_TSEC2            1
 431 #define CONFIG_TSEC2_NAME       "TSEC1"
 432 #define TSEC1_PHY_ADDR          0
 433 #define TSEC2_PHY_ADDR          1
 434 #define TSEC1_PHYIDX            0
 435 #define TSEC2_PHYIDX            0
 436 #define TSEC1_FLAGS             TSEC_GIGABIT
 437 #define TSEC2_FLAGS             TSEC_GIGABIT
 438
 439 /* Options are: TSEC[0-1] */
 440 #define CONFIG_ETHPRIME         "TSEC0"
 441
 442 #endif  /* CONFIG_TSEC_ENET */
 443
 444 /*
 445  * Configure on-board RTC
 446  */
 447 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 448 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 449
 450 /*
 451  * Environment
 452  */
 453 #ifndef CONFIG_SYS_RAMBOOT
 454         #define CONFIG_ENV_IS_IN_FLASH  1
 455         #define CONFIG_ENV_ADDR         \
 456                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 457         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 458         #define CONFIG_ENV_SIZE         0x2000
 459
 460 /* Address and size of Redundant Environment Sector     */
 461 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 462 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 463
 464 #else
 465         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 466         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 467         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 468         #define CONFIG_ENV_SIZE         0x2000
 469 #endif
 470
 471 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 472 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 473
 474
 475 /*
 476  * BOOTP options
 477  */
 478 #define CONFIG_BOOTP_BOOTFILESIZE
 479 #define CONFIG_BOOTP_BOOTPATH
 480 #define CONFIG_BOOTP_GATEWAY
 481 #define CONFIG_BOOTP_HOSTNAME
 482
 483
 484 /*
 485  * Command line configuration.
 486  */
 487 #define CONFIG_CMD_PING
 488 #define CONFIG_CMD_I2C
 489 #define CONFIG_CMD_DATE
 490 #define CONFIG_CMD_MII
 491
 492 #if defined(CONFIG_PCI)
 493     #define CONFIG_CMD_PCI
 494 #endif
 495
 496 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 497
 498 /*
 499  * Miscellaneous configurable options
 500  */
 501 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 502 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 503
 504 #if defined(CONFIG_CMD_KGDB)
 505         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 506 #else
 507         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 508 #endif
 509
 510                                 /* Print Buffer Size */
 511 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 512 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 513                                 /* Boot Argument Buffer Size */
 514 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 515
 516 /*
 517  * For booting Linux, the board info and command line data
 518  * have to be in the first 256 MB of memory, since this is
 519  * the maximum mapped by the Linux kernel during initialization.
 520  */
 521                                 /* Initial Memory map for Linux*/
 522 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 523
 524 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 525
 526 #if 1 /*528/264*/
 527 #define CONFIG_SYS_HRCW_LOW (\
 528         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 529         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 530         HRCWL_CSB_TO_CLKIN |\
 531         HRCWL_VCO_1X2 |\
 532         HRCWL_CORE_TO_CSB_2X1)
 533 #elif 0 /*396/132*/
 534 #define CONFIG_SYS_HRCW_LOW (\
 535         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 536         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 537         HRCWL_CSB_TO_CLKIN |\
 538         HRCWL_VCO_1X4 |\
 539         HRCWL_CORE_TO_CSB_3X1)
 540 #elif 0 /*264/132*/
 541 #define CONFIG_SYS_HRCW_LOW (\
 542         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 543         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 544         HRCWL_CSB_TO_CLKIN |\
 545         HRCWL_VCO_1X4 |\
 546         HRCWL_CORE_TO_CSB_2X1)
 547 #elif 0 /*132/132*/
 548 #define CONFIG_SYS_HRCW_LOW (\
 549         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 550         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 551         HRCWL_CSB_TO_CLKIN |\
 552         HRCWL_VCO_1X4 |\
 553         HRCWL_CORE_TO_CSB_1X1)
 554 #elif 0 /*264/264 */
 555 #define CONFIG_SYS_HRCW_LOW (\
 556         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 557         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 558         HRCWL_CSB_TO_CLKIN |\
 559         HRCWL_VCO_1X4 |\
 560         HRCWL_CORE_TO_CSB_1X1)
 561 #endif
 562
 563 #ifdef CONFIG_PCISLAVE
 564 #define CONFIG_SYS_HRCW_HIGH (\
 565         HRCWH_PCI_AGENT |\
 566         HRCWH_64_BIT_PCI |\
 567         HRCWH_PCI1_ARBITER_DISABLE |\
 568         HRCWH_PCI2_ARBITER_DISABLE |\
 569         HRCWH_CORE_ENABLE |\
 570         HRCWH_FROM_0X00000100 |\
 571         HRCWH_BOOTSEQ_DISABLE |\
 572         HRCWH_SW_WATCHDOG_DISABLE |\
 573         HRCWH_ROM_LOC_LOCAL_16BIT |\
 574         HRCWH_TSEC1M_IN_GMII |\
 575         HRCWH_TSEC2M_IN_GMII)
 576 #else
 577 #if defined(PCI_64BIT)
 578 #define CONFIG_SYS_HRCW_HIGH (\
 579         HRCWH_PCI_HOST |\
 580         HRCWH_64_BIT_PCI |\
 581         HRCWH_PCI1_ARBITER_ENABLE |\
 582         HRCWH_PCI2_ARBITER_DISABLE |\
 583         HRCWH_CORE_ENABLE |\
 584         HRCWH_FROM_0X00000100 |\
 585         HRCWH_BOOTSEQ_DISABLE |\
 586         HRCWH_SW_WATCHDOG_DISABLE |\
 587         HRCWH_ROM_LOC_LOCAL_16BIT |\
 588         HRCWH_TSEC1M_IN_GMII |\
 589         HRCWH_TSEC2M_IN_GMII)
 590 #else
 591 #define CONFIG_SYS_HRCW_HIGH (\
 592         HRCWH_PCI_HOST |\
 593         HRCWH_32_BIT_PCI |\
 594         HRCWH_PCI1_ARBITER_ENABLE |\
 595         HRCWH_PCI2_ARBITER_ENABLE |\
 596         HRCWH_CORE_ENABLE |\
 597         HRCWH_FROM_0X00000100 |\
 598         HRCWH_BOOTSEQ_DISABLE |\
 599         HRCWH_SW_WATCHDOG_DISABLE |\
 600         HRCWH_ROM_LOC_LOCAL_16BIT |\
 601         HRCWH_TSEC1M_IN_GMII |\
 602         HRCWH_TSEC2M_IN_GMII)
 603 #endif /* PCI_64BIT */
 604 #endif /* CONFIG_PCISLAVE */
 605
 606 /*
 607  * System performance
 608  */
 609 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 610 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 611 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 612 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 613 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 614 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 615
 616 /* System IO Config */
 617 #define CONFIG_SYS_SICRH 0
 618 #define CONFIG_SYS_SICRL SICRL_LDP_A
 619
 620 #define CONFIG_SYS_HID0_INIT    0x000000000
 621 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 622                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 623
 624 /* #define CONFIG_SYS_HID0_FINAL        (\
 625         HID0_ENABLE_INSTRUCTION_CACHE |\
 626         HID0_ENABLE_M_BIT |\
 627         HID0_ENABLE_ADDRESS_BROADCAST) */
 628
 629
 630 #define CONFIG_SYS_HID2 HID2_HBE
 631 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 632
 633 /* DDR @ 0x00000000 */
 634 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 635                                 | BATL_PP_RW \
 636                                 | BATL_MEMCOHERENCE)
 637 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 638                                 | BATU_BL_256M \
 639                                 | BATU_VS \
 640                                 | BATU_VP)
 641
 642 /* PCI @ 0x80000000 */
 643 #ifdef CONFIG_PCI
 644 #define CONFIG_PCI_INDIRECT_BRIDGE
 645 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 646                                 | BATL_PP_RW \
 647                                 | BATL_MEMCOHERENCE)
 648 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 649                                 | BATU_BL_256M \
 650                                 | BATU_VS \
 651                                 | BATU_VP)
 652 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 653                                 | BATL_PP_RW \
 654                                 | BATL_CACHEINHIBIT \
 655                                 | BATL_GUARDEDSTORAGE)
 656 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 657                                 | BATU_BL_256M \
 658                                 | BATU_VS \
 659                                 | BATU_VP)
 660 #else
 661 #define CONFIG_SYS_IBAT1L       (0)
 662 #define CONFIG_SYS_IBAT1U       (0)
 663 #define CONFIG_SYS_IBAT2L       (0)
 664 #define CONFIG_SYS_IBAT2U       (0)
 665 #endif
 666
 667 #ifdef CONFIG_MPC83XX_PCI2
 668 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 669                                 | BATL_PP_RW \
 670                                 | BATL_MEMCOHERENCE)
 671 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 672                                 | BATU_BL_256M \
 673                                 | BATU_VS \
 674                                 | BATU_VP)
 675 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 676                                 | BATL_PP_RW \
 677                                 | BATL_CACHEINHIBIT \
 678                                 | BATL_GUARDEDSTORAGE)
 679 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 680                                 | BATU_BL_256M \
 681                                 | BATU_VS \
 682                                 | BATU_VP)
 683 #else
 684 #define CONFIG_SYS_IBAT3L       (0)
 685 #define CONFIG_SYS_IBAT3U       (0)
 686 #define CONFIG_SYS_IBAT4L       (0)
 687 #define CONFIG_SYS_IBAT4U       (0)
 688 #endif
 689
 690 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
 691 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 692                                 | BATL_PP_RW \
 693                                 | BATL_CACHEINHIBIT \
 694                                 | BATL_GUARDEDSTORAGE)
 695 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 696                                 | BATU_BL_256M \
 697                                 | BATU_VS \
 698                                 | BATU_VP)
 699
 700 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 701 #define CONFIG_SYS_IBAT6L       (0xF0000000 \
 702                                 | BATL_PP_RW \
 703                                 | BATL_MEMCOHERENCE \
 704                                 | BATL_GUARDEDSTORAGE)
 705 #define CONFIG_SYS_IBAT6U       (0xF0000000 \
 706                                 | BATU_BL_256M \
 707                                 | BATU_VS \
 708                                 | BATU_VP)
 709
 710 #define CONFIG_SYS_IBAT7L       (0)
 711 #define CONFIG_SYS_IBAT7U       (0)
 712
 713 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 714 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 715 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 716 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 717 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 718 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 719 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 720 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 721 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 722 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 723 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 724 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 725 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 726 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 727 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 728 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 729
 730 #if defined(CONFIG_CMD_KGDB)
 731 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 732 #endif
 733
 734 /*
 735  * Environment Configuration
 736  */
 737 #define CONFIG_ENV_OVERWRITE
 738
 739 #if defined(CONFIG_TSEC_ENET)
 740 #define CONFIG_HAS_ETH1
 741 #define CONFIG_HAS_ETH0
 742 #endif
 743
 744 #define CONFIG_HOSTNAME         mpc8349emds
 745 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 746 #define CONFIG_BOOTFILE         "uImage"
 747
 748 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 749
 750 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 751 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 752
 753 #define CONFIG_BAUDRATE  115200
 754
 755 #define CONFIG_PREBOOT  "echo;" \
 756         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 757         "echo"
 758
 759 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 760         "netdev=eth0\0"                                                 \
 761         "hostname=mpc8349emds\0"                                        \
 762         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 763                 "nfsroot=${serverip}:${rootpath}\0"                     \
 764         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 765         "addip=setenv bootargs ${bootargs} "                            \
 766                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 767                 ":${hostname}:${netdev}:off panic=1\0"                  \
 768         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 769         "flash_nfs=run nfsargs addip addtty;"                           \
 770                 "bootm ${kernel_addr}\0"                                \
 771         "flash_self=run ramargs addip addtty;"                          \
 772                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 773         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 774                 "bootm\0"                                               \
 775         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 776         "update=protect off fe000000 fe03ffff; "                        \
 777                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 778         "upd=run load update\0"                                         \
 779         "fdtaddr=780000\0"                                              \
 780         "fdtfile=mpc834x_mds.dtb\0"                                     \
 781         ""
 782
 783 #define CONFIG_NFSBOOTCOMMAND                                           \
 784         "setenv bootargs root=/dev/nfs rw "                             \
 785                 "nfsroot=$serverip:$rootpath "                          \
 786                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 787                                                         "$netdev:off "  \
 788                 "console=$consoledev,$baudrate $othbootargs;"           \
 789         "tftp $loadaddr $bootfile;"                                     \
 790         "tftp $fdtaddr $fdtfile;"                                       \
 791         "bootm $loadaddr - $fdtaddr"
 792
 793 #define CONFIG_RAMBOOTCOMMAND                                           \
 794         "setenv bootargs root=/dev/ram rw "                             \
 795                 "console=$consoledev,$baudrate $othbootargs;"           \
 796         "tftp $ramdiskaddr $ramdiskfile;"                               \
 797         "tftp $loadaddr $bootfile;"                                     \
 798         "tftp $fdtaddr $fdtfile;"                                       \
 799         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 800
 801 #define CONFIG_BOOTCOMMAND      "run flash_self"
 802
 803 #endif  /* __CONFIG_H */