2 * Copyright 2004 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * mpc8349ads board configuration file
26 * Please refer to doc/README.mpc83xxads for more info.
37 * High Level Configuration Options
39 #define CONFIG_E300 1 /* E300 Family */
40 #define CONFIG_MPC83XX 1 /* MPC83XX family */
41 #define CONFIG_MPC8349 1 /* MPC8349 specific */
42 #define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
45 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
46 #define CONFIG_TSEC_ENET /* tsec ethernet support */
47 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
51 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
55 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
57 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
60 #ifndef CONFIG_SYS_CLK_FREQ
62 #define CONFIG_SYS_CLK_FREQ 66000000
64 #define CONFIG_SYS_CLK_FREQ 33000000
68 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
70 #define CFG_IMMRBAR 0xE0000000
72 #undef CFG_DRAM_TEST /* memory test, takes time */
73 #define CFG_MEMTEST_START 0x00000000 /* memtest region */
74 #define CFG_MEMTEST_END 0x00100000
80 #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
81 #define CFG_SDRAM_BASE CFG_DDR_BASE
82 #undef CONFIG_DDR_2T_TIMING
83 #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
85 #if defined(CONFIG_SPD_EEPROM)
87 * Determine DDR configuration from I2C interface.
89 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
92 * Manually set up DDR parameters
94 #define CFG_DDR_SIZE 256 /* Mb */
95 #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
96 #define CFG_DDR_TIMING_1 0x37344321
97 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
98 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
99 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
100 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
104 * SDRAM on the Local Bus
106 #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
107 #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
110 * FLASH on the Local Bus
112 #define CFG_FLASH_CFI /* use the Common Flash Interface */
113 #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
114 #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
115 #define CFG_FLASH_SIZE 8 /* FLASH size in MB */
116 /* #define CFG_FLASH_USE_BUFFER_WRITE */
118 #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
119 (2 << BR_PS_SHIFT) | /* 32 bit port size */ \
121 #define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/
122 #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
123 #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */
125 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
126 #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
128 #undef CFG_FLASH_CHECKSUM
129 #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
130 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
132 #define CFG_MID_FLASH_JUMP 0x7F000000
133 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
135 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
142 * BCSR register on local bus 32KB, 8-bit wide for ADS config reg
144 #define CFG_BCSR 0xF8000000
145 #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
146 #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
147 #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
148 #define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */
150 #define CONFIG_L1_INIT_RAM
151 #define CFG_INIT_RAM_LOCK 1
152 #define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
153 #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
155 #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
156 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
157 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
159 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
160 #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
163 * Local Bus LCRR and LBCR regs
164 * LCRR: DLL bypass, Clock divider is 4
165 * External Local Bus rate is
166 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
168 #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
169 #define CFG_LBC_LBCR 0x00000000
171 #define CFG_LB_SDRAM /* if board has SRDAM on local bus */
174 /*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
176 * Base Register 2 and Option Register 2 configure SDRAM.
177 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
180 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
181 * port-size = 32-bits = BR2[19:20] = 11
182 * no parity checking = BR2[21:22] = 00
183 * SDRAM for MSEL = BR2[24:26] = 011
186 * 0 4 8 12 16 20 24 28
187 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
189 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
190 * FIXME: the top 17 bits of BR2.
193 #define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
194 #define CFG_LBLAWBAR2_PRELIM 0xF0000000
195 #define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
198 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
201 * 64MB mask for AM, OR2[0:7] = 1111 1100
202 * XAM, OR2[17:18] = 11
203 * 9 columns OR2[19-21] = 010
204 * 13 rows OR2[23-25] = 100
205 * EAD set for extra time OR[31] = 1
207 * 0 4 8 12 16 20 24 28
208 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
211 #define CFG_OR2_PRELIM 0xfc006901
213 #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
214 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
219 #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
220 #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
221 #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
222 #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
223 #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
224 #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
225 #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
226 #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
227 #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
228 #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
229 #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
230 #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
231 #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
232 #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
233 #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
234 #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
235 #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
236 #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
238 #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
239 #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
240 #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
241 #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
242 #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
243 #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
244 #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
245 #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
247 #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
248 | CFG_LBC_LSDMR_BSMA1516 \
249 | CFG_LBC_LSDMR_RFCR8 \
250 | CFG_LBC_LSDMR_PRETOACT6 \
251 | CFG_LBC_LSDMR_ACTTORW3 \
252 | CFG_LBC_LSDMR_BL8 \
253 | CFG_LBC_LSDMR_WRC3 \
254 | CFG_LBC_LSDMR_CL3 \
258 * SDRAM Controller configuration sequence.
260 #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
261 | CFG_LBC_LSDMR_OP_PCHALL)
262 #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
263 | CFG_LBC_LSDMR_OP_ARFRSH)
264 #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
265 | CFG_LBC_LSDMR_OP_ARFRSH)
266 #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
267 | CFG_LBC_LSDMR_OP_MRW)
268 #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
269 | CFG_LBC_LSDMR_OP_NORMAL)
275 #define CONFIG_CONS_INDEX 1
276 #undef CONFIG_SERIAL_SOFTWARE_FIFO
278 #define CFG_NS16550_SERIAL
279 #define CFG_NS16550_REG_SIZE 1
280 #define CFG_NS16550_CLK get_bus_freq(0)
282 #define CFG_BAUDRATE_TABLE \
283 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
285 #define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500)
286 #define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600)
288 /* Use the HUSH parser */
289 #define CFG_HUSH_PARSER
290 #ifdef CFG_HUSH_PARSER
291 #define CFG_PROMPT_HUSH_PS2 "> "
295 #define CONFIG_HARD_I2C /* I2C with hardware support*/
296 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
297 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
298 #define CFG_I2C_SLAVE 0x7F
299 #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
300 #define CFG_I2C_OFFSET 0x3000
301 #define CFG_I2C2_OFFSET 0x3100
304 #define CFG_TSEC1_OFFSET 0x24000
305 #define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET)
306 #define CFG_TSEC2_OFFSET 0x25000
307 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
309 /* IO Configuration */
310 #define CFG_IO_CONF (\
324 * Addresses are mapped 1-1.
327 #define CFG_PCI1_MEM_BASE 0x80000000
328 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
329 #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
330 #define CFG_PCI1_MMIO_BASE 0x90000000
331 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
332 #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
333 #define CFG_PCI1_IO_BASE 0x00000000
334 #define CFG_PCI1_IO_PHYS 0xe2000000
335 #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
337 #define CFG_PCI2_MEM_BASE 0xa0000000
338 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
339 #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
340 #define CFG_PCI2_MMIO_BASE 0xb0000000
341 #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
342 #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
343 #define CFG_PCI2_IO_BASE 0x00000000
344 #define CFG_PCI2_IO_PHYS 0xe2100000
345 #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
346 #if defined(CONFIG_PCI)
349 #if defined(PCI_64BIT)
355 #define CONFIG_NET_MULTI
356 #define CONFIG_PCI_PNP /* do pci plug-and-play */
358 #undef CONFIG_EEPRO100
361 #if !defined(CONFIG_PCI_PNP)
362 #define PCI_ENET0_IOADDR 0xFIXME
363 #define PCI_ENET0_MEMADDR 0xFIXME
364 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
367 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
368 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
370 #endif /* CONFIG_PCI */
372 #if defined(CONFIG_TSEC_ENET)
373 #ifndef CONFIG_NET_MULTI
374 #define CONFIG_NET_MULTI 1
377 #define CONFIG_GMII 1 /* MII PHY management */
378 #define CONFIG_MPC83XX_TSEC1 1
379 #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
380 #define CONFIG_MPC83XX_TSEC2 1
381 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
382 #define TSEC1_PHY_ADDR 0
383 #define TSEC2_PHY_ADDR 1
384 #define TSEC1_PHYIDX 0
385 #define TSEC2_PHYIDX 0
387 /* Options are: TSEC[0-1] */
388 #define CONFIG_ETHPRIME "TSEC0"
390 #endif /* CONFIG_TSEC_ENET */
396 #define CFG_ENV_IS_IN_FLASH 1
397 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
398 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
399 #define CFG_ENV_SIZE 0x2000
401 #define CFG_NO_FLASH 1 /* Flash is not usable now */
402 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
403 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
404 #define CFG_ENV_SIZE 0x2000
407 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
408 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
410 #if defined(CFG_RAMBOOT)
411 #if defined(CONFIG_PCI)
412 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
420 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
428 #if defined(CONFIG_PCI)
429 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
434 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
442 #include <cmd_confdefs.h>
444 #undef CONFIG_WATCHDOG /* watchdog disabled */
447 * Miscellaneous configurable options
449 #define CFG_LONGHELP /* undef to save memory */
450 #define CFG_LOAD_ADDR 0x2000000 /* default load address */
451 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
453 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
454 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
456 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
459 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
460 #define CFG_MAXARGS 16 /* max number of command args */
461 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
462 #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
465 * For booting Linux, the board info and command line data
466 * have to be in the first 8 MB of memory, since this is
467 * the maximum mapped by the Linux kernel during initialization.
469 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
471 /* Cache Configuration */
472 #define CFG_DCACHE_SIZE 32768
473 #define CFG_CACHELINE_SIZE 32
474 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
475 #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
478 #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
480 #define CFG_HRCW_LOW (\
481 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
482 HRCWL_DDR_TO_SCB_CLK_1X1 |\
483 HRCWL_CSB_TO_CLKIN_4X1 |\
485 HRCWL_CORE_TO_CSB_2X1)
487 #if defined(PCI_64BIT)
488 #define CFG_HRCW_HIGH (\
491 HRCWH_PCI1_ARBITER_ENABLE |\
492 HRCWH_PCI2_ARBITER_DISABLE |\
494 HRCWH_FROM_0X00000100 |\
495 HRCWH_BOOTSEQ_DISABLE |\
496 HRCWH_SW_WATCHDOG_DISABLE |\
497 HRCWH_ROM_LOC_LOCAL_16BIT |\
498 HRCWH_TSEC1M_IN_GMII |\
499 HRCWH_TSEC2M_IN_GMII )
501 #define CFG_HRCW_HIGH (\
504 HRCWH_PCI1_ARBITER_ENABLE |\
505 HRCWH_PCI2_ARBITER_ENABLE |\
507 HRCWH_FROM_0X00000100 |\
508 HRCWH_BOOTSEQ_DISABLE |\
509 HRCWH_SW_WATCHDOG_DISABLE |\
510 HRCWH_ROM_LOC_LOCAL_16BIT |\
511 HRCWH_TSEC1M_IN_GMII |\
512 HRCWH_TSEC2M_IN_GMII )
515 /* System IO Config */
516 #define CFG_SICRH SICRH_TSOBI1
517 #define CFG_SICRL SICRL_LDP_A
519 #define CFG_HID0_INIT 0x000000000
521 #define CFG_HID0_FINAL CFG_HID0_INIT
523 /* #define CFG_HID0_FINAL (\
524 HID0_ENABLE_INSTRUCTION_CACHE |\
526 HID0_ENABLE_ADDRESS_BROADCAST ) */
528 #define CFG_HID2 HID2_HBE
531 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
532 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
534 /* stack in DCACHE @ 1GB (no backing mem) */
535 #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
536 #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
540 #define CFG_IBAT2L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
541 #define CFG_IBAT2U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
542 #define CFG_IBAT3L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
543 #define CFG_IBAT3U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
545 #define CFG_IBAT2L (0)
546 #define CFG_IBAT2U (0)
547 #define CFG_IBAT3L (0)
548 #define CFG_IBAT3U (0)
551 #ifdef CONFIG_MPC83XX_PCI2
552 #define CFG_IBAT4L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
553 #define CFG_IBAT4U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
554 #define CFG_IBAT5L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
555 #define CFG_IBAT5U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
557 #define CFG_IBAT4L (0)
558 #define CFG_IBAT4U (0)
559 #define CFG_IBAT5L (0)
560 #define CFG_IBAT5U (0)
564 #define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
565 #define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
567 /* SDRAM, BCSR & FLASH */
568 #define CFG_IBAT7L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
569 #define CFG_IBAT7U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
571 #define CFG_DBAT0L CFG_IBAT0L
572 #define CFG_DBAT0U CFG_IBAT0U
573 #define CFG_DBAT1L CFG_IBAT1L
574 #define CFG_DBAT1U CFG_IBAT1U
575 #define CFG_DBAT2L CFG_IBAT2L
576 #define CFG_DBAT2U CFG_IBAT2U
577 #define CFG_DBAT3L CFG_IBAT3L
578 #define CFG_DBAT3U CFG_IBAT3U
579 #define CFG_DBAT4L CFG_IBAT4L
580 #define CFG_DBAT4U CFG_IBAT4U
581 #define CFG_DBAT5L CFG_IBAT5L
582 #define CFG_DBAT5U CFG_IBAT5U
583 #define CFG_DBAT6L CFG_IBAT6L
584 #define CFG_DBAT6U CFG_IBAT6U
585 #define CFG_DBAT7L CFG_IBAT7L
586 #define CFG_DBAT7U CFG_IBAT7U
590 * Internal Definitions
594 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
595 #define BOOTFLAG_WARM 0x02 /* Software reboot */
597 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
598 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
599 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
603 * Environment Configuration
606 #if defined(CONFIG_TSEC_ENET)
607 #define CONFIG_ETHADDR 00:04:9f:11:22:33
608 #define CONFIG_HAS_ETH1
609 #define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01
612 #define CONFIG_IPADDR 192.168.1.253
614 #define CONFIG_HOSTNAME unknown
615 #define CONFIG_ROOTPATH /nfsroot
616 #define CONFIG_BOOTFILE your.uImage
618 #define CONFIG_SERVERIP 192.168.1.1
619 #define CONFIG_GATEWAYIP 192.168.1.1
620 #define CONFIG_NETMASK 255.255.255.0
622 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
624 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
625 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
627 #define CONFIG_BAUDRATE 115200
630 #define CONFIG_EXTRA_ENV_SETTINGS \
632 "consoledev=ttyS0\0" \
633 "ramdiskaddr=400000\0" \
634 "ramdiskfile=ramfs.83xx\0"
636 #define CONFIG_NFSBOOTCOMMAND \
637 "setenv bootargs root=/dev/nfs rw " \
638 "nfsroot=$serverip:$rootpath " \
639 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
640 "console=$consoledev,$baudrate $othbootargs;" \
641 "tftp $loadaddr $bootfile;" \
644 #define CONFIG_RAMBOOTCOMMAND \
645 "setenv bootargs root=/dev/ram rw " \
646 "console=$consoledev,$baudrate $othbootargs;" \
647 "tftp $ramdiskaddr $ramdiskfile;" \
648 "tftp $loadaddr $bootfile;" \
649 "bootm $loadaddr $ramdiskaddr"
651 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
653 #endif /* __CONFIG_H */