2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * High Level Configuration Options
26 #define CONFIG_E300 1 /* E300 family */
27 #define CONFIG_QE 1 /* Has QE */
28 #define CONFIG_MPC83xx 1 /* MPC83xx family */
29 #define CONFIG_MPC832x 1 /* MPC832x CPU specific */
30 #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
32 #define CONFIG_SYS_TEXT_BASE 0xFE000000
37 #ifdef CONFIG_PCISLAVE
38 #define CONFIG_83XX_PCICLK 66000000 /* in HZ */
40 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
43 #ifndef CONFIG_SYS_CLK_FREQ
44 #define CONFIG_SYS_CLK_FREQ 66000000
48 * Hardware Reset Configuration Word
50 #define CONFIG_SYS_HRCW_LOW (\
51 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_2X1 |\
54 HRCWL_CSB_TO_CLKIN_2X1 |\
55 HRCWL_CORE_TO_CSB_2X1 |\
56 HRCWL_CE_PLL_VCO_DIV_2 |\
57 HRCWL_CE_PLL_DIV_1X1 |\
60 #ifdef CONFIG_PCISLAVE
61 #define CONFIG_SYS_HRCW_HIGH (\
63 HRCWH_PCI1_ARBITER_DISABLE |\
65 HRCWH_FROM_0XFFF00100 |\
66 HRCWH_BOOTSEQ_DISABLE |\
67 HRCWH_SW_WATCHDOG_DISABLE |\
68 HRCWH_ROM_LOC_LOCAL_16BIT |\
72 #define CONFIG_SYS_HRCW_HIGH (\
74 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
87 #define CONFIG_SYS_SICRL 0x00000000
89 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
90 #define CONFIG_BOARD_EARLY_INIT_R
95 #define CONFIG_SYS_IMMR 0xE0000000
100 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
102 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
103 #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
105 #undef CONFIG_SPD_EEPROM
106 #if defined(CONFIG_SPD_EEPROM)
107 /* Determine DDR configuration from I2C interface
109 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
111 /* Manually set up DDR parameters
113 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
114 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
116 | CSCONFIG_ODT_WR_CFG \
117 | CSCONFIG_ROW_BIT_13 \
118 | CSCONFIG_COL_BIT_10)
120 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
121 | (0 << TIMING_CFG0_WRT_SHIFT) \
122 | (0 << TIMING_CFG0_RRT_SHIFT) \
123 | (0 << TIMING_CFG0_WWT_SHIFT) \
124 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
125 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
126 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
127 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
129 #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
130 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
131 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
132 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
133 | (13 << TIMING_CFG1_REFREC_SHIFT) \
134 | (3 << TIMING_CFG1_WRREC_SHIFT) \
135 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
136 | (2 << TIMING_CFG1_WRTORD_SHIFT))
138 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
139 | (31 << TIMING_CFG2_CPO_SHIFT) \
140 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
141 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
142 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
143 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
144 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
146 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
147 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
149 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
150 | (0x0232 << SDRAM_MODE_SD_SHIFT))
152 #define CONFIG_SYS_DDR_MODE2 0x8000c000
153 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
154 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
156 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
157 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
158 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
161 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
167 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
168 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
169 #define CONFIG_SYS_MEMTEST_END 0x00100000
172 * The reserved memory
174 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
176 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
177 #define CONFIG_SYS_RAMBOOT
179 #undef CONFIG_SYS_RAMBOOT
182 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
183 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
184 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
187 * Initial RAM Base Address Setup
189 #define CONFIG_SYS_INIT_RAM_LOCK 1
190 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
191 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
192 #define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
196 * Local Bus Configuration & Clock Setup
198 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
199 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
200 #define CONFIG_SYS_LBC_LBCR 0x00000000
203 * FLASH on the Local Bus
205 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
206 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
207 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
208 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
209 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
211 /* Window base at flash base */
212 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
213 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
215 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
216 | BR_PS_16 /* 16 bit port */ \
217 | BR_MS_GPCM /* MSEL = GPCM */ \
219 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
231 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
233 #undef CONFIG_SYS_FLASH_CHECKSUM
236 * BCSR on the Local Bus
238 #define CONFIG_SYS_BCSR 0xF8000000
239 /* Access window base at BCSR base */
240 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
241 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
243 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
247 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
258 * Windows to access PIB via local bus
260 /* PIB window base 0xF8008000 */
261 #define CONFIG_SYS_PIB_BASE 0xF8008000
262 #define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
263 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
264 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
267 * CS2 on Local Bus, to PIB
269 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
274 #define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
285 * CS3 on Local Bus, to PIB
287 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
288 CONFIG_SYS_PIB_WINDOW_SIZE) \
293 #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
306 #define CONFIG_CONS_INDEX 1
307 #define CONFIG_SYS_NS16550
308 #define CONFIG_SYS_NS16550_SERIAL
309 #define CONFIG_SYS_NS16550_REG_SIZE 1
310 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
312 #define CONFIG_SYS_BAUDRATE_TABLE \
313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
315 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
316 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
318 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
319 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
320 /* Use the HUSH parser */
321 #define CONFIG_SYS_HUSH_PARSER
323 /* pass open firmware flat tree */
324 #define CONFIG_OF_LIBFDT 1
325 #define CONFIG_OF_BOARD_SETUP 1
326 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
329 #define CONFIG_HARD_I2C /* I2C with hardware support */
330 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
331 #define CONFIG_FSL_I2C
332 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
333 #define CONFIG_SYS_I2C_SLAVE 0x7F
334 #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
335 #define CONFIG_SYS_I2C_OFFSET 0x3000
338 * Config on-board RTC
340 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
341 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
345 * Addresses are mapped 1-1.
347 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
348 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
349 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
350 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
351 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
352 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
353 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
354 #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
355 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
357 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
358 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
359 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
364 #define CONFIG_PCI_PNP /* do pci plug-and-play */
365 #define CONFIG_83XX_PCI_STREAMING
367 #undef CONFIG_EEPRO100
368 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
369 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
371 #endif /* CONFIG_PCI */
374 * QE UEC ethernet configuration
376 #define CONFIG_UEC_ETH
377 #define CONFIG_ETHPRIME "UEC0"
379 #define CONFIG_UEC_ETH1 /* ETH3 */
381 #ifdef CONFIG_UEC_ETH1
382 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
383 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
384 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
385 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
386 #define CONFIG_SYS_UEC1_PHY_ADDR 3
387 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
388 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
391 #define CONFIG_UEC_ETH2 /* ETH4 */
393 #ifdef CONFIG_UEC_ETH2
394 #define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
395 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
396 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
397 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
398 #define CONFIG_SYS_UEC2_PHY_ADDR 4
399 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
400 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
406 #ifndef CONFIG_SYS_RAMBOOT
407 #define CONFIG_ENV_IS_IN_FLASH 1
408 #define CONFIG_ENV_ADDR \
409 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
410 #define CONFIG_ENV_SECT_SIZE 0x20000
411 #define CONFIG_ENV_SIZE 0x2000
413 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
414 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
415 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
416 #define CONFIG_ENV_SIZE 0x2000
419 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
420 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
425 #define CONFIG_BOOTP_BOOTFILESIZE
426 #define CONFIG_BOOTP_BOOTPATH
427 #define CONFIG_BOOTP_GATEWAY
428 #define CONFIG_BOOTP_HOSTNAME
432 * Command line configuration.
434 #include <config_cmd_default.h>
436 #define CONFIG_CMD_PING
437 #define CONFIG_CMD_I2C
438 #define CONFIG_CMD_ASKENV
440 #if defined(CONFIG_PCI)
441 #define CONFIG_CMD_PCI
444 #if defined(CONFIG_SYS_RAMBOOT)
445 #undef CONFIG_CMD_SAVEENV
446 #undef CONFIG_CMD_LOADS
450 #undef CONFIG_WATCHDOG /* watchdog disabled */
453 * Miscellaneous configurable options
455 #define CONFIG_SYS_LONGHELP /* undef to save memory */
456 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
457 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
459 #if defined(CONFIG_CMD_KGDB)
460 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
462 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
465 /* Print Buffer Size */
466 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
467 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
468 /* Boot Argument Buffer Size */
469 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
470 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
473 * For booting Linux, the board info and command line data
474 * have to be in the first 256 MB of memory, since this is
475 * the maximum mapped by the Linux kernel during initialization.
477 /* Initial Memory map for Linux */
478 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
483 #define CONFIG_SYS_HID0_INIT 0x000000000
484 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
485 HID0_ENABLE_INSTRUCTION_CACHE)
486 #define CONFIG_SYS_HID2 HID2_HBE
492 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
494 /* DDR: cache cacheable */
495 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
498 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
502 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
503 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
505 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
506 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
508 | BATL_CACHEINHIBIT \
509 | BATL_GUARDEDSTORAGE)
510 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
514 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
515 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
517 /* BCSR: cache-inhibit and guarded */
518 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
520 | BATL_CACHEINHIBIT \
521 | BATL_GUARDEDSTORAGE)
522 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
526 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
527 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
529 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
530 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
533 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
537 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
539 | BATL_CACHEINHIBIT \
540 | BATL_GUARDEDSTORAGE)
541 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
543 #define CONFIG_SYS_IBAT4L (0)
544 #define CONFIG_SYS_IBAT4U (0)
545 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
546 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
548 /* Stack in dcache: cacheable, no memory coherence */
549 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
550 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
554 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
555 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
558 /* PCI MEM space: cacheable */
559 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
562 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
566 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
567 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
568 /* PCI MMIO space: cache-inhibit and guarded */
569 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
571 | BATL_CACHEINHIBIT \
572 | BATL_GUARDEDSTORAGE)
573 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
577 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
578 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
580 #define CONFIG_SYS_IBAT6L (0)
581 #define CONFIG_SYS_IBAT6U (0)
582 #define CONFIG_SYS_IBAT7L (0)
583 #define CONFIG_SYS_IBAT7U (0)
584 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
585 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
586 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
587 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
590 #if defined(CONFIG_CMD_KGDB)
591 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
592 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
596 * Environment Configuration
597 */ #define CONFIG_ENV_OVERWRITE
599 #if defined(CONFIG_UEC_ETH)
600 #define CONFIG_HAS_ETH0
601 #define CONFIG_HAS_ETH1
604 #define CONFIG_BAUDRATE 115200
606 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
608 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
609 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
611 #define CONFIG_EXTRA_ENV_SETTINGS \
613 "consoledev=ttyS0\0" \
614 "ramdiskaddr=1000000\0" \
615 "ramdiskfile=ramfs.83xx\0" \
617 "fdtfile=mpc832x_mds.dtb\0" \
620 #define CONFIG_NFSBOOTCOMMAND \
621 "setenv bootargs root=/dev/nfs rw " \
622 "nfsroot=$serverip:$rootpath " \
623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
625 "console=$consoledev,$baudrate $othbootargs;" \
626 "tftp $loadaddr $bootfile;" \
627 "tftp $fdtaddr $fdtfile;" \
628 "bootm $loadaddr - $fdtaddr"
630 #define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
639 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
641 #endif /* __CONFIG_H */