include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16
  17 /*
  18  * System IO Config
  19  */
  20 #define CONFIG_SYS_SICRL                0x00000000
  21
  22 /*
  23  * DDR Setup
  24  */
  25 #define CONFIG_SYS_SDRAM_BASE   0x00000000      /* DDR is system memory */
  26
  27 #undef CONFIG_SPD_EEPROM
  28 #if defined(CONFIG_SPD_EEPROM)
  29 /* Determine DDR configuration from I2C interface
  30  */
  31 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  32 #else
  33 /* Manually set up DDR parameters
  34  */
  35 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  36 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  37                                 | CSCONFIG_ROW_BIT_13 \
  38                                 | CSCONFIG_COL_BIT_9)
  39                                 /* 0x80010101 */
  40 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  41                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  42                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  43                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  44                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  45                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  46                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  47                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  48                                 /* 0x00220802 */
  49 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  50                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  51                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  52                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  53                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  54                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  55                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  56                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  57                                 /* 0x26253222 */
  58 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  59                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  60                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  61                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  62                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  63                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  64                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  65                                 /* 0x1f9048c7 */
  66 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  67 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  68                                 /* 0x02000000 */
  69 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  70                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  71                                 /* 0x44480232 */
  72 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  73 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  74                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  75                                 /* 0x03200064 */
  76 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  77 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  78                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  79                                 | SDRAM_CFG_32_BE)
  80                                 /* 0x43080000 */
  81 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  82 #endif
  83
  84 /*
  85  * Memory test
  86  */
  87 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  88
  89 /*
  90  * The reserved memory
  91  */
  92 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  93
  94 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  95 #define CONFIG_SYS_RAMBOOT
  96 #else
  97 #undef  CONFIG_SYS_RAMBOOT
  98 #endif
  99
 100 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 101 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 102 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 103
 104 /*
 105  * Initial RAM Base Address Setup
 106  */
 107 #define CONFIG_SYS_INIT_RAM_LOCK        1
 108 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 109 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 110 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 111                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112
 113 /*
 114  * FLASH on the Local Bus
 115  */
 116 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 117 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 118
 119
 120
 121 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 122 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 123
 124 #undef CONFIG_SYS_FLASH_CHECKSUM
 125
 126 /*
 127  * Serial Port
 128  */
 129 #define CONFIG_SYS_NS16550_SERIAL
 130 #define CONFIG_SYS_NS16550_REG_SIZE     1
 131 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 132
 133 #define CONFIG_SYS_BAUDRATE_TABLE  \
 134                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 135
 136 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 137 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 138
 139 /* I2C */
 140 #define CONFIG_SYS_I2C
 141 #define CONFIG_SYS_I2C_FSL
 142 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 143 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 144 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 145 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 146
 147 /*
 148  * Config on-board EEPROM
 149  */
 150 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 152 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 154
 155 /*
 156  * General PCI
 157  * Addresses are mapped 1-1.
 158  */
 159 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 160 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 161 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 162 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 163 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 164 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 165 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 166 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 167 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 168
 169 #ifdef CONFIG_PCI
 170 #define CONFIG_PCI_INDIRECT_BRIDGE
 171 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 172
 173 #undef CONFIG_EEPRO100
 174 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 175 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 176
 177 #endif  /* CONFIG_PCI */
 178
 179 /*
 180  * QE UEC ethernet configuration
 181  */
 182 #define CONFIG_UEC_ETH
 183 #define CONFIG_ETHPRIME         "UEC0"
 184
 185 #define CONFIG_UEC_ETH1         /* ETH3 */
 186
 187 #ifdef CONFIG_UEC_ETH1
 188 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 189 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 190 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 191 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 192 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 193 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 194 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 195 #endif
 196
 197 #define CONFIG_UEC_ETH2         /* ETH4 */
 198
 199 #ifdef CONFIG_UEC_ETH2
 200 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 201 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 202 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 203 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 204 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 205 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 206 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 207 #endif
 208
 209 /*
 210  * Environment
 211  */
 212
 213 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 214 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 215
 216 /*
 217  * BOOTP options
 218  */
 219 #define CONFIG_BOOTP_BOOTFILESIZE
 220
 221 /*
 222  * Command line configuration.
 223  */
 224
 225 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 226
 227 /*
 228  * Miscellaneous configurable options
 229  */
 230 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 231
 232 /*
 233  * For booting Linux, the board info and command line data
 234  * have to be in the first 256 MB of memory, since this is
 235  * the maximum mapped by the Linux kernel during initialization.
 236  */
 237                                         /* Initial Memory map for Linux */
 238 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 239 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 240
 241 #if (CONFIG_CMD_KGDB)
 242 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 243 #endif
 244
 245 /*
 246  * Environment Configuration
 247  */
 248 #define CONFIG_ENV_OVERWRITE
 249
 250 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 251 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 252
 253 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 254  * (see CONFIG_SYS_I2C_EEPROM) */
 255                                         /* MAC address offset in I2C EEPROM */
 256 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 257
 258 #define CONFIG_NETDEV           "eth1"
 259
 260 #define CONFIG_HOSTNAME         "mpc8323erdb"
 261 #define CONFIG_ROOTPATH         "/nfsroot"
 262 #define CONFIG_BOOTFILE         "uImage"
 263                                 /* U-Boot image on TFTP server */
 264 #define CONFIG_UBOOTPATH        "u-boot.bin"
 265 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 266 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 267
 268                                 /* default location for tftp and bootm */
 269 #define CONFIG_LOADADDR         800000
 270
 271 #define CONFIG_EXTRA_ENV_SETTINGS \
 272         "netdev=" CONFIG_NETDEV "\0"                                    \
 273         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 274         "tftpflash=tftp $loadaddr $uboot;"                              \
 275                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 276                         " +$filesize; " \
 277                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 278                         " +$filesize; " \
 279                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 280                         " $filesize; "  \
 281                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 282                         " +$filesize; " \
 283                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 284                         " $filesize\0"  \
 285         "fdtaddr=780000\0"                                              \
 286         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 287         "ramdiskaddr=1000000\0"                                         \
 288         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 289         "console=ttyS0\0"                                               \
 290         "setbootargs=setenv bootargs "                                  \
 291                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 292         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 293                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 294                                                                 "$netdev:off "\
 295                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 296
 297 #define CONFIG_NFSBOOTCOMMAND                                           \
 298         "setenv rootdev /dev/nfs;"                                      \
 299         "run setbootargs;"                                              \
 300         "run setipargs;"                                                \
 301         "tftp $loadaddr $bootfile;"                                     \
 302         "tftp $fdtaddr $fdtfile;"                                       \
 303         "bootm $loadaddr - $fdtaddr"
 304
 305 #define CONFIG_RAMBOOTCOMMAND                                           \
 306         "setenv rootdev /dev/ram;"                                      \
 307         "run setbootargs;"                                              \
 308         "tftp $ramdiskaddr $ramdiskfile;"                               \
 309         "tftp $loadaddr $bootfile;"                                     \
 310         "tftp $fdtaddr $fdtfile;"                                       \
 311         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 312
 313 #endif  /* __CONFIG_H */