include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /*
  24  * System performance
  25  */
  26 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  27 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  28 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  29 #define CONFIG_SYS_SPCR_OPT     1
  30
  31 /*
  32  * DDR Setup
  33  */
  34 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  35 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  36 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  37
  38 #undef CONFIG_SPD_EEPROM
  39 #if defined(CONFIG_SPD_EEPROM)
  40 /* Determine DDR configuration from I2C interface
  41  */
  42 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  43 #else
  44 /* Manually set up DDR parameters
  45  */
  46 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  47 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  48                                 | CSCONFIG_ROW_BIT_13 \
  49                                 | CSCONFIG_COL_BIT_9)
  50                                 /* 0x80010101 */
  51 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  52                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  53                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  54                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  55                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  56                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  57                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  58                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  59                                 /* 0x00220802 */
  60 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  61                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  62                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  63                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  64                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  65                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  66                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  67                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  68                                 /* 0x26253222 */
  69 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  70                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  71                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  72                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  73                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  74                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  75                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  76                                 /* 0x1f9048c7 */
  77 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  78 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  79                                 /* 0x02000000 */
  80 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  81                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  82                                 /* 0x44480232 */
  83 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  84 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  85                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  86                                 /* 0x03200064 */
  87 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  88 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  89                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  90                                 | SDRAM_CFG_32_BE)
  91                                 /* 0x43080000 */
  92 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  93 #endif
  94
  95 /*
  96  * Memory test
  97  */
  98 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  99 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 100 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 101
 102 /*
 103  * The reserved memory
 104  */
 105 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 106
 107 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 108 #define CONFIG_SYS_RAMBOOT
 109 #else
 110 #undef  CONFIG_SYS_RAMBOOT
 111 #endif
 112
 113 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 114 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 115 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 116
 117 /*
 118  * Initial RAM Base Address Setup
 119  */
 120 #define CONFIG_SYS_INIT_RAM_LOCK        1
 121 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 122 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 123 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 124                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 125
 126 /*
 127  * Local Bus Configuration & Clock Setup
 128  */
 129 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 130 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 131 #define CONFIG_SYS_LBC_LBCR             0x00000000
 132
 133 /*
 134  * FLASH on the Local Bus
 135  */
 136 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 137 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 138
 139
 140
 141 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 142 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 143
 144 #undef CONFIG_SYS_FLASH_CHECKSUM
 145
 146 /*
 147  * Serial Port
 148  */
 149 #define CONFIG_SYS_NS16550_SERIAL
 150 #define CONFIG_SYS_NS16550_REG_SIZE     1
 151 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 152
 153 #define CONFIG_SYS_BAUDRATE_TABLE  \
 154                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 155
 156 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 157 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 158
 159 /* I2C */
 160 #define CONFIG_SYS_I2C
 161 #define CONFIG_SYS_I2C_FSL
 162 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 163 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 164 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 165 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 166
 167 /*
 168  * Config on-board EEPROM
 169  */
 170 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 172 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 173 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 174
 175 /*
 176  * General PCI
 177  * Addresses are mapped 1-1.
 178  */
 179 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 180 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 181 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 182 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 183 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 184 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 185 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 186 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 187 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 188
 189 #ifdef CONFIG_PCI
 190 #define CONFIG_PCI_INDIRECT_BRIDGE
 191 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 192
 193 #undef CONFIG_EEPRO100
 194 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 195 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 196
 197 #endif  /* CONFIG_PCI */
 198
 199 /*
 200  * QE UEC ethernet configuration
 201  */
 202 #define CONFIG_UEC_ETH
 203 #define CONFIG_ETHPRIME         "UEC0"
 204
 205 #define CONFIG_UEC_ETH1         /* ETH3 */
 206
 207 #ifdef CONFIG_UEC_ETH1
 208 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 209 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 210 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 211 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 212 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 213 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 214 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 215 #endif
 216
 217 #define CONFIG_UEC_ETH2         /* ETH4 */
 218
 219 #ifdef CONFIG_UEC_ETH2
 220 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 221 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 222 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 223 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 224 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 225 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 226 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 227 #endif
 228
 229 /*
 230  * Environment
 231  */
 232 #ifndef CONFIG_SYS_RAMBOOT
 233         #define CONFIG_ENV_ADDR         \
 234                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 235         #define CONFIG_ENV_SECT_SIZE    0x20000
 236         #define CONFIG_ENV_SIZE         0x2000
 237 #else
 238         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 239         #define CONFIG_ENV_SIZE         0x2000
 240 #endif
 241
 242 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 243 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 244
 245 /*
 246  * BOOTP options
 247  */
 248 #define CONFIG_BOOTP_BOOTFILESIZE
 249
 250 /*
 251  * Command line configuration.
 252  */
 253
 254 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 255
 256 /*
 257  * Miscellaneous configurable options
 258  */
 259 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 260
 261 /*
 262  * For booting Linux, the board info and command line data
 263  * have to be in the first 256 MB of memory, since this is
 264  * the maximum mapped by the Linux kernel during initialization.
 265  */
 266                                         /* Initial Memory map for Linux */
 267 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 268 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 269
 270 #if (CONFIG_CMD_KGDB)
 271 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 272 #endif
 273
 274 /*
 275  * Environment Configuration
 276  */
 277 #define CONFIG_ENV_OVERWRITE
 278
 279 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 280 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 281
 282 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 283  * (see CONFIG_SYS_I2C_EEPROM) */
 284                                         /* MAC address offset in I2C EEPROM */
 285 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 286
 287 #define CONFIG_NETDEV           "eth1"
 288
 289 #define CONFIG_HOSTNAME         "mpc8323erdb"
 290 #define CONFIG_ROOTPATH         "/nfsroot"
 291 #define CONFIG_BOOTFILE         "uImage"
 292                                 /* U-Boot image on TFTP server */
 293 #define CONFIG_UBOOTPATH        "u-boot.bin"
 294 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 295 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 296
 297                                 /* default location for tftp and bootm */
 298 #define CONFIG_LOADADDR         800000
 299
 300 #define CONFIG_EXTRA_ENV_SETTINGS \
 301         "netdev=" CONFIG_NETDEV "\0"                                    \
 302         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 303         "tftpflash=tftp $loadaddr $uboot;"                              \
 304                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 305                         " +$filesize; " \
 306                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 307                         " +$filesize; " \
 308                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 309                         " $filesize; "  \
 310                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 311                         " +$filesize; " \
 312                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 313                         " $filesize\0"  \
 314         "fdtaddr=780000\0"                                              \
 315         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 316         "ramdiskaddr=1000000\0"                                         \
 317         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 318         "console=ttyS0\0"                                               \
 319         "setbootargs=setenv bootargs "                                  \
 320                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 321         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 322                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 323                                                                 "$netdev:off "\
 324                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 325
 326 #define CONFIG_NFSBOOTCOMMAND                                           \
 327         "setenv rootdev /dev/nfs;"                                      \
 328         "run setbootargs;"                                              \
 329         "run setipargs;"                                                \
 330         "tftp $loadaddr $bootfile;"                                     \
 331         "tftp $fdtaddr $fdtfile;"                                       \
 332         "bootm $loadaddr - $fdtaddr"
 333
 334 #define CONFIG_RAMBOOTCOMMAND                                           \
 335         "setenv rootdev /dev/ram;"                                      \
 336         "run setbootargs;"                                              \
 337         "tftp $ramdiskaddr $ramdiskfile;"                               \
 338         "tftp $loadaddr $bootfile;"                                     \
 339         "tftp $fdtaddr $fdtfile;"                                       \
 340         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 341
 342 #endif  /* __CONFIG_H */