2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
21 #define CONFIG_SYS_SICRL 0x00000000
26 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
28 #undef CONFIG_SPD_EEPROM
29 #if defined(CONFIG_SPD_EEPROM)
30 /* Determine DDR configuration from I2C interface
32 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
34 /* Manually set up DDR parameters
36 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
37 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
38 | CSCONFIG_ROW_BIT_13 \
41 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
42 | (0 << TIMING_CFG0_WRT_SHIFT) \
43 | (0 << TIMING_CFG0_RRT_SHIFT) \
44 | (0 << TIMING_CFG0_WWT_SHIFT) \
45 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
46 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
47 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
48 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
50 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
51 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
52 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
53 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
54 | (3 << TIMING_CFG1_REFREC_SHIFT) \
55 | (2 << TIMING_CFG1_WRREC_SHIFT) \
56 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
57 | (2 << TIMING_CFG1_WRTORD_SHIFT))
59 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
60 | (31 << TIMING_CFG2_CPO_SHIFT) \
61 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
62 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
63 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
64 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
65 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
67 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
68 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
70 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
71 | (0x0232 << SDRAM_MODE_SD_SHIFT))
73 #define CONFIG_SYS_DDR_MODE2 0x8000c000
74 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
75 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
77 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
78 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
79 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
82 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
88 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
89 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
90 #define CONFIG_SYS_MEMTEST_END 0x03f00000
95 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
97 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
98 #define CONFIG_SYS_RAMBOOT
100 #undef CONFIG_SYS_RAMBOOT
103 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
104 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
105 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
108 * Initial RAM Base Address Setup
110 #define CONFIG_SYS_INIT_RAM_LOCK 1
111 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
112 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
113 #define CONFIG_SYS_GBL_DATA_OFFSET \
114 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
117 * FLASH on the Local Bus
119 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
120 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
125 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
127 #undef CONFIG_SYS_FLASH_CHECKSUM
132 #define CONFIG_SYS_NS16550_SERIAL
133 #define CONFIG_SYS_NS16550_REG_SIZE 1
134 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
136 #define CONFIG_SYS_BAUDRATE_TABLE \
137 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
139 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
140 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
143 #define CONFIG_SYS_I2C
144 #define CONFIG_SYS_I2C_FSL
145 #define CONFIG_SYS_FSL_I2C_SPEED 400000
146 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
147 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
148 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
151 * Config on-board EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
156 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
160 * Addresses are mapped 1-1.
162 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
163 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
164 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
165 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
166 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
167 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
168 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
169 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
170 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
173 #define CONFIG_PCI_INDIRECT_BRIDGE
174 #define CONFIG_PCI_SKIP_HOST_BRIDGE
176 #undef CONFIG_EEPRO100
177 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
178 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
180 #endif /* CONFIG_PCI */
183 * QE UEC ethernet configuration
185 #define CONFIG_UEC_ETH
186 #define CONFIG_ETHPRIME "UEC0"
188 #define CONFIG_UEC_ETH1 /* ETH3 */
190 #ifdef CONFIG_UEC_ETH1
191 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
192 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
193 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
194 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
195 #define CONFIG_SYS_UEC1_PHY_ADDR 4
196 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
197 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
200 #define CONFIG_UEC_ETH2 /* ETH4 */
202 #ifdef CONFIG_UEC_ETH2
203 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
204 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
205 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
206 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
207 #define CONFIG_SYS_UEC2_PHY_ADDR 0
208 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
209 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
215 #ifndef CONFIG_SYS_RAMBOOT
216 #define CONFIG_ENV_ADDR \
217 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
218 #define CONFIG_ENV_SECT_SIZE 0x20000
219 #define CONFIG_ENV_SIZE 0x2000
221 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
222 #define CONFIG_ENV_SIZE 0x2000
225 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
226 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
231 #define CONFIG_BOOTP_BOOTFILESIZE
234 * Command line configuration.
237 #undef CONFIG_WATCHDOG /* watchdog disabled */
240 * Miscellaneous configurable options
242 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
245 * For booting Linux, the board info and command line data
246 * have to be in the first 256 MB of memory, since this is
247 * the maximum mapped by the Linux kernel during initialization.
249 /* Initial Memory map for Linux */
250 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
251 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
253 #if (CONFIG_CMD_KGDB)
254 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
258 * Environment Configuration
260 #define CONFIG_ENV_OVERWRITE
262 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
263 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
265 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
266 * (see CONFIG_SYS_I2C_EEPROM) */
267 /* MAC address offset in I2C EEPROM */
268 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
270 #define CONFIG_NETDEV "eth1"
272 #define CONFIG_HOSTNAME "mpc8323erdb"
273 #define CONFIG_ROOTPATH "/nfsroot"
274 #define CONFIG_BOOTFILE "uImage"
275 /* U-Boot image on TFTP server */
276 #define CONFIG_UBOOTPATH "u-boot.bin"
277 #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
278 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
280 /* default location for tftp and bootm */
281 #define CONFIG_LOADADDR 800000
283 #define CONFIG_EXTRA_ENV_SETTINGS \
284 "netdev=" CONFIG_NETDEV "\0" \
285 "uboot=" CONFIG_UBOOTPATH "\0" \
286 "tftpflash=tftp $loadaddr $uboot;" \
287 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
289 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
291 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
293 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
295 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
298 "fdtfile=" CONFIG_FDTFILE "\0" \
299 "ramdiskaddr=1000000\0" \
300 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
302 "setbootargs=setenv bootargs " \
303 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
304 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
305 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
307 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
309 #define CONFIG_NFSBOOTCOMMAND \
310 "setenv rootdev /dev/nfs;" \
313 "tftp $loadaddr $bootfile;" \
314 "tftp $fdtaddr $fdtfile;" \
315 "bootm $loadaddr - $fdtaddr"
317 #define CONFIG_RAMBOOTCOMMAND \
318 "setenv rootdev /dev/ram;" \
320 "tftp $ramdiskaddr $ramdiskfile;" \
321 "tftp $loadaddr $bootfile;" \
322 "tftp $fdtaddr $fdtfile;" \
323 "bootm $loadaddr $ramdiskaddr $fdtaddr"
325 #endif /* __CONFIG_H */