2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
13 * High Level Configuration Options
15 #define CONFIG_E300 1 /* E300 family */
16 #define CONFIG_QE 1 /* Has QE */
21 #define CONFIG_SYS_SICRL 0x00000000
26 #define CONFIG_SYS_IMMR 0xE0000000
31 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
32 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
33 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
34 #define CONFIG_SYS_SPCR_OPT 1
39 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
41 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
43 #undef CONFIG_SPD_EEPROM
44 #if defined(CONFIG_SPD_EEPROM)
45 /* Determine DDR configuration from I2C interface
47 #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
49 /* Manually set up DDR parameters
51 #define CONFIG_SYS_DDR_SIZE 64 /* MB */
52 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
53 | CSCONFIG_ROW_BIT_13 \
56 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
57 | (0 << TIMING_CFG0_WRT_SHIFT) \
58 | (0 << TIMING_CFG0_RRT_SHIFT) \
59 | (0 << TIMING_CFG0_WWT_SHIFT) \
60 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
61 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
62 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
63 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
65 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
66 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
67 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
68 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
69 | (3 << TIMING_CFG1_REFREC_SHIFT) \
70 | (2 << TIMING_CFG1_WRREC_SHIFT) \
71 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
72 | (2 << TIMING_CFG1_WRTORD_SHIFT))
74 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
75 | (31 << TIMING_CFG2_CPO_SHIFT) \
76 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
77 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
78 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
79 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
80 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
83 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
85 #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
86 | (0x0232 << SDRAM_MODE_SD_SHIFT))
88 #define CONFIG_SYS_DDR_MODE2 0x8000c000
89 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
90 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
92 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
93 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
94 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
97 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
103 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
104 #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
105 #define CONFIG_SYS_MEMTEST_END 0x03f00000
108 * The reserved memory
110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
113 #define CONFIG_SYS_RAMBOOT
115 #undef CONFIG_SYS_RAMBOOT
118 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
119 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
120 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
123 * Initial RAM Base Address Setup
125 #define CONFIG_SYS_INIT_RAM_LOCK 1
126 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
127 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
128 #define CONFIG_SYS_GBL_DATA_OFFSET \
129 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
132 * Local Bus Configuration & Clock Setup
134 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
135 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
136 #define CONFIG_SYS_LBC_LBCR 0x00000000
139 * FLASH on the Local Bus
141 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
142 #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
144 /* Window base at flash base */
145 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
146 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
148 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
149 | BR_PS_16 /* 16 bit port */ \
150 | BR_MS_GPCM /* MSEL = GPCM */ \
152 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
166 #undef CONFIG_SYS_FLASH_CHECKSUM
171 #define CONFIG_SYS_NS16550_SERIAL
172 #define CONFIG_SYS_NS16550_REG_SIZE 1
173 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
175 #define CONFIG_SYS_BAUDRATE_TABLE \
176 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
182 #define CONFIG_SYS_I2C
183 #define CONFIG_SYS_I2C_FSL
184 #define CONFIG_SYS_FSL_I2C_SPEED 400000
185 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
186 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
187 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
190 * Config on-board EEPROM
192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
199 * Addresses are mapped 1-1.
201 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
202 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
203 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
204 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
205 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
206 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
207 #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
208 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
209 #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
212 #define CONFIG_PCI_INDIRECT_BRIDGE
213 #define CONFIG_PCI_SKIP_HOST_BRIDGE
215 #undef CONFIG_EEPRO100
216 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
217 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
219 #endif /* CONFIG_PCI */
222 * QE UEC ethernet configuration
224 #define CONFIG_UEC_ETH
225 #define CONFIG_ETHPRIME "UEC0"
227 #define CONFIG_UEC_ETH1 /* ETH3 */
229 #ifdef CONFIG_UEC_ETH1
230 #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
231 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
232 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
233 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
234 #define CONFIG_SYS_UEC1_PHY_ADDR 4
235 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
236 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
239 #define CONFIG_UEC_ETH2 /* ETH4 */
241 #ifdef CONFIG_UEC_ETH2
242 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
243 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
244 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
245 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
246 #define CONFIG_SYS_UEC2_PHY_ADDR 0
247 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
248 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
254 #ifndef CONFIG_SYS_RAMBOOT
255 #define CONFIG_ENV_ADDR \
256 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
257 #define CONFIG_ENV_SECT_SIZE 0x20000
258 #define CONFIG_ENV_SIZE 0x2000
260 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
261 #define CONFIG_ENV_SIZE 0x2000
264 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
265 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
270 #define CONFIG_BOOTP_BOOTFILESIZE
273 * Command line configuration.
276 #undef CONFIG_WATCHDOG /* watchdog disabled */
279 * Miscellaneous configurable options
281 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
284 * For booting Linux, the board info and command line data
285 * have to be in the first 256 MB of memory, since this is
286 * the maximum mapped by the Linux kernel during initialization.
288 /* Initial Memory map for Linux */
289 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
290 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
295 #define CONFIG_SYS_HID0_INIT 0x000000000
296 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
297 HID0_ENABLE_INSTRUCTION_CACHE)
298 #define CONFIG_SYS_HID2 HID2_HBE
304 /* DDR: cache cacheable */
305 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
308 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
312 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
313 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
315 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
316 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
318 | BATL_CACHEINHIBIT \
319 | BATL_GUARDEDSTORAGE)
320 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
324 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
325 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
327 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
328 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
331 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
335 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
337 | BATL_CACHEINHIBIT \
338 | BATL_GUARDEDSTORAGE)
339 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
341 #define CONFIG_SYS_IBAT3L (0)
342 #define CONFIG_SYS_IBAT3U (0)
343 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
344 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
346 /* Stack in dcache: cacheable, no memory coherence */
347 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
348 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
352 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
353 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
356 /* PCI MEM space: cacheable */
357 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
360 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
364 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
365 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
366 /* PCI MMIO space: cache-inhibit and guarded */
367 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
369 | BATL_CACHEINHIBIT \
370 | BATL_GUARDEDSTORAGE)
371 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
375 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
376 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
378 #define CONFIG_SYS_IBAT5L (0)
379 #define CONFIG_SYS_IBAT5U (0)
380 #define CONFIG_SYS_IBAT6L (0)
381 #define CONFIG_SYS_IBAT6U (0)
382 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
383 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
384 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
385 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
388 /* Nothing in BAT7 */
389 #define CONFIG_SYS_IBAT7L (0)
390 #define CONFIG_SYS_IBAT7U (0)
391 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
392 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
394 #if (CONFIG_CMD_KGDB)
395 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
399 * Environment Configuration
401 #define CONFIG_ENV_OVERWRITE
403 #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
404 #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
406 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
407 * (see CONFIG_SYS_I2C_EEPROM) */
408 /* MAC address offset in I2C EEPROM */
409 #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
411 #define CONFIG_NETDEV "eth1"
413 #define CONFIG_HOSTNAME "mpc8323erdb"
414 #define CONFIG_ROOTPATH "/nfsroot"
415 #define CONFIG_BOOTFILE "uImage"
416 /* U-Boot image on TFTP server */
417 #define CONFIG_UBOOTPATH "u-boot.bin"
418 #define CONFIG_FDTFILE "mpc832x_rdb.dtb"
419 #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
421 /* default location for tftp and bootm */
422 #define CONFIG_LOADADDR 800000
424 #define CONFIG_EXTRA_ENV_SETTINGS \
425 "netdev=" CONFIG_NETDEV "\0" \
426 "uboot=" CONFIG_UBOOTPATH "\0" \
427 "tftpflash=tftp $loadaddr $uboot;" \
428 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
430 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
432 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
434 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
436 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
439 "fdtfile=" CONFIG_FDTFILE "\0" \
440 "ramdiskaddr=1000000\0" \
441 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
443 "setbootargs=setenv bootargs " \
444 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
445 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
446 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
448 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
450 #define CONFIG_NFSBOOTCOMMAND \
451 "setenv rootdev /dev/nfs;" \
454 "tftp $loadaddr $bootfile;" \
455 "tftp $fdtaddr $fdtfile;" \
456 "bootm $loadaddr - $fdtaddr"
458 #define CONFIG_RAMBOOTCOMMAND \
459 "setenv rootdev /dev/ram;" \
461 "tftp $ramdiskaddr $ramdiskfile;" \
462 "tftp $loadaddr $bootfile;" \
463 "tftp $fdtaddr $fdtfile;" \
464 "bootm $loadaddr $ramdiskaddr $fdtaddr"
466 #endif /* __CONFIG_H */