include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_SYS_GENERIC_BOARD
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 family */
  19 #define CONFIG_QE               1       /* Has QE */
  20 #define CONFIG_MPC832x          1       /* MPC832x CPU specific */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  23
  24 #define CONFIG_PCI              1
  25
  26 /*
  27  * System Clock Setup
  28  */
  29 #define CONFIG_83XX_CLKIN       66666667        /* in Hz */
  30
  31 #ifndef CONFIG_SYS_CLK_FREQ
  32 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  33 #endif
  34
  35 /*
  36  * Hardware Reset Configuration Word
  37  */
  38 #define CONFIG_SYS_HRCW_LOW (\
  39         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  40         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  41         HRCWL_VCO_1X2 |\
  42         HRCWL_CSB_TO_CLKIN_2X1 |\
  43         HRCWL_CORE_TO_CSB_2_5X1 |\
  44         HRCWL_CE_PLL_VCO_DIV_2 |\
  45         HRCWL_CE_PLL_DIV_1X1 |\
  46         HRCWL_CE_TO_PLL_1X3)
  47
  48 #define CONFIG_SYS_HRCW_HIGH (\
  49         HRCWH_PCI_HOST |\
  50         HRCWH_PCI1_ARBITER_ENABLE |\
  51         HRCWH_CORE_ENABLE |\
  52         HRCWH_FROM_0X00000100 |\
  53         HRCWH_BOOTSEQ_DISABLE |\
  54         HRCWH_SW_WATCHDOG_DISABLE |\
  55         HRCWH_ROM_LOC_LOCAL_16BIT |\
  56         HRCWH_BIG_ENDIAN |\
  57         HRCWH_LALE_NORMAL)
  58
  59 /*
  60  * System IO Config
  61  */
  62 #define CONFIG_SYS_SICRL                0x00000000
  63
  64 /*
  65  * IMMR new address
  66  */
  67 #define CONFIG_SYS_IMMR         0xE0000000
  68
  69 /*
  70  * System performance
  71  */
  72 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  73 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  74 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  75 #define CONFIG_SYS_SPCR_OPT     1
  76
  77 /*
  78  * DDR Setup
  79  */
  80 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  81 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  83
  84 #undef CONFIG_SPD_EEPROM
  85 #if defined(CONFIG_SPD_EEPROM)
  86 /* Determine DDR configuration from I2C interface
  87  */
  88 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  89 #else
  90 /* Manually set up DDR parameters
  91  */
  92 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  93 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  94                                 | CSCONFIG_ROW_BIT_13 \
  95                                 | CSCONFIG_COL_BIT_9)
  96                                 /* 0x80010101 */
  97 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  98                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  99                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 100                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 101                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 102                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 103                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 104                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 105                                 /* 0x00220802 */
 106 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 107                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 108                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 109                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 110                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
 111                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 112                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 113                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 114                                 /* 0x26253222 */
 115 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 116                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
 117                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 118                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 119                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 120                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 121                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
 122                                 /* 0x1f9048c7 */
 123 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 124 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 125                                 /* 0x02000000 */
 126 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
 127                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 128                                 /* 0x44480232 */
 129 #define CONFIG_SYS_DDR_MODE2    0x8000c000
 130 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
 131                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 132                                 /* 0x03200064 */
 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
 134 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 135                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 136                                 | SDRAM_CFG_32_BE)
 137                                 /* 0x43080000 */
 138 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 139 #endif
 140
 141 /*
 142  * Memory test
 143  */
 144 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 145 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 146 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 147
 148 /*
 149  * The reserved memory
 150  */
 151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 152
 153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 154 #define CONFIG_SYS_RAMBOOT
 155 #else
 156 #undef  CONFIG_SYS_RAMBOOT
 157 #endif
 158
 159 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 160 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)    /* Reserve 384 kB for Mon */
 161 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 162
 163 /*
 164  * Initial RAM Base Address Setup
 165  */
 166 #define CONFIG_SYS_INIT_RAM_LOCK        1
 167 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 168 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 170                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171
 172 /*
 173  * Local Bus Configuration & Clock Setup
 174  */
 175 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 176 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 177 #define CONFIG_SYS_LBC_LBCR             0x00000000
 178
 179 /*
 180  * FLASH on the Local Bus
 181  */
 182 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 183 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 184 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 185 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 186 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 187
 188                                         /* Window base at flash base */
 189 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 190 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 191
 192 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 193                                 | BR_PS_16      /* 16 bit port */ \
 194                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 195                                 | BR_V)         /* valid */
 196 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 197                                 | OR_GPCM_XAM \
 198                                 | OR_GPCM_CSNT \
 199                                 | OR_GPCM_ACS_DIV2 \
 200                                 | OR_GPCM_XACS \
 201                                 | OR_GPCM_SCY_15 \
 202                                 | OR_GPCM_TRLX_SET \
 203                                 | OR_GPCM_EHTR_SET \
 204                                 | OR_GPCM_EAD)
 205                                 /* 0xFE006FF7 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 209
 210 #undef CONFIG_SYS_FLASH_CHECKSUM
 211
 212 /*
 213  * Serial Port
 214  */
 215 #define CONFIG_CONS_INDEX       1
 216 #define CONFIG_SYS_NS16550
 217 #define CONFIG_SYS_NS16550_SERIAL
 218 #define CONFIG_SYS_NS16550_REG_SIZE     1
 219 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 220
 221 #define CONFIG_SYS_BAUDRATE_TABLE  \
 222                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 223
 224 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 225 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 226
 227 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 228 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 229 /* Use the HUSH parser */
 230 #define CONFIG_SYS_HUSH_PARSER
 231
 232 /* pass open firmware flat tree */
 233 #define CONFIG_OF_LIBFDT        1
 234 #define CONFIG_OF_BOARD_SETUP   1
 235 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 236
 237 /* I2C */
 238 #define CONFIG_SYS_I2C
 239 #define CONFIG_SYS_I2C_FSL
 240 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 241 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 242 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 243 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 244
 245 /*
 246  * Config on-board EEPROM
 247  */
 248 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 250 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 251 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 252
 253 /*
 254  * General PCI
 255  * Addresses are mapped 1-1.
 256  */
 257 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 258 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 259 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 260 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 261 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 262 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 263 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 264 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 265 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 266
 267 #ifdef CONFIG_PCI
 268 #define CONFIG_PCI_INDIRECT_BRIDGE
 269 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 270 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 271
 272 #undef CONFIG_EEPRO100
 273 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 274 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 275
 276 #endif  /* CONFIG_PCI */
 277
 278 /*
 279  * QE UEC ethernet configuration
 280  */
 281 #define CONFIG_UEC_ETH
 282 #define CONFIG_ETHPRIME         "UEC0"
 283
 284 #define CONFIG_UEC_ETH1         /* ETH3 */
 285
 286 #ifdef CONFIG_UEC_ETH1
 287 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 288 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 289 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 290 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 291 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 292 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 293 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 294 #endif
 295
 296 #define CONFIG_UEC_ETH2         /* ETH4 */
 297
 298 #ifdef CONFIG_UEC_ETH2
 299 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 300 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 301 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 302 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 303 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 304 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 305 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 306 #endif
 307
 308 /*
 309  * Environment
 310  */
 311 #ifndef CONFIG_SYS_RAMBOOT
 312         #define CONFIG_ENV_IS_IN_FLASH  1
 313         #define CONFIG_ENV_ADDR         \
 314                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 315         #define CONFIG_ENV_SECT_SIZE    0x20000
 316         #define CONFIG_ENV_SIZE         0x2000
 317 #else
 318         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 319         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 320         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 321         #define CONFIG_ENV_SIZE         0x2000
 322 #endif
 323
 324 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 325 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 326
 327 /*
 328  * BOOTP options
 329  */
 330 #define CONFIG_BOOTP_BOOTFILESIZE
 331 #define CONFIG_BOOTP_BOOTPATH
 332 #define CONFIG_BOOTP_GATEWAY
 333 #define CONFIG_BOOTP_HOSTNAME
 334
 335 /*
 336  * Command line configuration.
 337  */
 338 #include <config_cmd_default.h>
 339
 340 #define CONFIG_CMD_PING
 341 #define CONFIG_CMD_I2C
 342 #define CONFIG_CMD_EEPROM
 343 #define CONFIG_CMD_ASKENV
 344
 345 #if defined(CONFIG_PCI)
 346         #define CONFIG_CMD_PCI
 347 #endif
 348 #if defined(CONFIG_SYS_RAMBOOT)
 349         #undef CONFIG_CMD_SAVEENV
 350         #undef CONFIG_CMD_LOADS
 351 #endif
 352
 353 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 359 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 360
 361 #if (CONFIG_CMD_KGDB)
 362         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 363 #else
 364         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 365 #endif
 366
 367                                 /* Print Buffer Size */
 368 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 369 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 370                                 /* Boot Argument Buffer Size */
 371 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 372
 373 /*
 374  * For booting Linux, the board info and command line data
 375  * have to be in the first 256 MB of memory, since this is
 376  * the maximum mapped by the Linux kernel during initialization.
 377  */
 378                                         /* Initial Memory map for Linux */
 379 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 380
 381 /*
 382  * Core HID Setup
 383  */
 384 #define CONFIG_SYS_HID0_INIT    0x000000000
 385 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 386                                  HID0_ENABLE_INSTRUCTION_CACHE)
 387 #define CONFIG_SYS_HID2         HID2_HBE
 388
 389 /*
 390  * MMU Setup
 391  */
 392 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 393
 394 /* DDR: cache cacheable */
 395 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 396                                 | BATL_PP_RW \
 397                                 | BATL_MEMCOHERENCE)
 398 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 399                                 | BATU_BL_256M \
 400                                 | BATU_VS \
 401                                 | BATU_VP)
 402 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 403 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 404
 405 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 406 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 407                                 | BATL_PP_RW \
 408                                 | BATL_CACHEINHIBIT \
 409                                 | BATL_GUARDEDSTORAGE)
 410 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 411                                 | BATU_BL_4M \
 412                                 | BATU_VS \
 413                                 | BATU_VP)
 414 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 415 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 416
 417 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 418 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 419                                 | BATL_PP_RW \
 420                                 | BATL_MEMCOHERENCE)
 421 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 422                                 | BATU_BL_32M \
 423                                 | BATU_VS \
 424                                 | BATU_VP)
 425 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 426                                 | BATL_PP_RW \
 427                                 | BATL_CACHEINHIBIT \
 428                                 | BATL_GUARDEDSTORAGE)
 429 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 430
 431 #define CONFIG_SYS_IBAT3L       (0)
 432 #define CONFIG_SYS_IBAT3U       (0)
 433 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 434 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 435
 436 /* Stack in dcache: cacheable, no memory coherence */
 437 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 438 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 439                                 | BATU_BL_128K \
 440                                 | BATU_VS \
 441                                 | BATU_VP)
 442 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 443 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 444
 445 #ifdef CONFIG_PCI
 446 /* PCI MEM space: cacheable */
 447 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 448                                 | BATL_PP_RW \
 449                                 | BATL_MEMCOHERENCE)
 450 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 451                                 | BATU_BL_256M \
 452                                 | BATU_VS \
 453                                 | BATU_VP)
 454 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 455 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 456 /* PCI MMIO space: cache-inhibit and guarded */
 457 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 458                                 | BATL_PP_RW \
 459                                 | BATL_CACHEINHIBIT \
 460                                 | BATL_GUARDEDSTORAGE)
 461 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 462                                 | BATU_BL_256M \
 463                                 | BATU_VS \
 464                                 | BATU_VP)
 465 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 466 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 467 #else
 468 #define CONFIG_SYS_IBAT5L       (0)
 469 #define CONFIG_SYS_IBAT5U       (0)
 470 #define CONFIG_SYS_IBAT6L       (0)
 471 #define CONFIG_SYS_IBAT6U       (0)
 472 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 473 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 474 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 475 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 476 #endif
 477
 478 /* Nothing in BAT7 */
 479 #define CONFIG_SYS_IBAT7L       (0)
 480 #define CONFIG_SYS_IBAT7U       (0)
 481 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 482 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 483
 484 #if (CONFIG_CMD_KGDB)
 485 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 486 #endif
 487
 488 /*
 489  * Environment Configuration
 490  */
 491 #define CONFIG_ENV_OVERWRITE
 492
 493 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 494 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 495
 496 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 497  * (see CONFIG_SYS_I2C_EEPROM) */
 498                                         /* MAC address offset in I2C EEPROM */
 499 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 500
 501 #define CONFIG_NETDEV           "eth1"
 502
 503 #define CONFIG_HOSTNAME         mpc8323erdb
 504 #define CONFIG_ROOTPATH         "/nfsroot"
 505 #define CONFIG_BOOTFILE         "uImage"
 506                                 /* U-Boot image on TFTP server */
 507 #define CONFIG_UBOOTPATH        "u-boot.bin"
 508 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 509 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 510
 511                                 /* default location for tftp and bootm */
 512 #define CONFIG_LOADADDR         800000
 513 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 514 #define CONFIG_BAUDRATE         115200
 515
 516 #define CONFIG_EXTRA_ENV_SETTINGS \
 517         "netdev=" CONFIG_NETDEV "\0"                                    \
 518         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 519         "tftpflash=tftp $loadaddr $uboot;"                              \
 520                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 521                         " +$filesize; " \
 522                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 523                         " +$filesize; " \
 524                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 525                         " $filesize; "  \
 526                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 527                         " +$filesize; " \
 528                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 529                         " $filesize\0"  \
 530         "fdtaddr=780000\0"                                              \
 531         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 532         "ramdiskaddr=1000000\0"                                         \
 533         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 534         "console=ttyS0\0"                                               \
 535         "setbootargs=setenv bootargs "                                  \
 536                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 537         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 538                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 539                                                                 "$netdev:off "\
 540                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 541
 542 #define CONFIG_NFSBOOTCOMMAND                                           \
 543         "setenv rootdev /dev/nfs;"                                      \
 544         "run setbootargs;"                                              \
 545         "run setipargs;"                                                \
 546         "tftp $loadaddr $bootfile;"                                     \
 547         "tftp $fdtaddr $fdtfile;"                                       \
 548         "bootm $loadaddr - $fdtaddr"
 549
 550 #define CONFIG_RAMBOOTCOMMAND                                           \
 551         "setenv rootdev /dev/ram;"                                      \
 552         "run setbootargs;"                                              \
 553         "tftp $ramdiskaddr $ramdiskfile;"                               \
 554         "tftp $loadaddr $bootfile;"                                     \
 555         "tftp $fdtaddr $fdtfile;"                                       \
 556         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 557
 558 #endif  /* __CONFIG_H */