include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  24 #define CONFIG_SYS_SPCR_OPT     1
  25
  26 /*
  27  * DDR Setup
  28  */
  29 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  30 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  31 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  32
  33 #undef CONFIG_SPD_EEPROM
  34 #if defined(CONFIG_SPD_EEPROM)
  35 /* Determine DDR configuration from I2C interface
  36  */
  37 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  38 #else
  39 /* Manually set up DDR parameters
  40  */
  41 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  42 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  43                                 | CSCONFIG_ROW_BIT_13 \
  44                                 | CSCONFIG_COL_BIT_9)
  45                                 /* 0x80010101 */
  46 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  47                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  48                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  49                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  50                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  51                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  52                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  53                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  54                                 /* 0x00220802 */
  55 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  56                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  57                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  58                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  59                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  60                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  61                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  62                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  63                                 /* 0x26253222 */
  64 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  65                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  66                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  67                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  68                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  69                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  70                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  71                                 /* 0x1f9048c7 */
  72 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  73 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  74                                 /* 0x02000000 */
  75 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  76                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  77                                 /* 0x44480232 */
  78 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  79 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  80                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  81                                 /* 0x03200064 */
  82 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  83 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  84                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  85                                 | SDRAM_CFG_32_BE)
  86                                 /* 0x43080000 */
  87 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  88 #endif
  89
  90 /*
  91  * Memory test
  92  */
  93 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  94 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
  95 #define CONFIG_SYS_MEMTEST_END          0x03f00000
  96
  97 /*
  98  * The reserved memory
  99  */
 100 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 101
 102 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 103 #define CONFIG_SYS_RAMBOOT
 104 #else
 105 #undef  CONFIG_SYS_RAMBOOT
 106 #endif
 107
 108 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 109 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 110 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 111
 112 /*
 113  * Initial RAM Base Address Setup
 114  */
 115 #define CONFIG_SYS_INIT_RAM_LOCK        1
 116 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 117 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 119                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 120
 121 /*
 122  * Local Bus Configuration & Clock Setup
 123  */
 124 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 125 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 126 #define CONFIG_SYS_LBC_LBCR             0x00000000
 127
 128 /*
 129  * FLASH on the Local Bus
 130  */
 131 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 132 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 133
 134
 135
 136 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 137 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 138
 139 #undef CONFIG_SYS_FLASH_CHECKSUM
 140
 141 /*
 142  * Serial Port
 143  */
 144 #define CONFIG_SYS_NS16550_SERIAL
 145 #define CONFIG_SYS_NS16550_REG_SIZE     1
 146 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 147
 148 #define CONFIG_SYS_BAUDRATE_TABLE  \
 149                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 150
 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 153
 154 /* I2C */
 155 #define CONFIG_SYS_I2C
 156 #define CONFIG_SYS_I2C_FSL
 157 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 158 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 159 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 160 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 161
 162 /*
 163  * Config on-board EEPROM
 164  */
 165 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 167 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 168 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 169
 170 /*
 171  * General PCI
 172  * Addresses are mapped 1-1.
 173  */
 174 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 175 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 176 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 177 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 178 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 179 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 180 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 181 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 182 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 183
 184 #ifdef CONFIG_PCI
 185 #define CONFIG_PCI_INDIRECT_BRIDGE
 186 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 187
 188 #undef CONFIG_EEPRO100
 189 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 190 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 191
 192 #endif  /* CONFIG_PCI */
 193
 194 /*
 195  * QE UEC ethernet configuration
 196  */
 197 #define CONFIG_UEC_ETH
 198 #define CONFIG_ETHPRIME         "UEC0"
 199
 200 #define CONFIG_UEC_ETH1         /* ETH3 */
 201
 202 #ifdef CONFIG_UEC_ETH1
 203 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 204 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 205 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 206 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 207 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 208 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 209 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 210 #endif
 211
 212 #define CONFIG_UEC_ETH2         /* ETH4 */
 213
 214 #ifdef CONFIG_UEC_ETH2
 215 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 216 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 217 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 218 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 219 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 220 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 221 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 222 #endif
 223
 224 /*
 225  * Environment
 226  */
 227 #ifndef CONFIG_SYS_RAMBOOT
 228         #define CONFIG_ENV_ADDR         \
 229                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 230         #define CONFIG_ENV_SECT_SIZE    0x20000
 231         #define CONFIG_ENV_SIZE         0x2000
 232 #else
 233         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 234         #define CONFIG_ENV_SIZE         0x2000
 235 #endif
 236
 237 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 238 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 239
 240 /*
 241  * BOOTP options
 242  */
 243 #define CONFIG_BOOTP_BOOTFILESIZE
 244
 245 /*
 246  * Command line configuration.
 247  */
 248
 249 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 250
 251 /*
 252  * Miscellaneous configurable options
 253  */
 254 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 255
 256 /*
 257  * For booting Linux, the board info and command line data
 258  * have to be in the first 256 MB of memory, since this is
 259  * the maximum mapped by the Linux kernel during initialization.
 260  */
 261                                         /* Initial Memory map for Linux */
 262 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 263 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 264
 265 #if (CONFIG_CMD_KGDB)
 266 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 267 #endif
 268
 269 /*
 270  * Environment Configuration
 271  */
 272 #define CONFIG_ENV_OVERWRITE
 273
 274 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 275 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 276
 277 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 278  * (see CONFIG_SYS_I2C_EEPROM) */
 279                                         /* MAC address offset in I2C EEPROM */
 280 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 281
 282 #define CONFIG_NETDEV           "eth1"
 283
 284 #define CONFIG_HOSTNAME         "mpc8323erdb"
 285 #define CONFIG_ROOTPATH         "/nfsroot"
 286 #define CONFIG_BOOTFILE         "uImage"
 287                                 /* U-Boot image on TFTP server */
 288 #define CONFIG_UBOOTPATH        "u-boot.bin"
 289 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 290 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 291
 292                                 /* default location for tftp and bootm */
 293 #define CONFIG_LOADADDR         800000
 294
 295 #define CONFIG_EXTRA_ENV_SETTINGS \
 296         "netdev=" CONFIG_NETDEV "\0"                                    \
 297         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 298         "tftpflash=tftp $loadaddr $uboot;"                              \
 299                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 300                         " +$filesize; " \
 301                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 302                         " +$filesize; " \
 303                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 304                         " $filesize; "  \
 305                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 306                         " +$filesize; " \
 307                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 308                         " $filesize\0"  \
 309         "fdtaddr=780000\0"                                              \
 310         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 311         "ramdiskaddr=1000000\0"                                         \
 312         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 313         "console=ttyS0\0"                                               \
 314         "setbootargs=setenv bootargs "                                  \
 315                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 316         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 317                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 318                                                                 "$netdev:off "\
 319                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 320
 321 #define CONFIG_NFSBOOTCOMMAND                                           \
 322         "setenv rootdev /dev/nfs;"                                      \
 323         "run setbootargs;"                                              \
 324         "run setipargs;"                                                \
 325         "tftp $loadaddr $bootfile;"                                     \
 326         "tftp $fdtaddr $fdtfile;"                                       \
 327         "bootm $loadaddr - $fdtaddr"
 328
 329 #define CONFIG_RAMBOOTCOMMAND                                           \
 330         "setenv rootdev /dev/ram;"                                      \
 331         "run setbootargs;"                                              \
 332         "tftp $ramdiskaddr $ramdiskfile;"                               \
 333         "tftp $loadaddr $bootfile;"                                     \
 334         "tftp $fdtaddr $fdtfile;"                                       \
 335         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 336
 337 #endif  /* __CONFIG_H */