1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
11 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
12 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
14 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17 #ifndef CONFIG_SYS_MONITOR_BASE
18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
22 * High Level Configuration Options
24 #define CONFIG_E300 1 /* E300 family */
29 #define CONFIG_SYS_SICRH 0x00000000
30 #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
32 #define CONFIG_HWCONFIG
37 #define CONFIG_SYS_IMMR 0xE0000000
42 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
43 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
44 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
49 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
50 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
51 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
52 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
53 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
60 * Manually set up DDR parameters
61 * consist of two chips HY5PS12621BFP-C4 from HYNIX
63 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
64 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
65 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
66 | CSCONFIG_ODT_RD_NEVER \
67 | CSCONFIG_ODT_WR_ONLY_CURRENT \
68 | CSCONFIG_ROW_BIT_13 \
69 | CSCONFIG_COL_BIT_10)
71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
73 | (0 << TIMING_CFG0_WRT_SHIFT) \
74 | (0 << TIMING_CFG0_RRT_SHIFT) \
75 | (0 << TIMING_CFG0_WWT_SHIFT) \
76 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
77 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
78 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
79 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
81 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
82 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
83 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
84 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
85 | (6 << TIMING_CFG1_REFREC_SHIFT) \
86 | (2 << TIMING_CFG1_WRREC_SHIFT) \
87 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
88 | (2 << TIMING_CFG1_WRTORD_SHIFT))
90 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
91 | (4 << TIMING_CFG2_CPO_SHIFT) \
92 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
93 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
94 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
95 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
96 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
98 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
99 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
101 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
102 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
105 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
106 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
107 | (0x0232 << SDRAM_MODE_SD_SHIFT))
108 /* ODT 150ohm CL=3, AL=1 on SDRAM */
109 #define CONFIG_SYS_DDR_MODE2 0x00000000
114 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
115 #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
116 #define CONFIG_SYS_MEMTEST_END 0x00140000
119 * The reserved memory
121 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
122 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
125 * Initial RAM Base Address Setup
127 #define CONFIG_SYS_INIT_RAM_LOCK 1
128 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
129 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
130 #define CONFIG_SYS_GBL_DATA_OFFSET \
131 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
134 * Local Bus Configuration & Clock Setup
136 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
137 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
138 #define CONFIG_SYS_LBC_LBCR 0x00040000
139 #define CONFIG_FSL_ELBC 1
142 * FLASH on the Local Bus
144 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
146 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
147 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
149 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
150 /* 127 64KB sectors and 8 8KB top sectors per device */
151 #define CONFIG_SYS_MAX_FLASH_SECT 135
153 #undef CONFIG_SYS_FLASH_CHECKSUM
154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
158 * NAND Flash on the Local Bus
161 #ifdef CONFIG_NAND_SPL
162 #define CONFIG_SYS_NAND_BASE 0xFFF00000
164 #define CONFIG_SYS_NAND_BASE 0xE0600000
167 #define CONFIG_MTD_PARTITION
169 #define CONFIG_SYS_MAX_NAND_DEVICE 1
170 #define CONFIG_NAND_FSL_ELBC 1
171 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
172 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
174 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
175 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
176 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
177 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
178 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
180 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
181 | BR_PS_16 /* 16 bit port */ \
182 | BR_MS_GPCM /* MSEL = GPCM */ \
184 #define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
193 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
194 | BR_DECC_CHK_GEN /* Use HW ECC */ \
195 | BR_PS_8 /* 8 bit port */ \
196 | BR_MS_FCM /* MSEL = FCM */ \
198 #define CONFIG_SYS_OR1_PRELIM \
208 /* Still needed for spl_minimal.c */
209 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
210 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
212 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
213 !defined(CONFIG_NAND_SPL)
214 #define CONFIG_SYS_RAMBOOT
216 #undef CONFIG_SYS_RAMBOOT
222 #define CONFIG_SYS_NS16550_SERIAL
223 #define CONFIG_SYS_NS16550_REG_SIZE 1
224 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
226 #define CONFIG_SYS_BAUDRATE_TABLE \
227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
229 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
230 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
233 #define CONFIG_SYS_I2C
234 #define CONFIG_SYS_I2C_FSL
235 #define CONFIG_SYS_FSL_I2C_SPEED 400000
236 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
237 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
238 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
241 * Board info - revision and where boot from
243 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
246 * Config on-board RTC
248 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
249 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
253 * Addresses are mapped 1-1.
255 #define CONFIG_SYS_PCI_MEM_BASE 0x80000000
256 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
257 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
258 #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
259 #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
260 #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
261 #define CONFIG_SYS_PCI_IO_BASE 0x00000000
262 #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
263 #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
265 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
266 #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
267 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
269 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
270 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
271 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
272 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
273 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
274 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
275 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
276 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
277 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
279 #define CONFIG_SYS_PCIE2_BASE 0xC0000000
280 #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
281 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
282 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
283 #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
284 #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
285 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
286 #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
287 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
289 #define CONFIG_PCI_INDIRECT_BRIDGE
292 #define CONFIG_EEPRO100
293 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
294 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
296 #define CONFIG_HAS_FSL_DR_USB
297 #define CONFIG_SYS_SCCR_USBDRCM 3
299 #define CONFIG_USB_EHCI_FSL
300 #define CONFIG_USB_PHY_TYPE "utmi"
301 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
306 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
307 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
308 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
309 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
312 * TSEC ethernet configuration
314 #define CONFIG_TSEC1 1
315 #define CONFIG_TSEC1_NAME "eTSEC0"
316 #define CONFIG_TSEC2 1
317 #define CONFIG_TSEC2_NAME "eTSEC1"
318 #define TSEC1_PHY_ADDR 0
319 #define TSEC2_PHY_ADDR 1
320 #define TSEC1_PHYIDX 0
321 #define TSEC2_PHYIDX 0
322 #define TSEC1_FLAGS TSEC_GIGABIT
323 #define TSEC2_FLAGS TSEC_GIGABIT
325 /* Options are: eTSEC[0-1] */
326 #define CONFIG_ETHPRIME "eTSEC1"
331 #define CONFIG_SYS_SATA_MAX_DEVICE 2
333 #define CONFIG_SYS_SATA1_OFFSET 0x18000
334 #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
335 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
337 #define CONFIG_SYS_SATA2_OFFSET 0x19000
338 #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
339 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
341 #ifdef CONFIG_FSL_SATA
348 #if !defined(CONFIG_SYS_RAMBOOT)
349 #define CONFIG_ENV_ADDR \
350 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
351 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
352 #define CONFIG_ENV_SIZE 0x2000
354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
355 #define CONFIG_ENV_SIZE 0x2000
358 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
359 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
364 #define CONFIG_BOOTP_BOOTFILESIZE
367 * Command line configuration.
370 #undef CONFIG_WATCHDOG /* watchdog disabled */
373 * Miscellaneous configurable options
375 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
378 * For booting Linux, the board info and command line data
379 * have to be in the first 256 MB of memory, since this is
380 * the maximum mapped by the Linux kernel during initialization.
382 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
383 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
388 #define CONFIG_SYS_HID0_INIT 0x000000000
389 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
390 HID0_ENABLE_INSTRUCTION_CACHE | \
391 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
392 #define CONFIG_SYS_HID2 HID2_HBE
398 #if defined(CONFIG_CMD_KGDB)
399 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
403 * Environment Configuration
406 #define CONFIG_ENV_OVERWRITE
408 #if defined(CONFIG_TSEC_ENET)
409 #define CONFIG_HAS_ETH0
410 #define CONFIG_HAS_ETH1
413 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
415 #define CONFIG_EXTRA_ENV_SETTINGS \
417 "consoledev=ttyS0\0" \
418 "ramdiskaddr=1000000\0" \
419 "ramdiskfile=ramfs.83xx\0" \
421 "fdtfile=mpc8315erdb.dtb\0" \
422 "usb_phy_type=utmi\0" \
425 #define CONFIG_NFSBOOTCOMMAND \
426 "setenv bootargs root=/dev/nfs rw " \
427 "nfsroot=$serverip:$rootpath " \
428 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
430 "console=$consoledev,$baudrate $othbootargs;" \
431 "tftp $loadaddr $bootfile;" \
432 "tftp $fdtaddr $fdtfile;" \
433 "bootm $loadaddr - $fdtaddr"
435 #define CONFIG_RAMBOOTCOMMAND \
436 "setenv bootargs root=/dev/ram rw " \
437 "console=$consoledev,$baudrate $othbootargs;" \
438 "tftp $ramdiskaddr $ramdiskfile;" \
439 "tftp $loadaddr $bootfile;" \
440 "tftp $fdtaddr $fdtfile;" \
441 "bootm $loadaddr $ramdiskaddr $fdtaddr"
443 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
445 #endif /* __CONFIG_H */