include/configs/MPC8315ERDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   4  *
   5  * Dave Liu <daveliu@freescale.com>
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  12 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  13 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  14 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  15 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  16
  17 #ifndef CONFIG_SYS_MONITOR_BASE
  18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_E300             1 /* E300 family */
  25 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  26
  27 /*
  28  * System Clock Setup
  29  */
  30 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  31 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  32
  33 /*
  34  * Hardware Reset Configuration Word
  35  * if CLKIN is 66.66MHz, then
  36  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  37  */
  38 #define CONFIG_SYS_HRCW_LOW (\
  39         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  40         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  41         HRCWL_SVCOD_DIV_2 |\
  42         HRCWL_CSB_TO_CLKIN_2X1 |\
  43         HRCWL_CORE_TO_CSB_3X1)
  44 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  45         HRCWH_PCI_HOST |\
  46         HRCWH_PCI1_ARBITER_ENABLE |\
  47         HRCWH_CORE_ENABLE |\
  48         HRCWH_BOOTSEQ_DISABLE |\
  49         HRCWH_SW_WATCHDOG_DISABLE |\
  50         HRCWH_TSEC1M_IN_RGMII |\
  51         HRCWH_TSEC2M_IN_RGMII |\
  52         HRCWH_BIG_ENDIAN |\
  53         HRCWH_LALE_NORMAL)
  54
  55 #ifdef CONFIG_NAND_SPL
  56 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  57                        HRCWH_FROM_0XFFF00100 |\
  58                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  59                        HRCWH_RL_EXT_NAND)
  60 #else
  61 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  62                        HRCWH_FROM_0X00000100 |\
  63                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  64                        HRCWH_RL_EXT_LEGACY)
  65 #endif
  66
  67 /*
  68  * System IO Config
  69  */
  70 #define CONFIG_SYS_SICRH                0x00000000
  71 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  72
  73 #define CONFIG_HWCONFIG
  74
  75 /*
  76  * IMMR new address
  77  */
  78 #define CONFIG_SYS_IMMR         0xE0000000
  79
  80 /*
  81  * Arbiter Setup
  82  */
  83 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  84 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  85 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  91 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  92 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  93 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  94 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  95                                 | DDRCDR_PZ_LOZ \
  96                                 | DDRCDR_NZ_LOZ \
  97                                 | DDRCDR_ODT \
  98                                 | DDRCDR_Q_DRN)
  99                                 /* 0x7b880001 */
 100 /*
 101  * Manually set up DDR parameters
 102  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 103  */
 104 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 105 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 106 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 107                                 | CSCONFIG_ODT_RD_NEVER \
 108                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 109                                 | CSCONFIG_ROW_BIT_13 \
 110                                 | CSCONFIG_COL_BIT_10)
 111                                 /* 0x80010102 */
 112 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 113 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 114                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 115                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 116                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 117                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 118                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 119                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 120                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 121                                 /* 0x00220802 */
 122 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 123                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 124                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 125                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 126                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 127                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 128                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 129                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 130                                 /* 0x27256222 */
 131 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 132                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 133                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 134                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 135                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 136                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 137                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 138                                 /* 0x121048c5 */
 139 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 140                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 141                                 /* 0x03600100 */
 142 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 143                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 144                                 | SDRAM_CFG_DBW_32)
 145                                 /* 0x43080000 */
 146 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 147 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 148                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 149                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 150 #define CONFIG_SYS_DDR_MODE2    0x00000000
 151
 152 /*
 153  * Memory test
 154  */
 155 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 156 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 157 #define CONFIG_SYS_MEMTEST_END          0x00140000
 158
 159 /*
 160  * The reserved memory
 161  */
 162 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024) /* Reserve 512 kB for Mon */
 163 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 164
 165 /*
 166  * Initial RAM Base Address Setup
 167  */
 168 #define CONFIG_SYS_INIT_RAM_LOCK        1
 169 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 170 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 172                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 173
 174 /*
 175  * Local Bus Configuration & Clock Setup
 176  */
 177 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 178 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 179 #define CONFIG_SYS_LBC_LBCR             0x00040000
 180 #define CONFIG_FSL_ELBC         1
 181
 182 /*
 183  * FLASH on the Local Bus
 184  */
 185 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 186
 187 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 188 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 189
 190                                         /* Window base at flash base */
 191 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 192 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 193
 194 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 195                                         | BR_PS_16      /* 16 bit port */ \
 196                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 197                                         | BR_V)         /* valid */
 198 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 199                                         | OR_UPM_XAM \
 200                                         | OR_GPCM_CSNT \
 201                                         | OR_GPCM_ACS_DIV2 \
 202                                         | OR_GPCM_XACS \
 203                                         | OR_GPCM_SCY_15 \
 204                                         | OR_GPCM_TRLX_SET \
 205                                         | OR_GPCM_EHTR_SET \
 206                                         | OR_GPCM_EAD)
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 209 /* 127 64KB sectors and 8 8KB top sectors per device */
 210 #define CONFIG_SYS_MAX_FLASH_SECT       135
 211
 212 #undef CONFIG_SYS_FLASH_CHECKSUM
 213 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 214 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 215
 216 /*
 217  * NAND Flash on the Local Bus
 218  */
 219
 220 #ifdef CONFIG_NAND_SPL
 221 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 222 #else
 223 #define CONFIG_SYS_NAND_BASE            0xE0600000
 224 #endif
 225
 226 #define CONFIG_MTD_PARTITION
 227
 228 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 229 #define CONFIG_NAND_FSL_ELBC            1
 230 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 231 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 232
 233 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 234 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 235 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 236 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 237 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 238
 239 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 240                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 241                                 | BR_PS_8               /* 8 bit port */ \
 242                                 | BR_MS_FCM             /* MSEL = FCM */ \
 243                                 | BR_V)                 /* valid */
 244 #define CONFIG_SYS_NAND_OR_PRELIM       \
 245                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 246                                 | OR_FCM_CSCT \
 247                                 | OR_FCM_CST \
 248                                 | OR_FCM_CHT \
 249                                 | OR_FCM_SCY_1 \
 250                                 | OR_FCM_TRLX \
 251                                 | OR_FCM_EHTR)
 252                                 /* 0xFFFF8396 */
 253
 254 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 255 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 256 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 257 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 258
 259 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 260 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 261
 262 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 263 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 264
 265 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 266         !defined(CONFIG_NAND_SPL)
 267 #define CONFIG_SYS_RAMBOOT
 268 #else
 269 #undef CONFIG_SYS_RAMBOOT
 270 #endif
 271
 272 /*
 273  * Serial Port
 274  */
 275 #define CONFIG_SYS_NS16550_SERIAL
 276 #define CONFIG_SYS_NS16550_REG_SIZE     1
 277 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 278
 279 #define CONFIG_SYS_BAUDRATE_TABLE  \
 280                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 281
 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 284
 285 /* I2C */
 286 #define CONFIG_SYS_I2C
 287 #define CONFIG_SYS_I2C_FSL
 288 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 289 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 290 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 291 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 292
 293 /*
 294  * Board info - revision and where boot from
 295  */
 296 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 297
 298 /*
 299  * Config on-board RTC
 300  */
 301 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 302 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 303
 304 /*
 305  * General PCI
 306  * Addresses are mapped 1-1.
 307  */
 308 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 309 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 310 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 311 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 312 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 313 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 314 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 315 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 316 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 317
 318 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 319 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 320 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 321
 322 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 323 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 324 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 325 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 326 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 327 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 328 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 329 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 330 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 331
 332 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 333 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 334 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 335 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 336 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 337 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 338 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 339 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 340 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 341
 342 #define CONFIG_PCI_INDIRECT_BRIDGE
 343 #define CONFIG_PCIE
 344
 345 #define CONFIG_EEPRO100
 346 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 347 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 348
 349 #define CONFIG_HAS_FSL_DR_USB
 350 #define CONFIG_SYS_SCCR_USBDRCM         3
 351
 352 #define CONFIG_USB_EHCI_FSL
 353 #define CONFIG_USB_PHY_TYPE     "utmi"
 354 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 355
 356 /*
 357  * TSEC
 358  */
 359 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 360 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 361 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 362 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 363
 364 /*
 365  * TSEC ethernet configuration
 366  */
 367 #define CONFIG_TSEC1            1
 368 #define CONFIG_TSEC1_NAME       "eTSEC0"
 369 #define CONFIG_TSEC2            1
 370 #define CONFIG_TSEC2_NAME       "eTSEC1"
 371 #define TSEC1_PHY_ADDR          0
 372 #define TSEC2_PHY_ADDR          1
 373 #define TSEC1_PHYIDX            0
 374 #define TSEC2_PHYIDX            0
 375 #define TSEC1_FLAGS             TSEC_GIGABIT
 376 #define TSEC2_FLAGS             TSEC_GIGABIT
 377
 378 /* Options are: eTSEC[0-1] */
 379 #define CONFIG_ETHPRIME         "eTSEC1"
 380
 381 /*
 382  * SATA
 383  */
 384 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 385 #define CONFIG_SATA1
 386 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 387 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 388 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 389 #define CONFIG_SATA2
 390 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 391 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 392 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 393
 394 #ifdef CONFIG_FSL_SATA
 395 #define CONFIG_LBA48
 396 #endif
 397
 398 /*
 399  * Environment
 400  */
 401 #if !defined(CONFIG_SYS_RAMBOOT)
 402         #define CONFIG_ENV_ADDR         \
 403                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 404         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 405         #define CONFIG_ENV_SIZE         0x2000
 406 #else
 407         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 408         #define CONFIG_ENV_SIZE         0x2000
 409 #endif
 410
 411 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 412 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 413
 414 /*
 415  * BOOTP options
 416  */
 417 #define CONFIG_BOOTP_BOOTFILESIZE
 418
 419 /*
 420  * Command line configuration.
 421  */
 422
 423 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 424
 425 /*
 426  * Miscellaneous configurable options
 427  */
 428 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 429
 430 /*
 431  * For booting Linux, the board info and command line data
 432  * have to be in the first 256 MB of memory, since this is
 433  * the maximum mapped by the Linux kernel during initialization.
 434  */
 435 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 436 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 437
 438 /*
 439  * Core HID Setup
 440  */
 441 #define CONFIG_SYS_HID0_INIT    0x000000000
 442 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 443                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 444                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 445 #define CONFIG_SYS_HID2         HID2_HBE
 446
 447 /*
 448  * MMU Setup
 449  */
 450 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 451
 452 /* DDR: cache cacheable */
 453 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 454                                 | BATL_PP_RW \
 455                                 | BATL_MEMCOHERENCE)
 456 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 457                                 | BATU_BL_128M \
 458                                 | BATU_VS \
 459                                 | BATU_VP)
 460 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 461 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 462
 463 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 464 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 465                                 | BATL_PP_RW \
 466                                 | BATL_CACHEINHIBIT \
 467                                 | BATL_GUARDEDSTORAGE)
 468 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 469                                 | BATU_BL_8M \
 470                                 | BATU_VS \
 471                                 | BATU_VP)
 472 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 473 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 474
 475 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 476 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 477                                 | BATL_PP_RW \
 478                                 | BATL_MEMCOHERENCE)
 479 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 480                                 | BATU_BL_32M \
 481                                 | BATU_VS \
 482                                 | BATU_VP)
 483 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 484                                 | BATL_PP_RW \
 485                                 | BATL_CACHEINHIBIT \
 486                                 | BATL_GUARDEDSTORAGE)
 487 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 488
 489 /* Stack in dcache: cacheable, no memory coherence */
 490 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 491 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 492                                 | BATU_BL_128K \
 493                                 | BATU_VS \
 494                                 | BATU_VP)
 495 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 496 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 497
 498 /* PCI MEM space: cacheable */
 499 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 500                                 | BATL_PP_RW \
 501                                 | BATL_MEMCOHERENCE)
 502 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 503                                 | BATU_BL_256M \
 504                                 | BATU_VS \
 505                                 | BATU_VP)
 506 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 507 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 508
 509 /* PCI MMIO space: cache-inhibit and guarded */
 510 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 511                                 | BATL_PP_RW \
 512                                 | BATL_CACHEINHIBIT \
 513                                 | BATL_GUARDEDSTORAGE)
 514 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 515                                 | BATU_BL_256M \
 516                                 | BATU_VS \
 517                                 | BATU_VP)
 518 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 519 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 520
 521 #define CONFIG_SYS_IBAT6L       0
 522 #define CONFIG_SYS_IBAT6U       0
 523 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 524 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 525
 526 #define CONFIG_SYS_IBAT7L       0
 527 #define CONFIG_SYS_IBAT7U       0
 528 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 529 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 530
 531 #if defined(CONFIG_CMD_KGDB)
 532 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 533 #endif
 534
 535 /*
 536  * Environment Configuration
 537  */
 538
 539 #define CONFIG_ENV_OVERWRITE
 540
 541 #if defined(CONFIG_TSEC_ENET)
 542 #define CONFIG_HAS_ETH0
 543 #define CONFIG_HAS_ETH1
 544 #endif
 545
 546 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 547
 548 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 549         "netdev=eth0\0"                                                 \
 550         "consoledev=ttyS0\0"                                            \
 551         "ramdiskaddr=1000000\0"                                         \
 552         "ramdiskfile=ramfs.83xx\0"                                      \
 553         "fdtaddr=780000\0"                                              \
 554         "fdtfile=mpc8315erdb.dtb\0"                                     \
 555         "usb_phy_type=utmi\0"                                           \
 556         ""
 557
 558 #define CONFIG_NFSBOOTCOMMAND                                           \
 559         "setenv bootargs root=/dev/nfs rw "                             \
 560                 "nfsroot=$serverip:$rootpath "                          \
 561                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 562                                                         "$netdev:off "  \
 563                 "console=$consoledev,$baudrate $othbootargs;"           \
 564         "tftp $loadaddr $bootfile;"                                     \
 565         "tftp $fdtaddr $fdtfile;"                                       \
 566         "bootm $loadaddr - $fdtaddr"
 567
 568 #define CONFIG_RAMBOOTCOMMAND                                           \
 569         "setenv bootargs root=/dev/ram rw "                             \
 570                 "console=$consoledev,$baudrate $othbootargs;"           \
 571         "tftp $ramdiskaddr $ramdiskfile;"                               \
 572         "tftp $loadaddr $bootfile;"                                     \
 573         "tftp $fdtaddr $fdtfile;"                                       \
 574         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 575
 576 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 577
 578 #endif  /* __CONFIG_H */