include/configs/MPC8315ERDB.h

   1 /*
   2  * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
  13 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
  14 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
  15 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
  16 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
  17
  18 #ifndef CONFIG_SYS_TEXT_BASE
  19 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  20 #endif
  21
  22 #ifndef CONFIG_SYS_MONITOR_BASE
  23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  24 #endif
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_E300             1 /* E300 family */
  30 #define CONFIG_MPC831x          1 /* MPC831x CPU family */
  31 #define CONFIG_MPC8315          1 /* MPC8315 CPU specific */
  32 #define CONFIG_MPC8315ERDB      1 /* MPC8315ERDB board specific */
  33
  34 /*
  35  * System Clock Setup
  36  */
  37 #define CONFIG_83XX_CLKIN       66666667 /* in Hz */
  38 #define CONFIG_SYS_CLK_FREQ     CONFIG_83XX_CLKIN
  39
  40 /*
  41  * Hardware Reset Configuration Word
  42  * if CLKIN is 66.66MHz, then
  43  * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
  44  */
  45 #define CONFIG_SYS_HRCW_LOW (\
  46         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  47         HRCWL_DDR_TO_SCB_CLK_2X1 |\
  48         HRCWL_SVCOD_DIV_2 |\
  49         HRCWL_CSB_TO_CLKIN_2X1 |\
  50         HRCWL_CORE_TO_CSB_3X1)
  51 #define CONFIG_SYS_HRCW_HIGH_BASE (\
  52         HRCWH_PCI_HOST |\
  53         HRCWH_PCI1_ARBITER_ENABLE |\
  54         HRCWH_CORE_ENABLE |\
  55         HRCWH_BOOTSEQ_DISABLE |\
  56         HRCWH_SW_WATCHDOG_DISABLE |\
  57         HRCWH_TSEC1M_IN_RGMII |\
  58         HRCWH_TSEC2M_IN_RGMII |\
  59         HRCWH_BIG_ENDIAN |\
  60         HRCWH_LALE_NORMAL)
  61
  62 #ifdef CONFIG_NAND_SPL
  63 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  64                        HRCWH_FROM_0XFFF00100 |\
  65                        HRCWH_ROM_LOC_NAND_SP_8BIT |\
  66                        HRCWH_RL_EXT_NAND)
  67 #else
  68 #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
  69                        HRCWH_FROM_0X00000100 |\
  70                        HRCWH_ROM_LOC_LOCAL_16BIT |\
  71                        HRCWH_RL_EXT_LEGACY)
  72 #endif
  73
  74 /*
  75  * System IO Config
  76  */
  77 #define CONFIG_SYS_SICRH                0x00000000
  78 #define CONFIG_SYS_SICRL                0x00000000 /* 3.3V, no delay */
  79
  80 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
  81 #define CONFIG_HWCONFIG
  82
  83 /*
  84  * IMMR new address
  85  */
  86 #define CONFIG_SYS_IMMR         0xE0000000
  87
  88 /*
  89  * Arbiter Setup
  90  */
  91 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
  92 #define CONFIG_SYS_ACR_RPTCNT   3 /* Arbiter repeat count is 4 */
  93 #define CONFIG_SYS_SPCR_TSECEP  3 /* eTSEC emergency priority is highest */
  94
  95 /*
  96  * DDR Setup
  97  */
  98 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 102 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
 103                                 | DDRCDR_PZ_LOZ \
 104                                 | DDRCDR_NZ_LOZ \
 105                                 | DDRCDR_ODT \
 106                                 | DDRCDR_Q_DRN)
 107                                 /* 0x7b880001 */
 108 /*
 109  * Manually set up DDR parameters
 110  * consist of two chips HY5PS12621BFP-C4 from HYNIX
 111  */
 112 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
 113 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
 114 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
 115                                 | CSCONFIG_ODT_RD_NEVER \
 116                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
 117                                 | CSCONFIG_ROW_BIT_13 \
 118                                 | CSCONFIG_COL_BIT_10)
 119                                 /* 0x80010102 */
 120 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 121 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
 122                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
 123                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
 124                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
 125                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 126                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 127                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 128                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 129                                 /* 0x00220802 */
 130 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
 131                                 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 132                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
 133                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
 134                                 | (6 << TIMING_CFG1_REFREC_SHIFT) \
 135                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
 136                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 137                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
 138                                 /* 0x27256222 */
 139 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
 140                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
 141                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 142                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 143                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 144                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 145                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
 146                                 /* 0x121048c5 */
 147 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
 148                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 149                                 /* 0x03600100 */
 150 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
 151                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
 152                                 | SDRAM_CFG_DBW_32)
 153                                 /* 0x43080000 */
 154 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
 155 #define CONFIG_SYS_DDR_MODE             ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
 156                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
 157                                 /* ODT 150ohm CL=3, AL=1 on SDRAM */
 158 #define CONFIG_SYS_DDR_MODE2    0x00000000
 159
 160 /*
 161  * Memory test
 162  */
 163 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 164 #define CONFIG_SYS_MEMTEST_START        0x00040000 /* memtest region */
 165 #define CONFIG_SYS_MEMTEST_END          0x00140000
 166
 167 /*
 168  * The reserved memory
 169  */
 170 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 171 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 172
 173 /*
 174  * Initial RAM Base Address Setup
 175  */
 176 #define CONFIG_SYS_INIT_RAM_LOCK        1
 177 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 178 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 179 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 180                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 181
 182 /*
 183  * Local Bus Configuration & Clock Setup
 184  */
 185 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 186 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 187 #define CONFIG_SYS_LBC_LBCR             0x00040000
 188 #define CONFIG_FSL_ELBC         1
 189
 190 /*
 191  * FLASH on the Local Bus
 192  */
 193 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 194 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
 195 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 196
 197 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 198 #define CONFIG_SYS_FLASH_SIZE           8       /* FLASH size is 8M */
 199 #define CONFIG_SYS_FLASH_PROTECTION     1       /* Use h/w Flash protection. */
 200
 201                                         /* Window base at flash base */
 202 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 203 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 204
 205 #define CONFIG_SYS_NOR_BR_PRELIM        (CONFIG_SYS_FLASH_BASE \
 206                                         | BR_PS_16      /* 16 bit port */ \
 207                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 208                                         | BR_V)         /* valid */
 209 #define CONFIG_SYS_NOR_OR_PRELIM        (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 210                                         | OR_UPM_XAM \
 211                                         | OR_GPCM_CSNT \
 212                                         | OR_GPCM_ACS_DIV2 \
 213                                         | OR_GPCM_XACS \
 214                                         | OR_GPCM_SCY_15 \
 215                                         | OR_GPCM_TRLX_SET \
 216                                         | OR_GPCM_EHTR_SET \
 217                                         | OR_GPCM_EAD)
 218
 219 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 220 /* 127 64KB sectors and 8 8KB top sectors per device */
 221 #define CONFIG_SYS_MAX_FLASH_SECT       135
 222
 223 #undef CONFIG_SYS_FLASH_CHECKSUM
 224 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 225 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 226
 227 /*
 228  * NAND Flash on the Local Bus
 229  */
 230
 231 #ifdef CONFIG_NAND_SPL
 232 #define CONFIG_SYS_NAND_BASE            0xFFF00000
 233 #else
 234 #define CONFIG_SYS_NAND_BASE            0xE0600000
 235 #endif
 236
 237 #define CONFIG_MTD_DEVICE
 238 #define CONFIG_MTD_PARTITION
 239 #define CONFIG_CMD_MTDPARTS
 240 #define MTDIDS_DEFAULT                  "nand0=e0600000.flash"
 241 #define MTDPARTS_DEFAULT                \
 242         "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
 243
 244 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 245 #define CONFIG_MTD_NAND_VERIFY_WRITE    1
 246 #define CONFIG_CMD_NAND                 1
 247 #define CONFIG_NAND_FSL_ELBC            1
 248 #define CONFIG_SYS_NAND_BLOCK_SIZE      16384
 249 #define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 250
 251 #define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
 252 #define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
 253 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 254 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 255 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 256
 257 #define CONFIG_SYS_NAND_BR_PRELIM       (CONFIG_SYS_NAND_BASE \
 258                                 | BR_DECC_CHK_GEN       /* Use HW ECC */ \
 259                                 | BR_PS_8               /* 8 bit port */ \
 260                                 | BR_MS_FCM             /* MSEL = FCM */ \
 261                                 | BR_V)                 /* valid */
 262 #define CONFIG_SYS_NAND_OR_PRELIM       \
 263                                 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
 264                                 | OR_FCM_CSCT \
 265                                 | OR_FCM_CST \
 266                                 | OR_FCM_CHT \
 267                                 | OR_FCM_SCY_1 \
 268                                 | OR_FCM_TRLX \
 269                                 | OR_FCM_EHTR)
 270                                 /* 0xFFFF8396 */
 271
 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
 274 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
 275 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
 276
 277 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_NAND_BASE
 278 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_32KB)
 279
 280 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
 281 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
 282
 283 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
 284         !defined(CONFIG_NAND_SPL)
 285 #define CONFIG_SYS_RAMBOOT
 286 #else
 287 #undef CONFIG_SYS_RAMBOOT
 288 #endif
 289
 290 /*
 291  * Serial Port
 292  */
 293 #define CONFIG_CONS_INDEX       1
 294 #define CONFIG_SYS_NS16550
 295 #define CONFIG_SYS_NS16550_SERIAL
 296 #define CONFIG_SYS_NS16550_REG_SIZE     1
 297 #define CONFIG_SYS_NS16550_CLK          (CONFIG_83XX_CLKIN * 2)
 298
 299 #define CONFIG_SYS_BAUDRATE_TABLE  \
 300                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 301
 302 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 303 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 304
 305 /* Use the HUSH parser */
 306 #define CONFIG_SYS_HUSH_PARSER
 307
 308 /* Pass open firmware flat tree */
 309 #define CONFIG_OF_LIBFDT        1
 310 #define CONFIG_OF_BOARD_SETUP   1
 311 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 312
 313 /* I2C */
 314 #define CONFIG_SYS_I2C
 315 #define CONFIG_SYS_I2C_FSL
 316 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 317 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 318 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 319 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 320
 321 /*
 322  * Board info - revision and where boot from
 323  */
 324 #define CONFIG_SYS_I2C_PCF8574A_ADDR    0x39
 325
 326 /*
 327  * Config on-board RTC
 328  */
 329 #define CONFIG_RTC_DS1337       /* ds1339 on board, use ds1337 rtc via i2c */
 330 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
 331
 332 /*
 333  * General PCI
 334  * Addresses are mapped 1-1.
 335  */
 336 #define CONFIG_SYS_PCI_MEM_BASE         0x80000000
 337 #define CONFIG_SYS_PCI_MEM_PHYS         CONFIG_SYS_PCI_MEM_BASE
 338 #define CONFIG_SYS_PCI_MEM_SIZE         0x10000000 /* 256M */
 339 #define CONFIG_SYS_PCI_MMIO_BASE        0x90000000
 340 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 341 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000 /* 256M */
 342 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 343 #define CONFIG_SYS_PCI_IO_PHYS          0xE0300000
 344 #define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */
 345
 346 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL    CONFIG_SYS_SDRAM_BASE
 347 #define CONFIG_SYS_PCI_SLV_MEM_BUS      0x00000000
 348 #define CONFIG_SYS_PCI_SLV_MEM_SIZE     0x80000000
 349
 350 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 351 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 352 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 353 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 354 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 355 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 356 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 357 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 358 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 359
 360 #define CONFIG_SYS_PCIE2_BASE           0xC0000000
 361 #define CONFIG_SYS_PCIE2_MEM_BASE       0xC0000000
 362 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xC0000000
 363 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000
 364 #define CONFIG_SYS_PCIE2_CFG_BASE       0xD0000000
 365 #define CONFIG_SYS_PCIE2_CFG_SIZE       0x01000000
 366 #define CONFIG_SYS_PCIE2_IO_BASE        0x00000000
 367 #define CONFIG_SYS_PCIE2_IO_PHYS        0xD1000000
 368 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000
 369
 370 #define CONFIG_PCI
 371 #define CONFIG_PCI_INDIRECT_BRIDGE
 372 #define CONFIG_PCIE
 373
 374 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 375
 376 #define CONFIG_EEPRO100
 377 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 378 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 379
 380 #define CONFIG_HAS_FSL_DR_USB
 381 #define CONFIG_SYS_SCCR_USBDRCM         3
 382
 383 #define CONFIG_CMD_USB
 384 #define CONFIG_USB_STORAGE
 385 #define CONFIG_USB_EHCI
 386 #define CONFIG_USB_EHCI_FSL
 387 #define CONFIG_USB_PHY_TYPE     "utmi"
 388 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 389
 390 /*
 391  * TSEC
 392  */
 393 #define CONFIG_TSEC_ENET        /* TSEC ethernet support */
 394 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 395 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 396 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 397 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 398
 399 /*
 400  * TSEC ethernet configuration
 401  */
 402 #define CONFIG_MII              1 /* MII PHY management */
 403 #define CONFIG_TSEC1            1
 404 #define CONFIG_TSEC1_NAME       "eTSEC0"
 405 #define CONFIG_TSEC2            1
 406 #define CONFIG_TSEC2_NAME       "eTSEC1"
 407 #define TSEC1_PHY_ADDR          0
 408 #define TSEC2_PHY_ADDR          1
 409 #define TSEC1_PHYIDX            0
 410 #define TSEC2_PHYIDX            0
 411 #define TSEC1_FLAGS             TSEC_GIGABIT
 412 #define TSEC2_FLAGS             TSEC_GIGABIT
 413
 414 /* Options are: eTSEC[0-1] */
 415 #define CONFIG_ETHPRIME         "eTSEC1"
 416
 417 /*
 418  * SATA
 419  */
 420 #define CONFIG_LIBATA
 421 #define CONFIG_FSL_SATA
 422
 423 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 424 #define CONFIG_SATA1
 425 #define CONFIG_SYS_SATA1_OFFSET 0x18000
 426 #define CONFIG_SYS_SATA1        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 427 #define CONFIG_SYS_SATA1_FLAGS  FLAGS_DMA
 428 #define CONFIG_SATA2
 429 #define CONFIG_SYS_SATA2_OFFSET 0x19000
 430 #define CONFIG_SYS_SATA2        (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 431 #define CONFIG_SYS_SATA2_FLAGS  FLAGS_DMA
 432
 433 #ifdef CONFIG_FSL_SATA
 434 #define CONFIG_LBA48
 435 #define CONFIG_CMD_SATA
 436 #define CONFIG_DOS_PARTITION
 437 #define CONFIG_CMD_EXT2
 438 #endif
 439
 440 /*
 441  * Environment
 442  */
 443 #if !defined(CONFIG_SYS_RAMBOOT)
 444         #define CONFIG_ENV_IS_IN_FLASH  1
 445         #define CONFIG_ENV_ADDR         \
 446                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 447         #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
 448         #define CONFIG_ENV_SIZE         0x2000
 449 #else
 450         #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
 451         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 452         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 453         #define CONFIG_ENV_SIZE         0x2000
 454 #endif
 455
 456 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 457 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 458
 459 /*
 460  * BOOTP options
 461  */
 462 #define CONFIG_BOOTP_BOOTFILESIZE
 463 #define CONFIG_BOOTP_BOOTPATH
 464 #define CONFIG_BOOTP_GATEWAY
 465 #define CONFIG_BOOTP_HOSTNAME
 466
 467 /*
 468  * Command line configuration.
 469  */
 470 #include <config_cmd_default.h>
 471
 472 #define CONFIG_CMD_PING
 473 #define CONFIG_CMD_I2C
 474 #define CONFIG_CMD_MII
 475 #define CONFIG_CMD_DATE
 476 #define CONFIG_CMD_PCI
 477
 478 #if defined(CONFIG_SYS_RAMBOOT)
 479     #undef CONFIG_CMD_SAVEENV
 480     #undef CONFIG_CMD_LOADS
 481 #endif
 482
 483 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 484 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 485
 486 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 487
 488 /*
 489  * Miscellaneous configurable options
 490  */
 491 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 492 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 493
 494 #if defined(CONFIG_CMD_KGDB)
 495         #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 496 #else
 497         #define CONFIG_SYS_CBSIZE       256 /* Console I/O Buffer Size */
 498 #endif
 499
 500                                 /* Print Buffer Size */
 501 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 502 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 503                                 /* Boot Argument Buffer Size */
 504 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 505
 506 /*
 507  * For booting Linux, the board info and command line data
 508  * have to be in the first 256 MB of memory, since this is
 509  * the maximum mapped by the Linux kernel during initialization.
 510  */
 511 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 512
 513 /*
 514  * Core HID Setup
 515  */
 516 #define CONFIG_SYS_HID0_INIT    0x000000000
 517 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 518                                  HID0_ENABLE_INSTRUCTION_CACHE | \
 519                                  HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
 520 #define CONFIG_SYS_HID2         HID2_HBE
 521
 522 /*
 523  * MMU Setup
 524  */
 525 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 526
 527 /* DDR: cache cacheable */
 528 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 529                                 | BATL_PP_RW \
 530                                 | BATL_MEMCOHERENCE)
 531 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 532                                 | BATU_BL_128M \
 533                                 | BATU_VS \
 534                                 | BATU_VP)
 535 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 536 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 537
 538 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 539 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 540                                 | BATL_PP_RW \
 541                                 | BATL_CACHEINHIBIT \
 542                                 | BATL_GUARDEDSTORAGE)
 543 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 544                                 | BATU_BL_8M \
 545                                 | BATU_VS \
 546                                 | BATU_VP)
 547 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 548 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 549
 550 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 551 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 552                                 | BATL_PP_RW \
 553                                 | BATL_MEMCOHERENCE)
 554 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 555                                 | BATU_BL_32M \
 556                                 | BATU_VS \
 557                                 | BATU_VP)
 558 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 559                                 | BATL_PP_RW \
 560                                 | BATL_CACHEINHIBIT \
 561                                 | BATL_GUARDEDSTORAGE)
 562 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 563
 564 /* Stack in dcache: cacheable, no memory coherence */
 565 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 566 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_INIT_RAM_ADDR \
 567                                 | BATU_BL_128K \
 568                                 | BATU_VS \
 569                                 | BATU_VP)
 570 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 571 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 572
 573 /* PCI MEM space: cacheable */
 574 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI_MEM_PHYS \
 575                                 | BATL_PP_RW \
 576                                 | BATL_MEMCOHERENCE)
 577 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI_MEM_PHYS \
 578                                 | BATU_BL_256M \
 579                                 | BATU_VS \
 580                                 | BATU_VP)
 581 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 582 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 583
 584 /* PCI MMIO space: cache-inhibit and guarded */
 585 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI_MMIO_PHYS \
 586                                 | BATL_PP_RW \
 587                                 | BATL_CACHEINHIBIT \
 588                                 | BATL_GUARDEDSTORAGE)
 589 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI_MMIO_PHYS \
 590                                 | BATU_BL_256M \
 591                                 | BATU_VS \
 592                                 | BATU_VP)
 593 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 594 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 595
 596 #define CONFIG_SYS_IBAT6L       0
 597 #define CONFIG_SYS_IBAT6U       0
 598 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 599 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 600
 601 #define CONFIG_SYS_IBAT7L       0
 602 #define CONFIG_SYS_IBAT7U       0
 603 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 604 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 605
 606 #if defined(CONFIG_CMD_KGDB)
 607 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 608 #endif
 609
 610 /*
 611  * Environment Configuration
 612  */
 613
 614 #define CONFIG_ENV_OVERWRITE
 615
 616 #if defined(CONFIG_TSEC_ENET)
 617 #define CONFIG_HAS_ETH0
 618 #define CONFIG_HAS_ETH1
 619 #endif
 620
 621 #define CONFIG_BAUDRATE 115200
 622
 623 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 624
 625 #define CONFIG_BOOTDELAY 6      /* -1 disables auto-boot */
 626 #undef CONFIG_BOOTARGS          /* the boot command will set bootargs */
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 629         "netdev=eth0\0"                                                 \
 630         "consoledev=ttyS0\0"                                            \
 631         "ramdiskaddr=1000000\0"                                         \
 632         "ramdiskfile=ramfs.83xx\0"                                      \
 633         "fdtaddr=780000\0"                                              \
 634         "fdtfile=mpc8315erdb.dtb\0"                                     \
 635         "usb_phy_type=utmi\0"                                           \
 636         ""
 637
 638 #define CONFIG_NFSBOOTCOMMAND                                           \
 639         "setenv bootargs root=/dev/nfs rw "                             \
 640                 "nfsroot=$serverip:$rootpath "                          \
 641                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 642                                                         "$netdev:off "  \
 643                 "console=$consoledev,$baudrate $othbootargs;"           \
 644         "tftp $loadaddr $bootfile;"                                     \
 645         "tftp $fdtaddr $fdtfile;"                                       \
 646         "bootm $loadaddr - $fdtaddr"
 647
 648 #define CONFIG_RAMBOOTCOMMAND                                           \
 649         "setenv bootargs root=/dev/ram rw "                             \
 650                 "console=$consoledev,$baudrate $othbootargs;"           \
 651         "tftp $ramdiskaddr $ramdiskfile;"                               \
 652         "tftp $loadaddr $bootfile;"                                     \
 653         "tftp $fdtaddr $fdtfile;"                                       \
 654         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 655
 656
 657 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
 658
 659 #endif  /* __CONFIG_H */